1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <cdefs.h> 8 #include <stdint.h> 9 10 #include <common/debug.h> 11 #include <drivers/clk.h> 12 #include <drivers/st/regulator_fixed.h> 13 #include <lib/fconf/fconf.h> 14 #include <lib/fconf/fconf_dyn_cfg_getter.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 19 #include <platform_def.h> 20 #include <stm32mp_common.h> 21 #include <stm32mp_dt.h> 22 23 #define BOOT_CTX_ADDR 0x0e000020UL 24 25 static void print_reset_reason(void) 26 { 27 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR); 28 29 if (rstsr == 0U) { 30 WARN("Reset reason unknown\n"); 31 return; 32 } 33 34 INFO("Reset reason (0x%x):\n", rstsr); 35 36 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) { 37 if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) { 38 INFO("System exits from Standby for CA35\n"); 39 return; 40 } 41 42 if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) { 43 INFO("D1 domain exits from DStandby\n"); 44 return; 45 } 46 } 47 48 if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) { 49 INFO(" Power-on Reset (rst_por)\n"); 50 return; 51 } 52 53 if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) { 54 INFO(" Brownout Reset (rst_bor)\n"); 55 return; 56 } 57 58 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) { 59 INFO(" System reset (SYSRST) by M33\n"); 60 return; 61 } 62 63 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) { 64 INFO(" System reset (SYSRST) by A35\n"); 65 return; 66 } 67 68 if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) { 69 INFO(" Clock failure on HSE\n"); 70 return; 71 } 72 73 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) { 74 INFO(" IWDG1 system reset (rst_iwdg1)\n"); 75 return; 76 } 77 78 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) { 79 INFO(" IWDG2 system reset (rst_iwdg2)\n"); 80 return; 81 } 82 83 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) { 84 INFO(" IWDG3 system reset (rst_iwdg3)\n"); 85 return; 86 } 87 88 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) { 89 INFO(" IWDG4 system reset (rst_iwdg4)\n"); 90 return; 91 } 92 93 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) { 94 INFO(" IWDG5 system reset (rst_iwdg5)\n"); 95 return; 96 } 97 98 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) { 99 INFO(" A35 processor core 1 reset\n"); 100 return; 101 } 102 103 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) { 104 INFO(" Pad Reset from NRST\n"); 105 return; 106 } 107 108 if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) { 109 INFO(" Reset due to a failure of VDD_CORE\n"); 110 return; 111 } 112 113 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) { 114 INFO(" A35 processor reset\n"); 115 return; 116 } 117 118 ERROR(" Unidentified reset reason\n"); 119 } 120 121 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 122 u_register_t arg1 __unused, 123 u_register_t arg2 __unused, 124 u_register_t arg3 __unused) 125 { 126 stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR); 127 } 128 129 void bl2_platform_setup(void) 130 { 131 } 132 133 static void reset_backup_domain(void) 134 { 135 uintptr_t pwr_base = stm32mp_pwr_base(); 136 uintptr_t rcc_base = stm32mp_rcc_base(); 137 138 /* 139 * Disable the backup domain write protection. 140 * The protection is enable at each reset by hardware 141 * and must be disabled by software. 142 */ 143 mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P); 144 145 while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) { 146 ; 147 } 148 149 /* Reset backup domain on cold boot cases */ 150 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) { 151 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 152 153 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { 154 ; 155 } 156 157 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 158 } 159 } 160 161 void bl2_el3_plat_arch_setup(void) 162 { 163 const char *board_model; 164 boot_api_context_t *boot_context = 165 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 166 167 if (stm32_otp_probe() != 0U) { 168 EARLY_ERROR("OTP probe failed\n"); 169 panic(); 170 } 171 172 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 173 BL_CODE_END - BL_CODE_BASE, 174 MT_CODE | MT_SECURE); 175 176 configure_mmu(); 177 178 /* Prevent corruption of preloaded Device Tree */ 179 mmap_add_dynamic_region(DTB_BASE, DTB_BASE, 180 DTB_LIMIT - DTB_BASE, 181 MT_RO_DATA | MT_SECURE); 182 183 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 184 panic(); 185 } 186 187 reset_backup_domain(); 188 189 if (stm32mp2_clk_init() < 0) { 190 panic(); 191 } 192 193 stm32_save_boot_info(boot_context); 194 195 if (stm32mp_uart_console_setup() != 0) { 196 goto skip_console_init; 197 } 198 199 stm32mp_print_cpuinfo(); 200 201 board_model = dt_get_board_model(); 202 if (board_model != NULL) { 203 NOTICE("Model: %s\n", board_model); 204 } 205 206 stm32mp_print_boardinfo(); 207 208 print_reset_reason(); 209 210 skip_console_init: 211 if (fixed_regulator_register() != 0) { 212 panic(); 213 } 214 215 fconf_populate("TB_FW", STM32MP_DTB_BASE); 216 217 stm32mp_io_setup(); 218 } 219