1 /* 2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <bl31/bl31.h> 12 #include <common/debug.h> 13 #include <drivers/arm/gicv3.h> 14 #include <drivers/console.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/mmio.h> 18 #include <plat/common/platform.h> 19 #include <platform_def.h> 20 #include <pmu.h> 21 22 #include <cpus_on_fixed_addr.h> 23 #include <plat_pm_helpers.h> 24 #include <plat_private.h> 25 #include <pm_pd_regs.h> 26 #include <rockchip_sip_svc.h> 27 #include <secure.h> 28 #include <soc.h> 29 30 #define PSRAM_SP_TOP ((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf) 31 #define NONBOOT_CPUS_OFF_LOOP (500000) 32 33 #define DSUGRF_REG_CNT (0x78 / 4 + 1) 34 #define BCORE_GRF_REG_CNT (0x30 / 4 + 1) 35 #define LCORE_GRF_REG_CNT (0x30 / 4 + 1) 36 37 #define CENTER_GRF_REG_CNT (0x20 / 4 + 1) 38 39 static struct psram_data_t *psram_sleep_cfg = 40 (struct psram_data_t *)&sys_sleep_flag_sram; 41 42 static int8_t pd_repair_map[] = { 43 [PD_GPU] = PD_RPR_GPU, 44 [PD_NPU] = -1, 45 [PD_VCODEC] = -1, 46 [PD_NPUTOP] = PD_RPR_NPUTOP, 47 [PD_NPU1] = PD_RPR_NPU1, 48 [PD_NPU2] = PD_RPR_NPU2, 49 [PD_VENC0] = PD_RPR_VENC0, 50 [PD_VENC1] = PD_RPR_VENC1, 51 [PD_RKVDEC0] = PD_RPR_RKVDEC0, 52 [PD_RKVDEC1] = PD_RPR_RKVDEC1, 53 [PD_VDPU] = PD_RPR_VDPU, 54 [PD_RGA30] = PD_RPR_RGA30, 55 [PD_AV1] = PD_RPR_AV1, 56 [PD_VI] = PD_RPR_VI, 57 [PD_FEC] = PD_RPR_FEC, 58 [PD_ISP1] = PD_RPR_ISP1, 59 [PD_RGA31] = PD_RPR_RGA31, 60 [PD_VOP] = PD_RPR_VOP, 61 [PD_VO0] = PD_RPR_VO0, 62 [PD_VO1] = PD_RPR_VO1, 63 [PD_AUDIO] = PD_RPR_AUDIO, 64 [PD_PHP] = PD_RPR_PHP, 65 [PD_GMAC] = PD_RPR_GMAC, 66 [PD_PCIE] = PD_RPR_PCIE, 67 [PD_NVM] = -1, 68 [PD_NVM0] = PD_RPR_NVM0, 69 [PD_SDIO] = PD_RPR_SDIO, 70 [PD_USB] = PD_RPR_USB, 71 [PD_SECURE] = -1, 72 [PD_SDMMC] = PD_RPR_SDMMC, 73 [PD_CRYPTO] = PD_RPR_CRYPTO, 74 [PD_CENTER] = PD_RPR_CENTER, 75 [PD_DDR01] = PD_RPR_DDR01, 76 [PD_DDR23] = PD_RPR_DDR23, 77 }; 78 79 struct rk3588_sleep_ddr_data { 80 uint32_t gpio0a_iomux_l, gpio0a_iomux_h, gpio0b_iomux_l; 81 uint32_t pmu_pd_st0, bus_idle_st0, qch_pwr_st; 82 uint32_t pmu2_vol_gate_con[3], pmu2_submem_gate_sft_con0; 83 uint32_t pmu2_bisr_con0; 84 uint32_t cpll_con0; 85 uint32_t cru_mode_con, busscru_mode_con; 86 uint32_t bussgrf_soc_con7; 87 uint32_t pmu0grf_soc_con0, pmu0grf_soc_con1, pmu0grf_soc_con3; 88 uint32_t pmu1grf_soc_con2, pmu1grf_soc_con7, pmu1grf_soc_con8, pmu1grf_soc_con9; 89 uint32_t pmu0sgrf_soc_con1; 90 uint32_t pmu1sgrf_soc_con14; 91 uint32_t ddrgrf_chn_con0[4], ddrgrf_chn_con1[4], 92 ddrgrf_chn_con2[4], pmu1_ddr_pwr_sft_con[4]; 93 uint32_t pmu1cru_clksel_con1; 94 }; 95 96 static struct rk3588_sleep_ddr_data ddr_data; 97 98 struct rk3588_sleep_pmusram_data { 99 uint32_t dsusgrf_soc_con[DSUSGRF_SOC_CON_CNT], 100 dsusgrf_ddr_hash_con[DSUSGRF_DDR_HASH_CON_CNT]; 101 uint32_t dsu_ddr_fw_rgn_reg[FIREWALL_DSU_RGN_CNT], 102 dsu_ddr_fw_mst_reg[FIREWALL_DSU_MST_CNT], 103 dsu_ddr_fw_con_reg[FIREWALL_DSU_CON_CNT]; 104 uint32_t busioc_gpio0b_iomux_h; 105 }; 106 107 static __pmusramdata struct rk3588_sleep_pmusram_data pmusram_data; 108 109 static __pmusramfunc void dsu_restore_early(void) 110 { 111 int i; 112 113 /* dsusgrf */ 114 for (i = 0; i < DSUSGRF_SOC_CON_CNT; i++) 115 mmio_write_32(DSUSGRF_BASE + DSUSGRF_SOC_CON(i), 116 WITH_16BITS_WMSK(pmusram_data.dsusgrf_soc_con[i])); 117 118 for (i = 0; i < DSUSGRF_DDR_HASH_CON_CNT; i++) 119 mmio_write_32(DSUSGRF_BASE + DSUSGRF_DDR_HASH_CON(i), 120 pmusram_data.dsusgrf_ddr_hash_con[i]); 121 122 /* dsu ddr firewall */ 123 for (i = 0; i < FIREWALL_DSU_RGN_CNT; i++) 124 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(i), 125 pmusram_data.dsu_ddr_fw_rgn_reg[i]); 126 127 for (i = 0; i < FIREWALL_DSU_MST_CNT; i++) 128 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(i), 129 pmusram_data.dsu_ddr_fw_mst_reg[i]); 130 131 for (i = 0; i < FIREWALL_DSU_CON_CNT; i++) 132 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i), 133 pmusram_data.dsu_ddr_fw_con_reg[i]); 134 } 135 136 static __pmusramfunc void ddr_resume(void) 137 { 138 dsu_restore_early(); 139 } 140 141 static void dsu_core_save(void) 142 { 143 int i; 144 145 /* dsusgrf */ 146 for (i = 0; i < DSUSGRF_SOC_CON_CNT; i++) 147 pmusram_data.dsusgrf_soc_con[i] = 148 mmio_read_32(DSUSGRF_BASE + DSUSGRF_SOC_CON(i)); 149 150 for (i = 0; i < DSUSGRF_DDR_HASH_CON_CNT; i++) 151 pmusram_data.dsusgrf_ddr_hash_con[i] = 152 mmio_read_32(DSUSGRF_BASE + DSUSGRF_DDR_HASH_CON(i)); 153 154 /* dsu ddr firewall */ 155 for (i = 0; i < FIREWALL_DSU_RGN_CNT; i++) 156 pmusram_data.dsu_ddr_fw_rgn_reg[i] = 157 mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(i)); 158 159 for (i = 0; i < FIREWALL_DSU_MST_CNT; i++) 160 pmusram_data.dsu_ddr_fw_mst_reg[i] = 161 mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(i)); 162 163 for (i = 0; i < FIREWALL_DSU_CON_CNT; i++) 164 pmusram_data.dsu_ddr_fw_con_reg[i] = 165 mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i)); 166 167 pd_dsu_core_save(); 168 } 169 170 static void dsu_core_restore(void) 171 { 172 pd_dsu_core_restore(); 173 } 174 175 static uint32_t clk_save[CRU_CLKGATE_CON_CNT + PHPCRU_CLKGATE_CON_CNT + 176 SECURECRU_CLKGATE_CON_CNT + PMU1CRU_CLKGATE_CON_CNT]; 177 178 void clk_gate_con_save(void) 179 { 180 int i, j = 0; 181 182 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) 183 clk_save[j] = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); 184 185 clk_save[j] = mmio_read_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON); 186 187 for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++, j++) 188 clk_save[j] = mmio_read_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i)); 189 190 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) 191 clk_save[j] = mmio_read_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i)); 192 } 193 194 void clk_gate_con_disable(void) 195 { 196 int i; 197 198 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++) 199 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); 200 201 mmio_write_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON, 0xffff0000); 202 203 for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++) 204 mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), 0xffff0000); 205 206 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++) 207 mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); 208 } 209 210 void clk_gate_con_restore(void) 211 { 212 int i, j = 0; 213 214 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) 215 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 216 WITH_16BITS_WMSK(clk_save[j])); 217 218 mmio_write_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON, 219 WITH_16BITS_WMSK(clk_save[j])); 220 221 for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++, j++) 222 mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), 223 WITH_16BITS_WMSK(clk_save[j])); 224 225 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) 226 mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), 227 WITH_16BITS_WMSK(clk_save[j])); 228 } 229 230 static void pmu_bus_idle_req(uint32_t bus, uint32_t state) 231 { 232 uint32_t wait_cnt = 0; 233 234 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON(bus / 16), 235 BITS_WITH_WMASK(state, 0x1, bus % 16)); 236 237 while (pmu_bus_idle_st(bus) != state || 238 pmu_bus_idle_ack(bus) != state) { 239 if (++wait_cnt > BUS_IDLE_LOOP) 240 break; 241 udelay(1); 242 } 243 244 if (wait_cnt > BUS_IDLE_LOOP) 245 WARN("%s: can't wait state %d for bus %d (0x%x)\n", 246 __func__, state, bus, 247 mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(bus / 32))); 248 } 249 250 static void pmu_qch_pwr_ctlr(uint32_t msk, uint32_t state) 251 { 252 uint32_t wait_cnt = 0; 253 254 if (state != 0) 255 state = msk; 256 257 mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_SFTCON, 258 BITS_WITH_WMASK(state, msk, 0)); 259 260 while ((mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & msk) != state) { 261 if (++wait_cnt > QCH_PWR_LOOP) 262 break; 263 udelay(1); 264 } 265 266 if (wait_cnt > BUS_IDLE_LOOP) 267 WARN("%s: can't wait qch:0x%x to state:0x%x (0x%x)\n", 268 __func__, msk, state, 269 mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS)); 270 } 271 272 static inline uint32_t pmu_power_domain_chain_st(uint32_t pd) 273 { 274 return mmio_read_32(PMU_BASE + PMU2_PWR_CHAIN1_ST(pd / 32)) & BIT(pd % 32) ? 275 pmu_pd_on : 276 pmu_pd_off; 277 } 278 279 static inline uint32_t pmu_power_domain_mem_st(uint32_t pd) 280 { 281 return mmio_read_32(PMU_BASE + PMU2_PWR_MEM_ST(pd / 32)) & BIT(pd % 32) ? 282 pmu_pd_off : 283 pmu_pd_on; 284 } 285 286 static inline uint32_t pmu_power_domain_st(uint32_t pd) 287 { 288 int8_t pd_repair = pd_repair_map[pd]; 289 290 if (pd_repair >= 0) 291 return mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4)) & BIT(pd_repair) ? 292 pmu_pd_on : 293 pmu_pd_off; 294 else 295 return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(pd / 32)) & BIT(pd % 32) ? 296 pmu_pd_off : 297 pmu_pd_on; 298 } 299 300 static int pmu_power_domain_pd_to_mem_st(uint32_t pd, uint32_t *pd_mem_st) 301 { 302 uint32_t mem_st; 303 304 switch (pd) { 305 case PD_NPUTOP: 306 mem_st = PD_NPU_TOP_MEM_ST; 307 break; 308 case PD_NPU1: 309 mem_st = PD_NPU1_MEM_ST; 310 break; 311 case PD_NPU2: 312 mem_st = PD_NPU2_MEM_ST; 313 break; 314 case PD_VENC0: 315 mem_st = PD_VENC0_MEM_ST; 316 break; 317 case PD_VENC1: 318 mem_st = PD_VENC1_MEM_ST; 319 break; 320 case PD_RKVDEC0: 321 mem_st = PD_RKVDEC0_MEM_ST; 322 break; 323 case PD_RKVDEC1: 324 mem_st = PD_RKVDEC1_MEM_ST; 325 break; 326 case PD_RGA30: 327 mem_st = PD_RGA30_MEM_ST; 328 break; 329 case PD_AV1: 330 mem_st = PD_AV1_MEM_ST; 331 break; 332 case PD_VI: 333 mem_st = PD_VI_MEM_ST; 334 break; 335 case PD_FEC: 336 mem_st = PD_FEC_MEM_ST; 337 break; 338 case PD_ISP1: 339 mem_st = PD_ISP1_MEM_ST; 340 break; 341 case PD_RGA31: 342 mem_st = PD_RGA31_MEM_ST; 343 break; 344 case PD_VOP: 345 mem_st = PD_VOP_MEM_ST; 346 break; 347 case PD_VO0: 348 mem_st = PD_VO0_MEM_ST; 349 break; 350 case PD_VO1: 351 mem_st = PD_VO1_MEM_ST; 352 break; 353 case PD_AUDIO: 354 mem_st = PD_AUDIO_MEM_ST; 355 break; 356 case PD_PHP: 357 mem_st = PD_PHP_MEM_ST; 358 break; 359 case PD_GMAC: 360 mem_st = PD_GMAC_MEM_ST; 361 break; 362 case PD_PCIE: 363 mem_st = PD_PCIE_MEM_ST; 364 break; 365 case PD_NVM0: 366 mem_st = PD_NVM0_MEM_ST; 367 break; 368 case PD_SDIO: 369 mem_st = PD_SDIO_MEM_ST; 370 break; 371 case PD_USB: 372 mem_st = PD_USB_MEM_ST; 373 break; 374 case PD_SDMMC: 375 mem_st = PD_SDMMC_MEM_ST; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 *pd_mem_st = mem_st; 382 383 return 0; 384 } 385 386 static int pmu_power_domain_reset_mem(uint32_t pd, uint32_t pd_mem_st) 387 { 388 uint32_t loop = 0; 389 int ret = 0; 390 391 while (pmu_power_domain_chain_st(pd_mem_st) != pmu_pd_on) { 392 udelay(1); 393 loop++; 394 if (loop >= PD_CTR_LOOP) { 395 WARN("%s: %d chain up time out\n", __func__, pd); 396 ret = -EINVAL; 397 goto error; 398 } 399 } 400 401 udelay(60); 402 403 mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), 404 BITS_WITH_WMASK(pmu_pd_off, 0x1, pd % 16)); 405 dsb(); 406 407 loop = 0; 408 while (pmu_power_domain_mem_st(pd_mem_st) != pmu_pd_off) { 409 udelay(1); 410 loop++; 411 if (loop >= PD_CTR_LOOP) { 412 WARN("%s: %d mem down time out\n", __func__, pd); 413 ret = -EINVAL; 414 goto error; 415 } 416 } 417 418 mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), 419 BITS_WITH_WMASK(pmu_pd_on, 0x1, pd % 16)); 420 dsb(); 421 422 loop = 0; 423 while (pmu_power_domain_mem_st(pd_mem_st) != pmu_pd_on) { 424 udelay(1); 425 loop++; 426 if (loop >= PD_CTR_LOOP) { 427 WARN("%s: %d mem up time out\n", __func__, pd); 428 ret = -EINVAL; 429 goto error; 430 } 431 } 432 433 return 0; 434 435 error: 436 return ret; 437 } 438 439 static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) 440 { 441 uint32_t loop = 0; 442 uint32_t is_mem_on = pmu_pd_off; 443 uint32_t pd_mem_st; 444 int ret = 0; 445 446 if (pd_state == pmu_pd_on) { 447 ret = pmu_power_domain_pd_to_mem_st(pd, &pd_mem_st); 448 if (ret == 0) { 449 is_mem_on = pmu_power_domain_mem_st(pd_mem_st); 450 if (is_mem_on == pmu_pd_on) 451 WARN("%s: %d mem is up\n", __func__, pd); 452 } 453 } 454 455 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(pd / 16), 456 BITS_WITH_WMASK(pd_state, 0x1, pd % 16)); 457 dsb(); 458 459 if (is_mem_on == pmu_pd_on) { 460 ret = pmu_power_domain_reset_mem(pd, pd_mem_st); 461 if (ret != 0) 462 goto out; 463 WARN("%s: %d mem reset ok\n", __func__, pd); 464 } 465 466 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { 467 udelay(1); 468 loop++; 469 } 470 471 if (pmu_power_domain_st(pd) != pd_state) { 472 WARN("%s: %d, %d, (0x%x, 0x%x) error!\n", __func__, pd, pd_state, 473 mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)), 474 mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4))); 475 ret = -EINVAL; 476 } 477 478 out: 479 return ret; 480 } 481 482 static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) 483 { 484 uint32_t state; 485 486 if (pmu_power_domain_st(pd_id) == pd_state) 487 goto out; 488 489 if (pd_state == pmu_pd_on) 490 pmu_power_domain_ctr(pd_id, pd_state); 491 492 state = (pd_state == pmu_pd_off) ? bus_idle : bus_active; 493 494 switch (pd_id) { 495 case PD_GPU: 496 pmu_bus_idle_req(BUS_ID_GPU, state); 497 break; 498 case PD_NPUTOP: 499 pmu_bus_idle_req(BUS_ID_NPUTOP, state); 500 break; 501 case PD_NPU1: 502 pmu_bus_idle_req(BUS_ID_NPU1, state); 503 break; 504 case PD_NPU2: 505 pmu_bus_idle_req(BUS_ID_NPU2, state); 506 break; 507 case PD_VENC0: 508 pmu_bus_idle_req(BUS_ID_RKVENC0, state); 509 break; 510 case PD_VENC1: 511 pmu_bus_idle_req(BUS_ID_RKVENC1, state); 512 break; 513 case PD_RKVDEC0: 514 pmu_bus_idle_req(BUS_ID_RKVDEC0, state); 515 break; 516 case PD_RKVDEC1: 517 pmu_bus_idle_req(BUS_ID_RKVDEC1, state); 518 break; 519 case PD_VDPU: 520 pmu_bus_idle_req(BUS_ID_VDPU, state); 521 break; 522 case PD_AV1: 523 pmu_bus_idle_req(BUS_ID_AV1, state); 524 break; 525 case PD_VI: 526 pmu_bus_idle_req(BUS_ID_VI, state); 527 break; 528 case PD_ISP1: 529 pmu_bus_idle_req(BUS_ID_ISP, state); 530 break; 531 case PD_RGA31: 532 pmu_bus_idle_req(BUS_ID_RGA31, state); 533 break; 534 case PD_VOP: 535 pmu_bus_idle_req(BUS_ID_VOP_CHANNEL, state); 536 pmu_bus_idle_req(BUS_ID_VOP, state); 537 break; 538 case PD_VO0: 539 pmu_bus_idle_req(BUS_ID_VO0, state); 540 break; 541 case PD_VO1: 542 pmu_bus_idle_req(BUS_ID_VO1, state); 543 break; 544 case PD_AUDIO: 545 pmu_bus_idle_req(BUS_ID_AUDIO, state); 546 break; 547 case PD_PHP: 548 pmu_bus_idle_req(BUS_ID_PHP, state); 549 break; 550 case PD_NVM: 551 pmu_bus_idle_req(BUS_ID_NVM, state); 552 break; 553 case PD_SDIO: 554 pmu_bus_idle_req(BUS_ID_SDIO, state); 555 break; 556 case PD_USB: 557 pmu_bus_idle_req(BUS_ID_USB, state); 558 break; 559 case PD_SECURE: 560 pmu_bus_idle_req(BUS_ID_SECURE, state); 561 break; 562 default: 563 break; 564 } 565 566 if (pd_state == pmu_pd_off) 567 pmu_power_domain_ctr(pd_id, pd_state); 568 569 out: 570 return 0; 571 } 572 573 static void pmu_power_domains_suspend(void) 574 { 575 ddr_data.qch_pwr_st = 576 mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & PMU2_QCH_PWR_MSK; 577 ddr_data.pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)); 578 ddr_data.bus_idle_st0 = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(0)); 579 580 qos_save(); 581 582 if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) 583 pd_php_save(); 584 585 if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) 586 pd_crypto_save(); 587 588 pmu_qch_pwr_ctlr(0x20, 1); 589 pmu_qch_pwr_ctlr(0x40, 1); 590 pmu_qch_pwr_ctlr(0x1, 1); 591 pmu_qch_pwr_ctlr(0x2, 1); 592 pmu_qch_pwr_ctlr(0x4, 1); 593 pmu_qch_pwr_ctlr(0x8, 1); 594 pmu_qch_pwr_ctlr(0x10, 1); 595 596 pmu_bus_idle_req(BUS_ID_VO1USBTOP, bus_idle); 597 pmu_bus_idle_req(BUS_ID_SECURE_VO1USB_CHANNEL, bus_idle); 598 599 pmu_bus_idle_req(BUS_ID_USB, bus_idle); 600 601 pmu_set_power_domain(PD_GPU, pmu_pd_off); 602 603 pmu_set_power_domain(PD_NPU1, pmu_pd_off); 604 pmu_set_power_domain(PD_NPU2, pmu_pd_off); 605 pmu_set_power_domain(PD_NPUTOP, pmu_pd_off); 606 pmu_set_power_domain(PD_NPU, pmu_pd_off); 607 608 pmu_set_power_domain(PD_RKVDEC1, pmu_pd_off); 609 pmu_set_power_domain(PD_RKVDEC0, pmu_pd_off); 610 pmu_set_power_domain(PD_VENC1, pmu_pd_off); 611 pmu_set_power_domain(PD_VENC0, pmu_pd_off); 612 pmu_set_power_domain(PD_VCODEC, pmu_pd_off); 613 614 pmu_set_power_domain(PD_RGA30, pmu_pd_off); 615 pmu_set_power_domain(PD_AV1, pmu_pd_off); 616 pmu_set_power_domain(PD_VDPU, pmu_pd_off); 617 618 pmu_set_power_domain(PD_VO0, pmu_pd_off); 619 pmu_set_power_domain(PD_VO1, pmu_pd_off); 620 pmu_set_power_domain(PD_VOP, pmu_pd_off); 621 622 pmu_set_power_domain(PD_FEC, pmu_pd_off); 623 pmu_set_power_domain(PD_ISP1, pmu_pd_off); 624 pmu_set_power_domain(PD_VI, pmu_pd_off); 625 626 pmu_set_power_domain(PD_RGA31, pmu_pd_off); 627 628 pmu_set_power_domain(PD_AUDIO, pmu_pd_off); 629 630 pmu_set_power_domain(PD_GMAC, pmu_pd_off); 631 pmu_set_power_domain(PD_PCIE, pmu_pd_off); 632 pmu_set_power_domain(PD_PHP, pmu_pd_off); 633 634 pmu_set_power_domain(PD_SDIO, pmu_pd_off); 635 636 pmu_set_power_domain(PD_NVM0, pmu_pd_off); 637 pmu_set_power_domain(PD_NVM, pmu_pd_off); 638 639 pmu_set_power_domain(PD_SDMMC, pmu_pd_off); 640 pmu_set_power_domain(PD_CRYPTO, pmu_pd_off); 641 } 642 643 static void pmu_power_domains_resume(void) 644 { 645 int i; 646 647 pmu_set_power_domain(PD_CRYPTO, !!(ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO))); 648 pmu_set_power_domain(PD_SDMMC, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDMMC))); 649 650 pmu_set_power_domain(PD_NVM, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM))); 651 pmu_set_power_domain(PD_NVM0, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM0))); 652 653 pmu_set_power_domain(PD_SDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDIO))); 654 655 pmu_set_power_domain(PD_PHP, !!(ddr_data.pmu_pd_st0 & BIT(PD_PHP))); 656 pmu_set_power_domain(PD_PCIE, !!(ddr_data.pmu_pd_st0 & BIT(PD_PCIE))); 657 pmu_set_power_domain(PD_GMAC, !!(ddr_data.pmu_pd_st0 & BIT(PD_GMAC))); 658 659 pmu_set_power_domain(PD_AUDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_AUDIO))); 660 661 pmu_set_power_domain(PD_USB, !!(ddr_data.pmu_pd_st0 & BIT(PD_USB))); 662 663 pmu_set_power_domain(PD_RGA31, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA31))); 664 665 pmu_set_power_domain(PD_VI, !!(ddr_data.pmu_pd_st0 & BIT(PD_VI))); 666 pmu_set_power_domain(PD_ISP1, !!(ddr_data.pmu_pd_st0 & BIT(PD_ISP1))); 667 pmu_set_power_domain(PD_FEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_FEC))); 668 669 pmu_set_power_domain(PD_VOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_VOP))); 670 671 pmu_set_power_domain(PD_VO1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO1))); 672 673 pmu_set_power_domain(PD_VO0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO0))); 674 675 pmu_set_power_domain(PD_VDPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_VDPU))); 676 pmu_set_power_domain(PD_AV1, !!(ddr_data.pmu_pd_st0 & BIT(PD_AV1))); 677 pmu_set_power_domain(PD_RGA30, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA30))); 678 679 pmu_set_power_domain(PD_VCODEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_VCODEC))); 680 pmu_set_power_domain(PD_VENC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC0))); 681 pmu_set_power_domain(PD_VENC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC1))); 682 pmu_set_power_domain(PD_RKVDEC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC0))); 683 pmu_set_power_domain(PD_RKVDEC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC1))); 684 685 pmu_set_power_domain(PD_NPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU))); 686 pmu_set_power_domain(PD_NPUTOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPUTOP))); 687 pmu_set_power_domain(PD_NPU2, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU2))); 688 pmu_set_power_domain(PD_NPU1, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU1))); 689 690 pmu_set_power_domain(PD_GPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_GPU))); 691 692 for (i = 0; i < 32; i++) 693 pmu_bus_idle_req(i, !!(ddr_data.bus_idle_st0 & BIT(i))); 694 695 pmu_qch_pwr_ctlr(0x10, !!(ddr_data.qch_pwr_st & 0x10)); 696 pmu_qch_pwr_ctlr(0x8, !!(ddr_data.qch_pwr_st & 0x8)); 697 pmu_qch_pwr_ctlr(0x4, !!(ddr_data.qch_pwr_st & 0x4)); 698 pmu_qch_pwr_ctlr(0x2, !!(ddr_data.qch_pwr_st & 0x2)); 699 pmu_qch_pwr_ctlr(0x1, !!(ddr_data.qch_pwr_st & 0x1)); 700 pmu_qch_pwr_ctlr(0x40, !!(ddr_data.qch_pwr_st & 0x40)); 701 pmu_qch_pwr_ctlr(0x20, !!(ddr_data.qch_pwr_st & 0x20)); 702 703 if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) 704 pd_crypto_restore(); 705 706 if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) 707 pd_php_restore(); 708 709 qos_restore(); 710 } 711 712 static int cpus_power_domain_on(uint32_t cpu_id) 713 { 714 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 715 BITS_WITH_WMASK(0, 0x1, core_pm_en)); 716 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 717 BITS_WITH_WMASK(1, 0x1, core_pm_sft_wakeup_en)); 718 dsb(); 719 720 return 0; 721 } 722 723 static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) 724 { 725 uint32_t apm_value = BIT(core_pm_en); 726 727 if (pd_cfg == core_pwr_wfi_int) 728 apm_value |= BIT(core_pm_int_wakeup_en); 729 730 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 731 BITS_WITH_WMASK(apm_value, 0x3, 0)); 732 dsb(); 733 734 return 0; 735 } 736 737 static inline void cpus_pd_req_enter_wfi(void) 738 { 739 /* CORTEX_A55_CPUACTLR_EL1 */ 740 __asm__ volatile ("msr DBGPRCR_EL1, xzr\n" 741 "mrs x0, S3_0_C15_C2_7\n" 742 "orr x0, x0, #0x1\n" 743 "msr S3_0_C15_C2_7, x0\n" 744 "wfi_loop:\n" 745 "isb\n" 746 "wfi\n" 747 "b wfi_loop\n"); 748 } 749 750 static void nonboot_cpus_off(void) 751 { 752 uint32_t boot_cpu, cpu, tmp; 753 uint32_t exp_st; 754 uint32_t bcore0_rst_msk = 0, bcore1_rst_msk = 0; 755 int wait_cnt; 756 757 bcore0_rst_msk = CRU_BIGCPU02_RST_MSK | CRU_BIGCPU13_RST_MSK; 758 bcore1_rst_msk = CRU_BIGCPU02_RST_MSK | CRU_BIGCPU13_RST_MSK; 759 760 mmio_write_32(BIGCORE0CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore0_rst_msk, 0)); 761 mmio_write_32(BIGCORE1CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore1_rst_msk, 0)); 762 763 wait_cnt = NONBOOT_CPUS_OFF_LOOP; 764 exp_st = SYS_GRF_BIG_CPUS_WFE; 765 do { 766 wait_cnt--; 767 tmp = mmio_read_32(SYSGRF_BASE + SYS_GRF_SOC_STATUS(3)); 768 tmp &= SYS_GRF_BIG_CPUS_WFE; 769 } while (tmp != exp_st && wait_cnt); 770 771 boot_cpu = plat_my_core_pos(); 772 773 /* turn off noboot cpus */ 774 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { 775 if (cpu == boot_cpu) 776 continue; 777 cpus_power_domain_off(cpu, core_pwr_wfi); 778 } 779 780 mmio_write_32(SRAM_BASE + 0x08, (uintptr_t)&cpus_pd_req_enter_wfi); 781 mmio_write_32(SRAM_BASE + 0x04, 0xdeadbeaf); 782 783 dsb(); 784 isb(); 785 786 sev(); 787 788 wait_cnt = NONBOOT_CPUS_OFF_LOOP; 789 do { 790 wait_cnt--; 791 tmp = mmio_read_32(PMU_BASE + PMU2_CLUSTER_ST); 792 tmp &= CLUSTER_STS_NONBOOT_CPUS_DWN; 793 } while (tmp != CLUSTER_STS_NONBOOT_CPUS_DWN && wait_cnt); 794 795 if (tmp != CLUSTER_STS_NONBOOT_CPUS_DWN) 796 ERROR("nonboot cpus status(%x) error!\n", tmp); 797 } 798 799 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, 800 uint64_t entrypoint) 801 { 802 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 803 804 assert(cpu_id < PLATFORM_CORE_COUNT); 805 assert(cpuson_flags[cpu_id] == 0); 806 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; 807 cpuson_entry_point[cpu_id] = entrypoint; 808 dsb(); 809 810 flush_dcache_range((uintptr_t)cpuson_flags, sizeof(cpuson_flags)); 811 flush_dcache_range((uintptr_t)cpuson_entry_point, 812 sizeof(cpuson_entry_point)); 813 dsb(); 814 isb(); 815 816 cpus_power_domain_on(cpu_id); 817 818 return PSCI_E_SUCCESS; 819 } 820 821 int rockchip_soc_cores_pwr_dm_on_finish(void) 822 { 823 uint32_t cpu_id = plat_my_core_pos(); 824 825 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 826 BITS_WITH_WMASK(0, 0xf, 0)); 827 828 return PSCI_E_SUCCESS; 829 } 830 831 int rockchip_soc_cores_pwr_dm_off(void) 832 { 833 uint32_t cpu_id = plat_my_core_pos(); 834 835 cpus_power_domain_off(cpu_id, core_pwr_wfi); 836 837 return PSCI_E_SUCCESS; 838 } 839 840 int rockchip_soc_cores_pwr_dm_suspend(void) 841 { 842 uint32_t cpu_id = plat_my_core_pos(); 843 844 assert(cpu_id < PLATFORM_CORE_COUNT); 845 846 cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; 847 cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); 848 dsb(); 849 flush_dcache_range((uintptr_t)cpuson_flags, sizeof(cpuson_flags)); 850 flush_dcache_range((uintptr_t)cpuson_entry_point, 851 sizeof(cpuson_entry_point)); 852 dsb(); 853 isb(); 854 855 cpus_power_domain_off(cpu_id, core_pwr_wfi_int); 856 857 __asm__ volatile ("msr DBGPRCR_EL1, xzr\n" 858 "mrs x0, S3_0_C15_C2_7\n" 859 "orr x0, x0, #0x1\n" 860 "msr S3_0_C15_C2_7, x0\n"); 861 862 return PSCI_E_SUCCESS; 863 } 864 865 int rockchip_soc_cores_pwr_dm_resume(void) 866 { 867 uint32_t cpu_id = plat_my_core_pos(); 868 869 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 870 BITS_WITH_WMASK(0, 0x3, 0)); 871 872 dsb(); 873 874 return PSCI_E_SUCCESS; 875 } 876 877 static void ddr_sleep_config(void) 878 { 879 int i; 880 881 if (pmu_power_domain_st(PD_DDR01) == 0) { 882 ddr_data.ddrgrf_chn_con0[0] = 883 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0)); 884 ddr_data.ddrgrf_chn_con0[1] = 885 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0)); 886 ddr_data.ddrgrf_chn_con1[0] = 887 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1)); 888 ddr_data.ddrgrf_chn_con1[1] = 889 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1)); 890 ddr_data.ddrgrf_chn_con2[0] = 891 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2)); 892 ddr_data.ddrgrf_chn_con2[1] = 893 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2)); 894 895 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 0x20002000); 896 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 0x20002000); 897 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 0x08000000); 898 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 0x08000000); 899 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0), 0x00200020); 900 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0), 0x00200020); 901 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1), 0x00400040); 902 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1), 0x00400040); 903 } 904 905 if (pmu_power_domain_st(PD_DDR23) == 0) { 906 ddr_data.ddrgrf_chn_con0[2] = 907 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0)); 908 ddr_data.ddrgrf_chn_con0[3] = 909 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0)); 910 ddr_data.ddrgrf_chn_con1[2] = 911 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1)); 912 ddr_data.ddrgrf_chn_con1[3] = 913 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1)); 914 ddr_data.ddrgrf_chn_con2[2] = 915 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2)); 916 ddr_data.ddrgrf_chn_con2[3] = 917 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2)); 918 919 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 0x20002000); 920 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 0x20002000); 921 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 0x08000000); 922 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 0x08000000); 923 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0), 0x00200020); 924 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0), 0x00200020); 925 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1), 0x00400040); 926 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1), 0x00400040); 927 } 928 929 for (i = 0; i < DDR_CHN_CNT; i++) { 930 ddr_data.pmu1_ddr_pwr_sft_con[i] = 931 mmio_read_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i)); 932 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), 0x0fff0900); 933 } 934 } 935 936 static void ddr_sleep_config_restore(void) 937 { 938 int i; 939 940 for (i = 0; i < DDR_CHN_CNT; i++) { 941 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), 942 0x0fff0000 | ddr_data.pmu1_ddr_pwr_sft_con[i]); 943 } 944 945 if (pmu_power_domain_st(PD_DDR01) == 0) { 946 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1), 947 0x00400000 | ddr_data.ddrgrf_chn_con1[0]); 948 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1), 949 0x00400000 | ddr_data.ddrgrf_chn_con1[1]); 950 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0), 951 0x00200000 | ddr_data.ddrgrf_chn_con0[0]); 952 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0), 953 0x00200000 | ddr_data.ddrgrf_chn_con0[1]); 954 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 955 0x28000000 | ddr_data.ddrgrf_chn_con2[0]); 956 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 957 0x28000000 | ddr_data.ddrgrf_chn_con2[1]); 958 } 959 960 if (pmu_power_domain_st(PD_DDR23) == 0) { 961 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1), 962 0x00400000 | ddr_data.ddrgrf_chn_con1[2]); 963 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1), 964 0x00400000 | ddr_data.ddrgrf_chn_con1[3]); 965 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0), 966 0x00200000 | ddr_data.ddrgrf_chn_con0[2]); 967 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0), 968 0x00200000 | ddr_data.ddrgrf_chn_con0[3]); 969 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 970 0x28000000 | ddr_data.ddrgrf_chn_con2[2]); 971 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 972 0x28000000 | ddr_data.ddrgrf_chn_con2[3]); 973 } 974 } 975 976 static void pmu_sleep_config(void) 977 { 978 uint32_t pmu1_pwr_con, pmu1_wkup_int_con, pmu1_cru_pwr_con; 979 uint32_t pmu1_ddr_pwr_con, pmu1_pll_pd_con[2] = {0}; 980 uint32_t pmu2_dsu_pwr_con, pmu2_core_pwr_con, pmu2_clst_idle_con; 981 uint32_t pmu2_bus_idle_con[3] = {0}, pmu2_pwr_gate_con[3] = {0}; 982 uint32_t pmu2_vol_gate_con[3] = {0}, pmu2_qch_pwr_con = 0; 983 int i; 984 985 ddr_data.pmu1grf_soc_con7 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(7)); 986 ddr_data.pmu1grf_soc_con8 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(8)); 987 ddr_data.pmu1grf_soc_con9 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(9)); 988 ddr_data.pmu1sgrf_soc_con14 = mmio_read_32(PMU1SGRF_BASE + PMU1_SGRF_SOC_CON(14)); 989 ddr_data.pmu0sgrf_soc_con1 = mmio_read_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1)); 990 ddr_data.pmu0grf_soc_con1 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(1)); 991 992 ddr_data.pmu2_vol_gate_con[0] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(0)); 993 ddr_data.pmu2_vol_gate_con[1] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(1)); 994 ddr_data.pmu2_vol_gate_con[2] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(2)); 995 996 ddr_data.pmu2_submem_gate_sft_con0 = 997 mmio_read_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0)); 998 999 /* save pmic_sleep iomux gpio0_a4 */ 1000 ddr_data.gpio0a_iomux_l = mmio_read_32(PMU0IOC_BASE + 0); 1001 ddr_data.gpio0a_iomux_h = mmio_read_32(PMU0IOC_BASE + 4); 1002 ddr_data.pmu0grf_soc_con3 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3)); 1003 1004 /* PMU1 repair disable */ 1005 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(0), 0x00010000); 1006 1007 /* set pmic_sleep iomux */ 1008 mmio_write_32(PMU0IOC_BASE + 0, 1009 BITS_WITH_WMASK(1, 0xf, 8) | 1010 BITS_WITH_WMASK(1, 0xfu, 12)); 1011 1012 /* set tsadc_shut_m0 pin iomux to gpio */ 1013 mmio_write_32(PMU0IOC_BASE + 0, 1014 BITS_WITH_WMASK(0, 0xf, 4)); 1015 1016 /* set spi2_cs0/1 pin iomux to gpio */ 1017 mmio_write_32(PMU0IOC_BASE + 8, 1018 BITS_WITH_WMASK(0, 0xff, 0)); 1019 1020 /* sleep 1~2 src select */ 1021 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 1022 BITS_WITH_WMASK(0x8, 0xf, 0) | 1023 BITS_WITH_WMASK(0x8, 0xf, 4) | 1024 BITS_WITH_WMASK(0x0, 0x3, 8)); 1025 1026 pmu1_wkup_int_con = BIT(WAKEUP_GPIO0_INT_EN) | 1027 BIT(WAKEUP_CPU0_INT_EN); 1028 1029 pmu1_pwr_con = BIT(powermode_en); 1030 1031 pmu1_cru_pwr_con = 1032 BIT(alive_osc_mode_en) | 1033 BIT(power_off_en) | 1034 BIT(pd_clk_src_gate_en); 1035 1036 pmu1_ddr_pwr_con = 0; 1037 1038 pmu2_dsu_pwr_con = 1039 BIT(DSU_PWRDN_EN) | 1040 BIT(DSU_PWROFF_EN); 1041 1042 pmu2_core_pwr_con = BIT(CORE_PWRDN_EN); 1043 1044 pmu2_clst_idle_con = 1045 BIT(IDLE_REQ_BIGCORE0_EN) | 1046 BIT(IDLE_REQ_BIGCORE1_EN) | 1047 BIT(IDLE_REQ_DSU_EN) | 1048 BIT(IDLE_REQ_LITDSU_EN) | 1049 BIT(IDLE_REQ_ADB400_CORE_QCH_EN); 1050 1051 pmu1_pll_pd_con[0] = 1052 BIT(B0PLL_PD_EN) | 1053 BIT(B1PLL_PD_EN) | 1054 BIT(LPLL_PD_EN) | 1055 BIT(V0PLL_PD_EN) | 1056 BIT(AUPLL_PD_EN) | 1057 BIT(GPLL_PD_EN) | 1058 BIT(CPLL_PD_EN) | 1059 BIT(NPLL_PD_EN); 1060 1061 pmu1_pll_pd_con[1] = 1062 BIT(PPLL_PD_EN) | 1063 BIT(SPLL_PD_EN); 1064 1065 pmu2_bus_idle_con[0] = 0; 1066 1067 pmu2_bus_idle_con[1] = 1068 BIT(BUS_ID_SECURE - 16) | 1069 BIT(BUS_ID_SECURE_CENTER_CHANNEL - 16) | 1070 BIT(BUS_ID_CENTER_CHANNEL - 16); 1071 1072 pmu2_bus_idle_con[2] = 1073 BIT(BUS_ID_MSCH - 32) | 1074 BIT(BUS_ID_BUS - 32) | 1075 BIT(BUS_ID_TOP - 32); 1076 1077 pmu2_pwr_gate_con[0] = 0; 1078 pmu2_pwr_gate_con[1] = BIT(PD_SECURE - 16); 1079 pmu2_pwr_gate_con[2] = 0; 1080 1081 pmu2_qch_pwr_con = 0; 1082 1083 pmu2_vol_gate_con[0] = 0x7; 1084 pmu2_vol_gate_con[2] = 0; 1085 1086 mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(0), 0x00030000); 1087 mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(1), 0x00030000); 1088 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), 1089 WITH_16BITS_WMSK(pmu2_core_pwr_con)); 1090 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), 1091 WITH_16BITS_WMSK(pmu2_core_pwr_con)); 1092 mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 1093 WITH_16BITS_WMSK(pmu2_clst_idle_con)); 1094 mmio_write_32(PMU_BASE + PMU2_DSU_AUTO_PWR_CON, 0x00030000); 1095 mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, 1096 WITH_16BITS_WMSK(pmu2_dsu_pwr_con)); 1097 1098 mmio_write_32(PMU_BASE + PMU1_OSC_STABLE_CNT_THRESH, 24000); 1099 mmio_write_32(PMU_BASE + PMU1_STABLE_CNT_THRESH, 24000); 1100 mmio_write_32(PMU_BASE + PMU1_WAKEUP_RST_CLR_CNT_THRESH, 24000); 1101 mmio_write_32(PMU_BASE + PMU1_PLL_LOCK_CNT_THRESH, 24000); 1102 mmio_write_32(PMU_BASE + PMU1_PWM_SWITCH_CNT_THRESH, 24000); 1103 mmio_write_32(PMU_BASE + PMU2_CORE0_STABLE_CNT_THRESH, 24000); 1104 mmio_write_32(PMU_BASE + PMU2_CORE0_PWRUP_CNT_THRESH, 24000); 1105 mmio_write_32(PMU_BASE + PMU2_CORE0_PWRDN_CNT_THRESH, 24000); 1106 mmio_write_32(PMU_BASE + PMU2_CORE1_STABLE_CNT_THRESH, 24000); 1107 mmio_write_32(PMU_BASE + PMU2_CORE1_PWRUP_CNT_THRESH, 24000); 1108 mmio_write_32(PMU_BASE + PMU2_CORE1_PWRDN_CNT_THRESH, 24000); 1109 mmio_write_32(PMU_BASE + PMU2_DSU_STABLE_CNT_THRESH, 24000); 1110 mmio_write_32(PMU_BASE + PMU2_DSU_PWRUP_CNT_THRESH, 24000); 1111 mmio_write_32(PMU_BASE + PMU2_DSU_PWRDN_CNT_THRESH, 24000); 1112 1113 /* Config pmu power mode and pmu wakeup source */ 1114 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 1115 BITS_WITH_WMASK(1, 0x1, 0)); 1116 1117 /* pmu1_pwr_con */ 1118 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 1119 WITH_16BITS_WMSK(pmu1_pwr_con)); 1120 1121 /* cru_pwr_con */ 1122 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON, 1123 WITH_16BITS_WMSK(pmu1_cru_pwr_con)); 1124 1125 /* wakeup source */ 1126 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, pmu1_wkup_int_con); 1127 1128 /* ddr pwr con */ 1129 for (i = 0; i < DDR_CHN_CNT; i++) { 1130 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(i), 1131 WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); 1132 pmu2_bus_idle_con[1] |= 1133 BIT(BUS_ID_MSCH0 - 16 + i); 1134 } 1135 1136 /* pll_pd */ 1137 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), 1138 WITH_16BITS_WMSK(pmu1_pll_pd_con[0])); 1139 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(1), 1140 WITH_16BITS_WMSK(pmu1_pll_pd_con[1])); 1141 1142 /* bypass cpu1~7*/ 1143 mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0x00ff00fe); 1144 1145 /* bus idle */ 1146 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), 1147 WITH_16BITS_WMSK(pmu2_bus_idle_con[0])); 1148 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), 1149 WITH_16BITS_WMSK(pmu2_bus_idle_con[1])); 1150 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), 1151 WITH_16BITS_WMSK(pmu2_bus_idle_con[2])); 1152 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), 1153 0xf000f000); 1154 /* power gate */ 1155 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), 1156 WITH_16BITS_WMSK(pmu2_pwr_gate_con[0])); 1157 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), 1158 WITH_16BITS_WMSK(pmu2_pwr_gate_con[1])); 1159 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(2), 1160 WITH_16BITS_WMSK(pmu2_pwr_gate_con[2])); 1161 /* vol gate */ 1162 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), 1163 BITS_WITH_WMASK(pmu2_vol_gate_con[0], 0x7, 0)); 1164 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), 0); 1165 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), 1166 BITS_WITH_WMASK(pmu2_vol_gate_con[2], 0x3, 0)); 1167 /* qch */ 1168 mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_CON, 1169 BITS_WITH_WMASK(pmu2_qch_pwr_con, 0x7f, 0)); 1170 1171 mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), 1172 0x000f000f); 1173 } 1174 1175 static void pmu_sleep_restore(void) 1176 { 1177 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(7), 1178 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con7)); 1179 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(8), 1180 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con8)); 1181 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(9), 1182 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con9)); 1183 mmio_write_32(PMU1SGRF_BASE + PMU1_SGRF_SOC_CON(14), 1184 WITH_16BITS_WMSK(ddr_data.pmu1sgrf_soc_con14)); 1185 1186 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1), 1187 WITH_16BITS_WMSK(ddr_data.pmu0sgrf_soc_con1)); 1188 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(1), 1189 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con1)); 1190 1191 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), 0xffff0000); 1192 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), 0xffff0000); 1193 mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 0xffff0000); 1194 mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, 0xffff0000); 1195 mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0xffff0000); 1196 1197 /* Must clear PMU1_WAKEUP_INT_CON because the wakeup source 1198 * in PMU1_WAKEUP_INT_CON will wakeup cpus in cpu_auto_pd state. 1199 */ 1200 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, 0); 1201 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 0xffff0000); 1202 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 0x00010000); 1203 mmio_write_32(PMU_BASE + PMU0_WAKEUP_INT_CON, 0x00010000); 1204 mmio_write_32(PMU_BASE + PMU0_PWR_CON, 0xffff0000); 1205 1206 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), 1207 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[0])); 1208 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), 1209 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[1])); 1210 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), 1211 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[2])); 1212 1213 mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), 1214 WITH_16BITS_WMSK(ddr_data.pmu2_submem_gate_sft_con0)); 1215 1216 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 1217 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con3)); 1218 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(2), 1219 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con2)); 1220 1221 mmio_write_32(PMU0IOC_BASE + 0x4, 1222 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h)); 1223 mmio_write_32(PMU0IOC_BASE + 0, 1224 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l)); 1225 } 1226 1227 static void soc_sleep_config(void) 1228 { 1229 ddr_data.gpio0b_iomux_l = mmio_read_32(PMU0IOC_BASE + 0x8); 1230 1231 pmu_sleep_config(); 1232 ddr_sleep_config(); 1233 } 1234 1235 static void soc_sleep_restore(void) 1236 { 1237 ddr_sleep_config_restore(); 1238 pmu_sleep_restore(); 1239 1240 mmio_write_32(PMU0IOC_BASE + 0x8, WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l)); 1241 } 1242 1243 static void pm_pll_suspend(void) 1244 { 1245 ddr_data.cru_mode_con = mmio_read_32(CRU_BASE + 0x280); 1246 ddr_data.busscru_mode_con = mmio_read_32(BUSSCRU_BASE + 0x280); 1247 ddr_data.pmu2_bisr_con0 = mmio_read_32(PMU_BASE + PMU2_BISR_CON(0)); 1248 ddr_data.cpll_con0 = mmio_read_32(CRU_BASE + CRU_PLLS_CON(2, 0)); 1249 ddr_data.pmu1cru_clksel_con1 = mmio_read_32(PMU1CRU_BASE + CRU_CLKSEL_CON(1)); 1250 1251 /* disable bisr_init */ 1252 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), BITS_WITH_WMASK(0, 0x1, 0)); 1253 /* cpll bypass */ 1254 mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), BITS_WITH_WMASK(1u, 1u, 15)); 1255 } 1256 1257 static void pm_pll_restore(void) 1258 { 1259 pm_pll_wait_lock(CRU_BASE + CRU_PLLS_CON(2, 0)); 1260 1261 mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); 1262 mmio_write_32(BUSSCRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.busscru_mode_con)); 1263 mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), WITH_16BITS_WMSK(ddr_data.cpll_con0)); 1264 dsb(); 1265 isb(); 1266 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), WITH_16BITS_WMSK(ddr_data.pmu2_bisr_con0)); 1267 } 1268 1269 int rockchip_soc_sys_pwr_dm_suspend(void) 1270 { 1271 clk_gate_con_save(); 1272 clk_gate_con_disable(); 1273 1274 psram_sleep_cfg->pm_flag &= ~PM_WARM_BOOT_BIT; 1275 1276 pmu_power_domains_suspend(); 1277 soc_sleep_config(); 1278 dsu_core_save(); 1279 pm_pll_suspend(); 1280 1281 return 0; 1282 } 1283 1284 int rockchip_soc_sys_pwr_dm_resume(void) 1285 { 1286 pm_pll_restore(); 1287 dsu_core_restore(); 1288 soc_sleep_restore(); 1289 pmu_power_domains_resume(); 1290 plat_rockchip_gic_cpuif_enable(); 1291 1292 psram_sleep_cfg->pm_flag |= PM_WARM_BOOT_BIT; 1293 1294 clk_gate_con_restore(); 1295 1296 return 0; 1297 } 1298 1299 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(const 1300 psci_power_state_t *target_state) 1301 { 1302 psci_power_down_wfi(); 1303 } 1304 1305 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void) 1306 { 1307 cpus_pd_req_enter_wfi(); 1308 psci_power_down_wfi(); 1309 } 1310 1311 void __dead2 rockchip_soc_soft_reset(void) 1312 { 1313 /* pll slow mode */ 1314 mmio_write_32(CRU_BASE + 0x280, 0x03ff0000); 1315 mmio_write_32(BIGCORE0CRU_BASE + 0x280, 0x00030000); 1316 mmio_write_32(BIGCORE0CRU_BASE + 0x300, 0x60000000); 1317 mmio_write_32(BIGCORE0CRU_BASE + 0x304, 0x00600000); 1318 mmio_write_32(BIGCORE1CRU_BASE + 0x280, 0x00030000); 1319 mmio_write_32(BIGCORE1CRU_BASE + 0x300, 0x60000000); 1320 mmio_write_32(BIGCORE1CRU_BASE + 0x304, 0x00600000); 1321 mmio_write_32(DSUCRU_BASE + 0x280, 0x00030000); 1322 mmio_write_32(DSUCRU_BASE + 0x318, 0x30600000); 1323 mmio_write_32(DSUCRU_BASE + 0x31c, 0x30600000); 1324 mmio_write_32(DSUCRU_BASE + 0x304, 0x00010000); 1325 mmio_write_32(BUSSCRU_BASE + 0x280, 0x0003000); 1326 dsb(); 1327 isb(); 1328 1329 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 1330 1331 /* 1332 * Maybe the HW needs some times to reset the system, 1333 * so we do not hope the core to execute valid codes. 1334 */ 1335 psci_power_down_wfi(); 1336 } 1337 1338 void __dead2 rockchip_soc_system_off(void) 1339 { 1340 /* set pmic_sleep pin(gpio0_a2) to gpio mode */ 1341 mmio_write_32(PMU0IOC_BASE + 0, BITS_WITH_WMASK(0, 0xf, 8)); 1342 1343 /* config output */ 1344 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DDR_L, 1345 BITS_WITH_WMASK(1, 0x1, 2)); 1346 1347 /* config output high level */ 1348 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DR_L, 1349 BITS_WITH_WMASK(1, 0x1, 2)); 1350 dsb(); 1351 1352 /* 1353 * Maybe the HW needs some times to reset the system, 1354 * so we do not hope the core to execute valid codes. 1355 */ 1356 psci_power_down_wfi(); 1357 } 1358 1359 static void rockchip_pmu_pd_init(void) 1360 { 1361 mmio_write_32(PMU_BASE + PMU2_BISR_CON(1), 0xffffffff); 1362 mmio_write_32(PMU_BASE + PMU2_BISR_CON(2), 0xffffffff); 1363 mmio_write_32(PMU_BASE + PMU2_BISR_CON(3), 0xffffffff); 1364 1365 pmu_set_power_domain(PD_PHP, pmu_pd_on); 1366 pmu_set_power_domain(PD_PCIE, pmu_pd_on); 1367 pmu_set_power_domain(PD_GMAC, pmu_pd_on); 1368 pmu_set_power_domain(PD_SECURE, pmu_pd_on); 1369 pmu_set_power_domain(PD_VOP, pmu_pd_on); 1370 pmu_set_power_domain(PD_VO0, pmu_pd_on); 1371 pmu_set_power_domain(PD_VO1, pmu_pd_on); 1372 } 1373 1374 #define PLL_LOCKED_TIMEOUT 600000U 1375 1376 void pm_pll_wait_lock(uint32_t pll_base) 1377 { 1378 int delay = PLL_LOCKED_TIMEOUT; 1379 1380 if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0) 1381 return; 1382 1383 while (delay-- >= 0) { 1384 if (mmio_read_32(pll_base + CRU_PLL_CON(6)) & 1385 CRU_PLLCON6_LOCK_STATUS) 1386 break; 1387 udelay(1); 1388 } 1389 1390 if (delay <= 0) 1391 ERROR("Can't wait pll(0x%x) lock\n", pll_base); 1392 } 1393 1394 void rockchip_plat_mmu_el3(void) 1395 { 1396 /* Nothing todo */ 1397 } 1398 1399 void plat_rockchip_pmu_init(void) 1400 { 1401 int cpu; 1402 1403 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) 1404 cpuson_flags[cpu] = 0; 1405 1406 psram_sleep_cfg->sp = PSRAM_SP_TOP; 1407 psram_sleep_cfg->ddr_func = (uint64_t)ddr_resume; 1408 psram_sleep_cfg->ddr_data = 0; 1409 psram_sleep_cfg->ddr_flag = 0; 1410 psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; 1411 psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT; 1412 1413 nonboot_cpus_off(); 1414 1415 /* 1416 * When perform idle operation, corresponding clock can be 1417 * opened or gated automatically. 1418 */ 1419 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(0), 0xffffffff); 1420 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(1), 0xffffffff); 1421 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(2), 0x00070007); 1422 1423 rockchip_pmu_pd_init(); 1424 1425 /* grf_con_pmic_sleep_sel 1426 * pmic sleep function selection 1427 * 1'b0: From reset pulse generator, can reset external PMIC 1428 * 1'b1: From pmu block, only support sleep function for external PMIC 1429 */ 1430 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 0x03ff0000); 1431 1432 /* pmusram remap to 0xffff0000 */ 1433 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001); 1434 1435 pm_reg_rgns_init(); 1436 } 1437