1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp25-clks.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/stm32mp25-resets.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 }; 25 }; 26 27 clocks { 28 clk_hse: clk-hse { 29 #clock-cells = <0>; 30 compatible = "fixed-clock"; 31 clock-frequency = <48000000>; 32 }; 33 34 clk_hsi: clk-hsi { 35 #clock-cells = <0>; 36 compatible = "fixed-clock"; 37 clock-frequency = <64000000>; 38 }; 39 40 clk_lse: clk-lse { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <32768>; 44 }; 45 46 clk_lsi: clk-lsi { 47 #clock-cells = <0>; 48 compatible = "fixed-clock"; 49 clock-frequency = <32000>; 50 }; 51 52 clk_msi: clk-msi { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <16000000>; 56 }; 57 }; 58 59 intc: interrupt-controller@4ac00000 { 60 compatible = "arm,cortex-a7-gic"; 61 #interrupt-cells = <3>; 62 #address-cells = <1>; 63 interrupt-controller; 64 reg = <0x0 0x4ac10000 0x0 0x1000>, 65 <0x0 0x4ac20000 0x0 0x2000>, 66 <0x0 0x4ac40000 0x0 0x2000>, 67 <0x0 0x4ac60000 0x0 0x2000>; 68 }; 69 70 timer { 71 compatible = "arm,armv8-timer"; 72 interrupt-parent = <&intc>; 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 77 always-on; 78 }; 79 80 soc@0 { 81 compatible = "simple-bus"; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 interrupt-parent = <&intc>; 85 ranges = <0x0 0x0 0x0 0x80000000>; 86 87 rifsc: rifsc@42080000 { 88 compatible = "st,stm32mp25-rifsc"; 89 reg = <0x42080000 0x1000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 93 usart2: serial@400e0000 { 94 compatible = "st,stm32h7-uart"; 95 reg = <0x400e0000 0x400>; 96 clocks = <&rcc CK_KER_USART2>; 97 resets = <&rcc USART2_R>; 98 status = "disabled"; 99 }; 100 }; 101 102 bsec: efuse@44000000 { 103 compatible = "st,stm32mp25-bsec"; 104 reg = <0x44000000 0x400>; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 108 uid_otp: uid-otp@14 { 109 reg = <0x14 0xc>; 110 }; 111 part_number_otp: part-number-otp@24 { 112 reg = <0x24 0x4>; 113 }; 114 nand_otp: otp16@40 { 115 reg = <0x40 0x4>; 116 }; 117 lifecycle2_otp: otp18@48 { 118 reg = <0x48 0x4>; 119 }; 120 nand2_otp: otp20@50 { 121 reg = <0x50 0x4>; 122 }; 123 package_otp: package-otp@1e8 { 124 reg = <0x1e8 0x1>; 125 }; 126 hconf1_otp: otp124@1f0 { 127 reg = <0x1f0 0x4>; 128 }; 129 pkh_otp: otp144@240 { 130 reg = <0x240 0x20>; 131 }; 132 oem_fip_enc_key: otp260@410 { 133 reg = <0x410 0x20>; 134 }; 135 }; 136 137 rcc: rcc@44200000 { 138 compatible = "st,stm32mp25-rcc"; 139 reg = <0x44200000 0x10000>; 140 #clock-cells = <1>; 141 #reset-cells = <1>; 142 }; 143 144 pwr: pwr@44210000 { 145 compatible = "st,stm32mp25-pwr"; 146 reg = <0x44210000 0x400>; 147 148 vddio1: vddio1 { 149 regulator-name = "vddio1"; 150 }; 151 152 vddio2: vddio2 { 153 regulator-name = "vddio2"; 154 }; 155 156 vddio3: vddio3 { 157 regulator-name = "vddio3"; 158 }; 159 160 vddio4: vddio4 { 161 regulator-name = "vddio4"; 162 }; 163 164 vddio: vddio { 165 regulator-name = "vddio"; 166 }; 167 }; 168 169 syscfg: syscon@44230000 { 170 compatible = "st,stm32mp25-syscfg", "syscon"; 171 reg = <0x44230000 0x10000>; 172 }; 173 174 pinctrl: pinctrl@44240000 { 175 #address-cells = <1>; 176 #size-cells = <1>; 177 compatible = "st,stm32mp257-pinctrl"; 178 ranges = <0 0x44240000 0xa0400>; 179 180 gpioa: gpio@44240000 { 181 gpio-controller; 182 #gpio-cells = <2>; 183 interrupt-controller; 184 #interrupt-cells = <2>; 185 reg = <0x0 0x400>; 186 clocks = <&rcc CK_BUS_GPIOA>; 187 st,bank-name = "GPIOA"; 188 status = "disabled"; 189 }; 190 191 gpiob: gpio@44250000 { 192 gpio-controller; 193 #gpio-cells = <2>; 194 interrupt-controller; 195 #interrupt-cells = <2>; 196 reg = <0x10000 0x400>; 197 clocks = <&rcc CK_BUS_GPIOB>; 198 st,bank-name = "GPIOB"; 199 status = "disabled"; 200 }; 201 202 gpioc: gpio@44260000 { 203 gpio-controller; 204 #gpio-cells = <2>; 205 interrupt-controller; 206 #interrupt-cells = <2>; 207 reg = <0x20000 0x400>; 208 clocks = <&rcc CK_BUS_GPIOC>; 209 st,bank-name = "GPIOC"; 210 status = "disabled"; 211 }; 212 213 gpiod: gpio@44270000 { 214 gpio-controller; 215 #gpio-cells = <2>; 216 interrupt-controller; 217 #interrupt-cells = <2>; 218 reg = <0x30000 0x400>; 219 clocks = <&rcc CK_BUS_GPIOD>; 220 st,bank-name = "GPIOD"; 221 status = "disabled"; 222 }; 223 224 gpioe: gpio@44280000 { 225 gpio-controller; 226 #gpio-cells = <2>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 reg = <0x40000 0x400>; 230 clocks = <&rcc CK_BUS_GPIOE>; 231 st,bank-name = "GPIOE"; 232 status = "disabled"; 233 }; 234 235 gpiof: gpio@44290000 { 236 gpio-controller; 237 #gpio-cells = <2>; 238 interrupt-controller; 239 #interrupt-cells = <2>; 240 reg = <0x50000 0x400>; 241 clocks = <&rcc CK_BUS_GPIOF>; 242 st,bank-name = "GPIOF"; 243 status = "disabled"; 244 }; 245 246 gpiog: gpio@442a0000 { 247 gpio-controller; 248 #gpio-cells = <2>; 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 reg = <0x60000 0x400>; 252 clocks = <&rcc CK_BUS_GPIOG>; 253 st,bank-name = "GPIOG"; 254 status = "disabled"; 255 }; 256 257 gpioh: gpio@442b0000 { 258 gpio-controller; 259 #gpio-cells = <2>; 260 interrupt-controller; 261 #interrupt-cells = <2>; 262 reg = <0x70000 0x400>; 263 clocks = <&rcc CK_BUS_GPIOH>; 264 st,bank-name = "GPIOH"; 265 status = "disabled"; 266 }; 267 268 gpioi: gpio@442c0000 { 269 gpio-controller; 270 #gpio-cells = <2>; 271 interrupt-controller; 272 #interrupt-cells = <2>; 273 reg = <0x80000 0x400>; 274 clocks = <&rcc CK_BUS_GPIOI>; 275 st,bank-name = "GPIOI"; 276 status = "disabled"; 277 }; 278 279 gpioj: gpio@442d0000 { 280 gpio-controller; 281 #gpio-cells = <2>; 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 reg = <0x90000 0x400>; 285 clocks = <&rcc CK_BUS_GPIOJ>; 286 st,bank-name = "GPIOJ"; 287 status = "disabled"; 288 }; 289 290 gpiok: gpio@442e0000 { 291 gpio-controller; 292 #gpio-cells = <2>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 reg = <0xa0000 0x400>; 296 clocks = <&rcc CK_BUS_GPIOK>; 297 st,bank-name = "GPIOK"; 298 status = "disabled"; 299 }; 300 }; 301 302 pinctrl_z: pinctrl@46200000 { 303 #address-cells = <1>; 304 #size-cells = <1>; 305 compatible = "st,stm32mp257-z-pinctrl"; 306 ranges = <0 0x46200000 0x400>; 307 308 gpioz: gpio@46200000 { 309 gpio-controller; 310 #gpio-cells = <2>; 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 reg = <0 0x400>; 314 clocks = <&rcc CK_BUS_GPIOZ>; 315 st,bank-name = "GPIOZ"; 316 st,bank-ioport = <11>; 317 status = "disabled"; 318 }; 319 320 }; 321 }; 322}; 323