1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <cdefs.h> 8 #include <stdint.h> 9 10 #include <common/debug.h> 11 #include <drivers/clk.h> 12 #include <lib/fconf/fconf.h> 13 #include <lib/fconf/fconf_dyn_cfg_getter.h> 14 #include <lib/mmio.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 #include <plat/common/platform.h> 17 18 #include <platform_def.h> 19 #include <stm32mp_common.h> 20 #include <stm32mp_dt.h> 21 22 #define BOOT_CTX_ADDR 0x0e000020UL 23 24 static void print_reset_reason(void) 25 { 26 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR); 27 28 if (rstsr == 0U) { 29 WARN("Reset reason unknown\n"); 30 return; 31 } 32 33 INFO("Reset reason (0x%x):\n", rstsr); 34 35 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) { 36 if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) { 37 INFO("System exits from Standby for CA35\n"); 38 return; 39 } 40 41 if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) { 42 INFO("D1 domain exits from DStandby\n"); 43 return; 44 } 45 } 46 47 if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) { 48 INFO(" Power-on Reset (rst_por)\n"); 49 return; 50 } 51 52 if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) { 53 INFO(" Brownout Reset (rst_bor)\n"); 54 return; 55 } 56 57 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) { 58 INFO(" System reset (SYSRST) by M33\n"); 59 return; 60 } 61 62 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) { 63 INFO(" System reset (SYSRST) by A35\n"); 64 return; 65 } 66 67 if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) { 68 INFO(" Clock failure on HSE\n"); 69 return; 70 } 71 72 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) { 73 INFO(" IWDG1 system reset (rst_iwdg1)\n"); 74 return; 75 } 76 77 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) { 78 INFO(" IWDG2 system reset (rst_iwdg2)\n"); 79 return; 80 } 81 82 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) { 83 INFO(" IWDG3 system reset (rst_iwdg3)\n"); 84 return; 85 } 86 87 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) { 88 INFO(" IWDG4 system reset (rst_iwdg4)\n"); 89 return; 90 } 91 92 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) { 93 INFO(" IWDG5 system reset (rst_iwdg5)\n"); 94 return; 95 } 96 97 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) { 98 INFO(" A35 processor core 1 reset\n"); 99 return; 100 } 101 102 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) { 103 INFO(" Pad Reset from NRST\n"); 104 return; 105 } 106 107 if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) { 108 INFO(" Reset due to a failure of VDD_CORE\n"); 109 return; 110 } 111 112 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) { 113 INFO(" A35 processor reset\n"); 114 return; 115 } 116 117 ERROR(" Unidentified reset reason\n"); 118 } 119 120 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 121 u_register_t arg1 __unused, 122 u_register_t arg2 __unused, 123 u_register_t arg3 __unused) 124 { 125 stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR); 126 } 127 128 void bl2_platform_setup(void) 129 { 130 } 131 132 static void reset_backup_domain(void) 133 { 134 uintptr_t pwr_base = stm32mp_pwr_base(); 135 uintptr_t rcc_base = stm32mp_rcc_base(); 136 137 /* 138 * Disable the backup domain write protection. 139 * The protection is enable at each reset by hardware 140 * and must be disabled by software. 141 */ 142 mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P); 143 144 while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) { 145 ; 146 } 147 148 /* Reset backup domain on cold boot cases */ 149 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) { 150 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 151 152 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { 153 ; 154 } 155 156 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 157 } 158 } 159 160 void bl2_el3_plat_arch_setup(void) 161 { 162 const char *board_model; 163 boot_api_context_t *boot_context = 164 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 165 166 if (stm32_otp_probe() != 0U) { 167 EARLY_ERROR("OTP probe failed\n"); 168 panic(); 169 } 170 171 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 172 BL_CODE_END - BL_CODE_BASE, 173 MT_CODE | MT_SECURE); 174 175 configure_mmu(); 176 177 /* Prevent corruption of preloaded Device Tree */ 178 mmap_add_dynamic_region(DTB_BASE, DTB_BASE, 179 DTB_LIMIT - DTB_BASE, 180 MT_RO_DATA | MT_SECURE); 181 182 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 183 panic(); 184 } 185 186 reset_backup_domain(); 187 188 if (stm32mp2_clk_init() < 0) { 189 panic(); 190 } 191 192 stm32_save_boot_info(boot_context); 193 194 if (stm32mp_uart_console_setup() != 0) { 195 goto skip_console_init; 196 } 197 198 stm32mp_print_cpuinfo(); 199 200 board_model = dt_get_board_model(); 201 if (board_model != NULL) { 202 NOTICE("Model: %s\n", board_model); 203 } 204 205 stm32mp_print_boardinfo(); 206 207 print_reset_reason(); 208 209 skip_console_init: 210 fconf_populate("TB_FW", STM32MP_DTB_BASE); 211 212 stm32mp_io_setup(); 213 } 214