1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #endif 14 #include <drivers/st/stm32mp25_rcc.h> 15 #ifndef __ASSEMBLER__ 16 #include <drivers/st/stm32mp2_clk.h> 17 #endif 18 #include <drivers/st/stm32mp2_pwr.h> 19 #include <dt-bindings/clock/stm32mp25-clks.h> 20 #include <dt-bindings/clock/stm32mp25-clksrc.h> 21 #include <dt-bindings/gpio/stm32-gpio.h> 22 #include <dt-bindings/reset/stm32mp25-resets.h> 23 24 #ifndef __ASSEMBLER__ 25 #include <boot_api.h> 26 #include <stm32mp2_private.h> 27 #include <stm32mp_common.h> 28 #include <stm32mp_dt.h> 29 #include <stm32mp_shared_resources.h> 30 #endif 31 32 /******************************************************************************* 33 * STM32MP2 memory map related constants 34 ******************************************************************************/ 35 #define STM32MP_SYSRAM_BASE U(0x0E000000) 36 #define STM32MP_SYSRAM_SIZE U(0x00040000) 37 38 /* DDR configuration */ 39 #define STM32MP_DDR_BASE U(0x80000000) 40 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 41 42 /* DDR power initializations */ 43 #ifndef __ASSEMBLER__ 44 enum ddr_type { 45 STM32MP_DDR3, 46 STM32MP_DDR4, 47 STM32MP_LPDDR4 48 }; 49 #endif 50 51 /* Section used inside TF binaries */ 52 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 53 /* 512 Bytes reserved for header */ 54 #define STM32MP_HEADER_SIZE U(0x00000200) 55 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \ 56 STM32MP_PARAM_LOAD_SIZE) 57 58 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 59 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 60 61 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 62 STM32MP_PARAM_LOAD_SIZE + \ 63 STM32MP_HEADER_SIZE) 64 65 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 66 (STM32MP_PARAM_LOAD_SIZE + \ 67 STM32MP_HEADER_SIZE)) 68 69 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */ 70 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */ 71 72 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \ 73 STM32MP_SYSRAM_SIZE - \ 74 STM32MP_BL2_SIZE) 75 76 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 77 78 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 79 STM32MP_BL2_RO_SIZE) 80 81 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 82 STM32MP_SYSRAM_SIZE - \ 83 STM32MP_BL2_RW_BASE) 84 85 /* BL2 and BL32/sp_min require 4 tables */ 86 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 87 88 /* 89 * MAX_MMAP_REGIONS is usually: 90 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 91 */ 92 #define MAX_MMAP_REGIONS 6 93 94 /* DTB initialization value */ 95 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 96 97 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 98 STM32MP_BL2_DTB_SIZE) 99 100 #if defined(IMAGE_BL2) 101 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 102 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 103 #endif 104 105 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 106 #define STM32MP_BL33_MAX_SIZE U(0x400000) 107 108 /******************************************************************************* 109 * STM32MP2 device/io map related constants (used for MMU) 110 ******************************************************************************/ 111 #define STM32MP_DEVICE_BASE U(0x40000000) 112 #define STM32MP_DEVICE_SIZE U(0x40000000) 113 114 /******************************************************************************* 115 * STM32MP2 RCC 116 ******************************************************************************/ 117 #define RCC_BASE U(0x44200000) 118 119 /******************************************************************************* 120 * STM32MP2 PWR 121 ******************************************************************************/ 122 #define PWR_BASE U(0x44210000) 123 124 /******************************************************************************* 125 * STM32MP2 GPIO 126 ******************************************************************************/ 127 #define GPIOA_BASE U(0x44240000) 128 #define GPIOB_BASE U(0x44250000) 129 #define GPIOC_BASE U(0x44260000) 130 #define GPIOD_BASE U(0x44270000) 131 #define GPIOE_BASE U(0x44280000) 132 #define GPIOF_BASE U(0x44290000) 133 #define GPIOG_BASE U(0x442A0000) 134 #define GPIOH_BASE U(0x442B0000) 135 #define GPIOI_BASE U(0x442C0000) 136 #define GPIOJ_BASE U(0x442D0000) 137 #define GPIOK_BASE U(0x442E0000) 138 #define GPIOZ_BASE U(0x46200000) 139 #define GPIO_BANK_OFFSET U(0x10000) 140 141 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 142 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 143 144 /******************************************************************************* 145 * STM32MP2 UART 146 ******************************************************************************/ 147 #define USART1_BASE U(0x40330000) 148 #define USART2_BASE U(0x400E0000) 149 #define USART3_BASE U(0x400F0000) 150 #define UART4_BASE U(0x40100000) 151 #define UART5_BASE U(0x40110000) 152 #define USART6_BASE U(0x40220000) 153 #define UART7_BASE U(0x40370000) 154 #define UART8_BASE U(0x40380000) 155 #define UART9_BASE U(0x402C0000) 156 #define STM32MP_NB_OF_UART U(9) 157 158 /* For UART crash console */ 159 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 160 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 161 #define STM32MP_DEBUG_USART_BASE USART2_BASE 162 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 163 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 164 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 165 #define DEBUG_UART_TX_GPIO_PORT 4 166 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 167 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 168 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 169 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 170 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 171 #define DEBUG_UART_RST_REG RCC_USART2CFGR 172 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 173 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 174 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 175 176 /******************************************************************************* 177 * STM32MP2 SDMMC 178 ******************************************************************************/ 179 #define STM32MP_SDMMC1_BASE U(0x48220000) 180 #define STM32MP_SDMMC2_BASE U(0x48230000) 181 #define STM32MP_SDMMC3_BASE U(0x48240000) 182 183 /******************************************************************************* 184 * STM32MP2 BSEC / OTP 185 ******************************************************************************/ 186 /* 187 * 367 available OTPs, the other are masked 188 * - ECIES key: 368 to 375 (only readable by bootrom) 189 * - HWKEY: 376 to 383 (never reloadable or readable) 190 */ 191 #define STM32MP2_OTP_MAX_ID U(0x16F) 192 #define STM32MP2_MID_OTP_START U(0x80) 193 #define STM32MP2_UPPER_OTP_START U(0x100) 194 195 /* OTP labels */ 196 #define PART_NUMBER_OTP "part-number-otp" 197 #define PACKAGE_OTP "package-otp" 198 #define HCONF1_OTP "otp124" 199 #define NAND_OTP "otp16" 200 #define NAND2_OTP "otp20" 201 #define BOARD_ID_OTP "board-id" 202 #define UID_OTP "uid-otp" 203 #define LIFECYCLE2_OTP "otp18" 204 #define PKH_OTP "otp144" 205 #define ENCKEY_OTP "otp260" 206 207 /* OTP mask */ 208 /* PACKAGE */ 209 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 210 #define PACKAGE_OTP_PKG_SHIFT U(0) 211 212 /* IWDG OTP */ 213 #define HCONF1_OTP_IWDG_HW_POS U(0) 214 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 215 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 216 217 /* NAND OTP */ 218 /* NAND parameter storage flag */ 219 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 220 221 /* NAND page size in bytes */ 222 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 223 #define NAND_PAGE_SIZE_SHIFT U(29) 224 #define NAND_PAGE_SIZE_2K U(0) 225 #define NAND_PAGE_SIZE_4K U(1) 226 #define NAND_PAGE_SIZE_8K U(2) 227 228 /* NAND block size in pages */ 229 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 230 #define NAND_BLOCK_SIZE_SHIFT U(27) 231 #define NAND_BLOCK_SIZE_64_PAGES U(0) 232 #define NAND_BLOCK_SIZE_128_PAGES U(1) 233 #define NAND_BLOCK_SIZE_256_PAGES U(2) 234 235 /* NAND number of block (in unit of 256 blocks) */ 236 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 237 #define NAND_BLOCK_NB_SHIFT U(19) 238 #define NAND_BLOCK_NB_UNIT U(256) 239 240 /* NAND bus width in bits */ 241 #define NAND_WIDTH_MASK BIT_32(18) 242 #define NAND_WIDTH_SHIFT U(18) 243 244 /* NAND number of ECC bits per 512 bytes */ 245 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 246 #define NAND_ECC_BIT_NB_SHIFT U(15) 247 #define NAND_ECC_BIT_NB_UNSET U(0) 248 #define NAND_ECC_BIT_NB_1_BITS U(1) 249 #define NAND_ECC_BIT_NB_4_BITS U(2) 250 #define NAND_ECC_BIT_NB_8_BITS U(3) 251 #define NAND_ECC_ON_DIE U(4) 252 253 /* NAND number of planes */ 254 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 255 256 /* NAND2 OTP */ 257 #define NAND2_PAGE_SIZE_SHIFT U(16) 258 259 /* NAND2 config distribution */ 260 #define NAND2_CONFIG_DISTRIB BIT_32(0) 261 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 262 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 263 264 /* MONOTONIC OTP */ 265 #define MAX_MONOTONIC_VALUE U(32) 266 267 /* UID OTP */ 268 #define UID_WORD_NB U(3) 269 270 /* Lifecycle OTP */ 271 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 272 273 /******************************************************************************* 274 * STM32MP2 TAMP 275 ******************************************************************************/ 276 #define PLAT_MAX_TAMP_INT U(5) 277 #define PLAT_MAX_TAMP_EXT U(3) 278 #define TAMP_BASE U(0x46010000) 279 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 280 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 281 #define TAMP_BKP_REG_CLK CK_BUS_RTC 282 #define TAMP_BKP_SEC_NUMBER U(10) 283 #define TAMP_COUNTR U(0x40) 284 285 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 286 static inline uintptr_t tamp_bkpr(uint32_t idx) 287 { 288 return TAMP_BKP_REGISTER_BASE + (idx << 2); 289 } 290 #endif 291 292 /******************************************************************************* 293 * STM32MP2 DDRCTRL 294 ******************************************************************************/ 295 #define DDRCTRL_BASE U(0x48040000) 296 297 /******************************************************************************* 298 * STM32MP2 DDRDBG 299 ******************************************************************************/ 300 #define DDRDBG_BASE U(0x48050000) 301 302 /******************************************************************************* 303 * STM32MP2 DDRPHYC 304 ******************************************************************************/ 305 #define DDRPHYC_BASE U(0x48C00000) 306 307 /******************************************************************************* 308 * Miscellaneous STM32MP1 peripherals base address 309 ******************************************************************************/ 310 #define BSEC_BASE U(0x44000000) 311 #define DBGMCU_BASE U(0x4A010000) 312 #define HASH_BASE U(0x42010000) 313 #define RTC_BASE U(0x46000000) 314 #define STGEN_BASE U(0x48080000) 315 #define SYSCFG_BASE U(0x44230000) 316 317 /******************************************************************************* 318 * STM32MP CA35SSC 319 ******************************************************************************/ 320 #define A35SSC_BASE U(0x48800000) 321 322 /******************************************************************************* 323 * REGULATORS 324 ******************************************************************************/ 325 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 326 #define PLAT_NB_RDEVS U(19) 327 /* 2 FIXED */ 328 #define PLAT_NB_FIXED_REGUS U(2) 329 /* No GPIO regu */ 330 #define PLAT_NB_GPIO_REGUS U(0) 331 332 /******************************************************************************* 333 * Device Tree defines 334 ******************************************************************************/ 335 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 336 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 337 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 338 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 339 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2" 340 #define DT_UART_COMPAT "st,stm32h7-uart" 341 342 #endif /* STM32MP2_DEF_H */ 343