fix(st): use KEEP for .dtb_image and .bl2_image sections

Use KEEP keyword in linker scripts that are used to build .stm32 files.
This avoids them being removed if --gc-sections option is used.

Chan

fix(st): use KEEP for .dtb_image and .bl2_image sections

Use KEEP keyword in linker scripts that are used to build .stm32 files.
This avoids them being removed if --gc-sections option is used.

Change-Id: If8e98a293199184ef3cabc45da8de6cd505d9886
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(rk3588): report actual measured PVTPLL clocks

The GRF block includes a counter that measures PVTPLL clock pulses after
the CON1 register, exposed via STATUS1 and STATUS2. The counter uses an
in

feat(rk3588): report actual measured PVTPLL clocks

The GRF block includes a counter that measures PVTPLL clock pulses after
the CON1 register, exposed via STATUS1 and STATUS2. The counter uses an
input clock that can be configured in the CRU block; however, in the
current ATF implementation it is always XIN = 24 MHz.

The counter accumulates PVTPLL pulses for a window of:

measurement_time = CON1 / input_frequency

Since CON1 is fixed to 24, the current implementation measures over:

24 / 24 MHz = 1 µs

The resulting count is stored in the lower 14 bits of STATUS2.

This commit waits 2 µs (ensuring the 1 µs accumulation period completes)
and computes the PVTPLL frequency from the measured value. While CON1
could be increased for higher accuracy (as long as the 14-bit counter
does not overflow), this change keeps the existing 1 µs window for
simplicity.

With this feature, PVTPLL frequency can be measured with ~1 MHz
accuracy, instead of reporting only the configured frequency, which can
hide information related to chip degradation and environmental effects
impacting PVTPLL clocks.

Ideally the flow of measuring PVTPLL clocks should be the same for the
rest of RK35xx devices with minor tweaks at most.

Change-Id: Idc18246e8d794777f0dacc7820f15fcecc00af33
Signed-off-by: Hüseyin BIYIK <boogiepop@gmx.com>

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Merge "fix(st): avoid enormous tf-a-stm32mp13*stm32" into integration

Merge "docs(threat-model): clarify scope of experimental features" into integration

Merge "fix(nxp-ddr): fix improper disable of first DDRC" into integration

Merge changes from topic "xl/v2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V2 erratum 4302968
fix(cpus): workaround for Neoverse-V2 erratum 3888126

fix(st): avoid enormous tf-a-stm32mp13*stm32

The current STM32MP13xx build produces tf-a-stm32mp13*stm32 which is
about 800 MiB is size. This is caused by default build-id emitted by
GNU linker and

fix(st): avoid enormous tf-a-stm32mp13*stm32

The current STM32MP13xx build produces tf-a-stm32mp13*stm32 which is
about 800 MiB is size. This is caused by default build-id emitted by
GNU linker and no-pie build. Change the linker flags such that the
build is static and no build-id is generated. This produces expected
binary, with the right size, which works on the actual hardware again.
This fix is similar to 72f4b70e8e8e ("fix(rcar-layout): fix tool build").

This failure is triggered using most of arm-linux-* toolchains, which
are generated by OE-core 5.0 Scarthgap, arm-linux-gnueabi* 15.2.0 in
Debian and such toolchain. The arm-none-eabi- toolchains do not seem
to trigger this.

Change-Id: I0f7d9f330dbe08d6adf491ed79b3a10a4adfecc7
Fixes: 6d26d75c374b ("fix(st): set no-pie option when building ST elf file")
Signed-off-by: Marek Vasut <marex@nabladev.com>

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Merge changes I20c97011,Ia1facabb into integration

* changes:
fix(rk3576): shorten names to fit into the allocated space
fix(debugfs): allocate enough space to fit all names

Merge changes from topic "xl/c1pro-errata-fix" into integration

* changes:
refactor(cpus): move CVE to the end of errata workaround
fix(cpus): fix feature detection for C1-Pro erratum 3686597

refactor(cpus): move CVE to the end of errata workaround

To comply with errata ordering, the errata workaround should
be before CVE workaround.

Change-Id: I2e13b479b44c5f86399e540e53ad02086ad9d16e

refactor(cpus): move CVE to the end of errata workaround

To comply with errata ordering, the errata workaround should
be before CVE workaround.

Change-Id: I2e13b479b44c5f86399e540e53ad02086ad9d16e
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): fix feature detection for C1-Pro erratum 3686597

C1-Pro erratum 3686597 needs SME feature detection, which
can be none, compile time and run time, any errata fix involved
the feature need

fix(cpus): fix feature detection for C1-Pro erratum 3686597

C1-Pro erratum 3686597 needs SME feature detection, which
can be none, compile time and run time, any errata fix involved
the feature needs to follow the convention.

Change-Id: Ie9da0cde56a653ab0dbea702e09855e2e28dfd3d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(nxp-ddr): fix improper disable of first DDRC

Fixes an issue where the first DDRC is disabled improperly
when two DDRCs are present and only the second DDRC slot is
populated with a DIMM.

Change

fix(nxp-ddr): fix improper disable of first DDRC

Fixes an issue where the first DDRC is disabled improperly
when two DDRCs are present and only the second DDRC slot is
populated with a DIMM.

Change-Id: Ia4f71c5e79fa318a81a291080494f25e76fd987f
Signed-off-by: Roman Meier <romameie@outlook.com>

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fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FE

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FEATURE. Setting -march directly can lead to unexpected results
when using the above flags and is generally not recommended within tfa.

This patch migrates all instances of -march=armv8-a+crc to
ARM_ARCH_FEATURE=crc. Arm platforms (via arm_common.mk) are checked and
those that support cores greater than arm8.1 do not get the flag as it
is automatically pulled in.

Change-Id: I846f97367eab9529524a2805d5b87d34cce2360f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(rcar3): rephrase RCAR_BL31_CRASH_BASE definition

Since RCAR_BL31_CRASH_BASE depends on the RCAR_TRUSTED_SRAM_BASE,
use it for the RCAR_BL31_CRASH_BASE calculation.

Change-Id: Ibf3b4747a8dbd8fb

feat(rcar3): rephrase RCAR_BL31_CRASH_BASE definition

Since RCAR_BL31_CRASH_BASE depends on the RCAR_TRUSTED_SRAM_BASE,
use it for the RCAR_BL31_CRASH_BASE calculation.

Change-Id: Ibf3b4747a8dbd8fbbff793387d841e615788a003
Signed-off-by: Vincent Bryce <vincent.bryce@cogentembedded.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

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fix(rcar): enable intialisation code for EL3 to NS-EL1 handoff

Enable initialisation code for handoff from EL3 to NS-EL1 using the
INIT_UNUSED_NS_EL2 flag on both R-Car Gen3 and Gen4 SoCs. This is
u

fix(rcar): enable intialisation code for EL3 to NS-EL1 handoff

Enable initialisation code for handoff from EL3 to NS-EL1 using the
INIT_UNUSED_NS_EL2 flag on both R-Car Gen3 and Gen4 SoCs. This is
used by cores which proceed directly from EL3 to NS-ES1 and have no
code in NS-EL2.

Change-Id: I4d2441e23a0020fe98298c7f329514686ca62fe4
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Marek: update commit message, combined for Gen3 and Gen4

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Merge "fix(cpus): workaround for Cortex-A76AE erratum 2753838" into integration

fix(cpus): workaround for Neoverse-V2 erratum 4302968

Neoverse-V2 erratum 4302968 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR5_E

fix(cpus): workaround for Neoverse-V2 erratum 4302968

Neoverse-V2 erratum 4302968 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I42b27e19d61a7f9c57efe1b5f5336d165eb98210
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3888126

Neoverse-V2 erratum 3888126 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR2[2

fix(cpus): workaround for Neoverse-V2 erratum 3888126

Neoverse-V2 erratum 3888126 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I4068aa73d38a70c00d66bb894169be2659d67de7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 4302969

Cortex-X2 erratum 4302969 that applies to revisions
r0p0, r1p0, r2p0 and r2p1, and is still open.

This erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for Cortex-X2 erratum 4302969

Cortex-X2 erratum 4302969 that applies to revisions
r0p0, r1p0, r2p0 and r2p1, and is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I6c5de5843f2199fa697f8336558fa56a87ee846d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 3888122

Cortex-X2 erratum 3888122 that applies to revisions r0p0,
r1p0, r2p0 and r2p1 and is still open.

The erratum can be avoided by setting CPUACTLR2[

fix(cpus): workaround for Cortex-X2 erratum 3888122

Cortex-X2 erratum 3888122 that applies to revisions r0p0,
r1p0, r2p0 and r2p1 and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I368cfdd216ea5875b81640415ff71b15f46ea953
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 2753838

Cortex-A76AE erratum 2753838 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by addin

fix(cpus): workaround for Cortex-A76AE erratum 2753838

Cortex-A76AE erratum 2753838 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by adding a DSB instruction before
the ISB of the power-down code sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/latest/

Change-Id: I338834a21c14879faee5280876a59153d549cb7b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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feat(mt8196): add audio SMC cmd implementation

To enable audio SMMU, MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS setting
is required to allow audio to use its own DAPC IP domain. If not
set, audio access to D

feat(mt8196): add audio SMC cmd implementation

To enable audio SMMU, MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS setting
is required to allow audio to use its own DAPC IP domain. If not
set, audio access to DRAM will be blocked.
- Add MT8196 specific code
- Enable for MT8196

Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com>
Change-Id: I0dfc35d8a7116bcd69d6ca643a5ce527bb32676e

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Merge changes from topic "xl/x925-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X925 erratum 3865185
fix(cpus): workaround for Cortex-X925 erratum 3730893
fix(cpus): wor

Merge changes from topic "xl/x925-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X925 erratum 3865185
fix(cpus): workaround for Cortex-X925 erratum 3730893
fix(cpus): workaround for Cortex-X925 erratum 3692980
fix(cpus): workaround for Cortex-X925 erratum 3324334
fix(cpus): workaround for Cortex-X925 erratum 2933290
fix(cpus): workaround for Cortex-X925 erratum 2922378
fix(cpus): workaround for Cortex-X925 erratum 2921199

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fix(cpus): workaround for Cortex-X925 erratum 3865185

Cortex-X925 erratum 3865185 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

Load issued to Non-Cacheable or De

fix(cpus): workaround for Cortex-X925 erratum 3865185

Cortex-X925 erratum 3865185 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

Load issued to Non-Cacheable or Device GRE memory can
read stale data brought in by an earlier load to the
same cache-line thereby violating ordering requirements.
This erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: Iff224ef82bd1cb9aff8d6b11451e2ac1d048149f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X925 erratum 3730893

Cortex-X925 erratum 3730893 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

PE executing a load instruction th

fix(cpus): workaround for Cortex-X925 erratum 3730893

Cortex-X925 erratum 3730893 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

PE executing a load instruction that accesses a memory
region which crosses a 4K boundary might cause a deadlock.
This erratum can be avoided by setting CPUACTLR_EL1[60:58]
to 3'b001, which has a small perf impact.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I0245183669255afb0d3ec71cafa058aa72129de0
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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