1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31workaround_runtime_start c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 32 speculation_barrier 33workaround_runtime_end c1_pro, ERRATUM(3338470) 34 35check_erratum_ls c1_pro, ERRATUM(3338470), CPU_REV(0, 0) 36 37workaround_reset_start c1_pro, ERRATUM(3362007), ERRATA_C1PRO_3362007 38 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(27) 39workaround_reset_end c1_pro, ERRATUM(3362007) 40 41check_erratum_ls c1_pro, ERRATUM(3362007), CPU_REV(0, 0) 42 43workaround_reset_start c1_pro, ERRATUM(3619847), ERRATA_C1PRO_3619847 44 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(42) 45workaround_reset_end c1_pro, ERRATUM(3619847) 46 47check_erratum_ls c1_pro, ERRATUM(3619847), CPU_REV(0, 0) 48 49workaround_reset_start c1_pro, ERRATUM(3684268), ERRATA_C1PRO_3684268 50 sysreg_bit_set C1_PRO_IMP_CPUECTLR2_EL1, BIT(49) 51 dsb sy 52workaround_reset_end c1_pro, ERRATUM(3684268) 53 54check_erratum_ls c1_pro, ERRATUM(3684268), CPU_REV(1, 0) 55 56workaround_runtime_start c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 57#if ENABLE_SME_FOR_NS 58#if ENABLE_SME_FOR_NS == 2 59 is_feat_sme_present_asm x1 60 beq 1f 61#endif 62 63 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(57) 64 dsb sy 65 661: 67#endif 68workaround_runtime_end c1_pro, ERRATUM(3686597) 69 70check_erratum_ls c1_pro, ERRATUM(3686597), CPU_REV(1, 0) 71 72workaround_reset_start c1_pro, ERRATUM(3694158), ERRATA_C1PRO_3694158 73 mov x0, #5 74 msr C1_PRO_IMP_CPUPSELR_EL3, x0 75 isb 76 ldr x0, =0xd503329f 77 msr C1_PRO_IMP_CPUPOR_EL3, x0 78 ldr x0, =0xfffff3ff 79 msr C1_PRO_IMP_CPUPMR_EL3, x0 80 mov x1, #0 81 orr x1, x1, #1<<0 82 orr x1, x1, #3<<4 83 orr x1, x1, #0xf<<6 84 orr x1, x1, #1<<22 85 orr x1, x1, #1<<32 86 msr C1_PRO_IMP_CPUPCR_EL3, x1 87workaround_reset_end c1_pro, ERRATUM(3694158) 88 89check_erratum_ls c1_pro, ERRATUM(3694158), CPU_REV(1, 1) 90 91workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 92 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 93workaround_reset_end c1_pro, ERRATUM(3706576) 94 95check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 96 97add_erratum_entry c1_pro, ERRATUM(3300099), ERRATA_C1PRO_3300099 98.global check_erratum_c1_pro_3300099 99check_erratum_ls c1_pro, ERRATUM(3300099), CPU_REV(1, 0) 100 101 /* ----------------------------------------------------------- 102 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 103 * workaround by disabling the affected prefetcher 104 * via IMP_CPUECTLR_EL1[49]. 105 * ----------------------------------------------------------- 106 */ 107workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 108 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(49) 109 dsb sy 110workaround_reset_end c1_pro, CVE(2024, 7881) 111 112check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 113 114cpu_reset_func_start c1_pro 115 /* ---------------------------------------------------- 116 * Disable speculative loads 117 * ---------------------------------------------------- 118 */ 119 msr SSBS, xzr 120 apply_erratum c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 121 /* model bug: not cleared on reset */ 122 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 123 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 124 enable_mpmm 125cpu_reset_func_end c1_pro 126 127 /* ---------------------------------------------------- 128 * HW will do the cache maintenance while powering down 129 * ---------------------------------------------------- 130 */ 131func c1_pro_core_pwr_dwn 132 /* --------------------------------------------------- 133 * Flip CPU power down bit in power control register. 134 * It will be set on powerdown and cleared on wakeup 135 * --------------------------------------------------- 136 */ 137 apply_erratum c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 138 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 139 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 140 isb 141 signal_pabandon_handled 142 ret 143endfunc c1_pro_core_pwr_dwn 144 145 /* --------------------------------------------- 146 * This function provides Arm C1-Pro specific 147 * register information for crash reporting. 148 * It needs to return with x6 pointing to 149 * a list of register names in ascii and 150 * x8 - x15 having values of registers to be 151 * reported. 152 * --------------------------------------------- 153 */ 154.section .rodata.c1_pro_regs, "aS" 155c1_pro_regs: /* The ASCII list of register names to be reported */ 156 .asciz "imp_cpuectlr_el1", "" 157 158func c1_pro_cpu_reg_dump 159 adr x6, c1_pro_regs 160 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 161 ret 162endfunc c1_pro_cpu_reg_dump 163 164declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 165 c1_pro_reset_func, \ 166 c1_pro_core_pwr_dwn 167