Juno: Add support for image overlaying in Trusted SRAM

This patch allows the BL3-1 NOBITS section to overlap the BL1 R/W
section since the former will always be used after the latter.
Similarly, the

Juno: Add support for image overlaying in Trusted SRAM

This patch allows the BL3-1 NOBITS section to overlap the BL1 R/W
section since the former will always be used after the latter.
Similarly, the BL3-2 NOBITS section can overlay the BL2 image
when BL3-2 is loaded in Trusted SRAM.

Due to the current size of the images, there is no actual overlap.
Nevertheless, this reorganization may help to optimise the Trusted
SRAM usage when the images size grows.

Note that because BL3-1 NOBITS section is allowed to overlap the
BL1 R/W section, BL1 global variables will remain valid only until
execution reaches the BL3-1 entry point during a cold boot.

Documentation updated accordingly.

Fixes ARM-software/tf-issues#254

Change-Id: Id538f4d1c7f1f7858108280fd7b97e138572b879

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User Guide: Enable secure memory on Foundation FVP

Previously, the User Guide recommended launching the Foundation
FVP with the parameter --no-secure-memory, which disabled security
control of the a

User Guide: Enable secure memory on Foundation FVP

Previously, the User Guide recommended launching the Foundation
FVP with the parameter --no-secure-memory, which disabled security
control of the address map. This was due to missing support for
secure memory regions in v1 of the Foundation FVP. This is no longer
needed as secure memory is now supported on the Foundation FVP.

This patch updates the User Guide to recommend enabling secure
memory instead.

Change-Id: Ifae53c10ff6e1c7c6724af20e05a3d3a88f6a5ad

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Bug fix: initialize bl30_image_info fields before use

This patch initializes the version field in the bl30_image_info
structure when loading BL30. This initialization must be done before
calling loa

Bug fix: initialize bl30_image_info fields before use

This patch initializes the version field in the bl30_image_info
structure when loading BL30. This initialization must be done before
calling load_image().

Fixes ARM-software/tf-issues#274

Change-Id: I74a05167d66fff51d257ad611abc7b5436e5d912

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Merge pull request #222 from jbech-linaro/user_guide_toc_links

Create TOC links in the User Guide markdown file

Prevent optimisation of sysregs accessors calls

Calls to system register read accessors functions may be optimised
out by the compiler if called twice in a row for the same register.
This is because

Prevent optimisation of sysregs accessors calls

Calls to system register read accessors functions may be optimised
out by the compiler if called twice in a row for the same register.
This is because the compiler is not aware that the result from
the instruction may be modified by external agents. Therefore, if
nothing modifies the register between the 2 reads as far as the
compiler knows then it might consider that it is useless to read
it twice and emit only 1 call.

This behaviour is faulty for registers that may not have the same
value if read twice in succession. E.g.: counters, timer
control/countdown registers, GICv3 interrupt status registers and
so on.

The same problem happens for calls to system register write
accessors functions. The compiler might optimise out some calls
if it considers that it will produce the same result. Again, this
behaviour is faulty for cases where intermediate writes to these
registers make a difference in the system.

This patch fixes the problem by making these assembly register
accesses volatile.

Fixes ARM-software/tf-issues#273

Change-Id: I33903bc4cc4eea8a8d87bc2c757909fbb0138925

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Create Table of Content links in markdown files

Fixes arm-software/tf-issues#276

Merge pull request #226 from sandrine-bailleux/sb/tf-issues-279

fip_create: don't succeed if one of the passed files doesn't exist

Merge pull request #227 from soby-mathew/sm/afflvl_fix

Fix CPU_SUSPEND when invoked with affinity level higher than get_max_aff...

Merge pull request #225 from sandrine-bailleux/sb/remove-IRQ_SEC_SGI_8

Remove IRQ_SEC_SGI_8 constant

Specify FIP filename at build time

This patch allows to define the name of the FIP at build time by
defining the FIP_NAME variable. If FIP_NAME is not defined, default
name 'fip.bin' is used.

Docum

Specify FIP filename at build time

This patch allows to define the name of the FIP at build time by
defining the FIP_NAME variable. If FIP_NAME is not defined, default
name 'fip.bin' is used.

Documentation updated accordingly.

Change-Id: Ic41f42aac379b0c958b3dfd02863ba8ba7108710

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Fix CPU_SUSPEND when invoked with affinity level higher than get_max_afflvl()

This patch fixes the assertion failure when CPU_SUSPEND is invoked with
an affinity level higher than supported by the p

Fix CPU_SUSPEND when invoked with affinity level higher than get_max_afflvl()

This patch fixes the assertion failure when CPU_SUSPEND is invoked with
an affinity level higher than supported by the platform by adding suitable
checks for affinity level within `psci_cpu_suspend`. Also added suitable
bound checks within `psci_aff_map_get_idx` to prevent indexing beyond array
limits.

Fixes ARM-software/tf-issues#260

Change-Id: I04b75c49729e6c6d1983add590f60146c8fc3630

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fip_create: don't succeed if one of the passed files doesn't exist

If one of the files passed to fip_create on the command line doesn't
exist, it will print an error message but produce an incomplet

fip_create: don't succeed if one of the passed files doesn't exist

If one of the files passed to fip_create on the command line doesn't
exist, it will print an error message but produce an incomplete
fip.bin file and report success. This behaviour could potentially
hide errors made in the command line arguments.

This patch addresses the issue by having the tool bail out if one of
the supplied files can't be processed.

Signed-off-by: Kévin Petit <kevin.petit@arm.com>

Fixes ARM-software/tf-issues#279

Change-Id: I1c7d87d09eb4c063005b7969bdaad1d043c29dec

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Remove IRQ_SEC_SGI_8 constant

In both FVP and Juno ports, IRQ #16, which is a PPI, is incorrectly
identified as secure SGI #8 through the constant IRQ_SEC_SGI_8.
This patch removes it.

Fixes ARM-so

Remove IRQ_SEC_SGI_8 constant

In both FVP and Juno ports, IRQ #16, which is a PPI, is incorrectly
identified as secure SGI #8 through the constant IRQ_SEC_SGI_8.
This patch removes it.

Fixes ARM-software/tf-issues#282

Change-Id: I9e52d849611ffcd2b1f28e56dd156c5b217ed63e

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Merge pull request #223 from sandrine-bailleux/sb/fix-fiptool-target

Fix problem of dependencies on the fiptool makefile target

Merge pull request #224 from soby-mathew/sm/fix_mpidr_aff_map_nodes_t

Fix the array size of mpidr_aff_map_nodes_t.

Fix the array size of mpidr_aff_map_nodes_t.

This patch fixes the array size of mpidr_aff_map_nodes_t which
was less by one element.

Fixes ARM-software/tf-issues#264

Change-Id: I48264f6f9e7046a3d0

Fix the array size of mpidr_aff_map_nodes_t.

This patch fixes the array size of mpidr_aff_map_nodes_t which
was less by one element.

Fixes ARM-software/tf-issues#264

Change-Id: I48264f6f9e7046a3d0f4cbcd63b9ba49657e8818

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Fix problem of dependencies on the fiptool makefile target

The 'fiptool' target doesn't depend on fip_create's source files,
neither directly nor indirectly. As a result, the FIP tool is not
rebuilt

Fix problem of dependencies on the fiptool makefile target

The 'fiptool' target doesn't depend on fip_create's source files,
neither directly nor indirectly. As a result, the FIP tool is not
rebuilt whenever its source files change.

This patch makes the ${FIPTOOL} target into a phony target so that the
FIP tool's sub-makefile is always called. The sub-makefile correctly
handles the dependencies. It also moves the completion message into
the sub-makefile so that it is only displayed when the tool is
actually recompiled.

Fixes ARM-software/tf-issues#278

Change-Id: Ia027519fe51d3c42be30665d1ad20a7b89fa350f

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Merge pull request #220 from soby-mathew/sm/reassign_crash_console

Use the BL3-1 runtime console as the crash console.

Merge pull request #221 from achingupta/ag/tf-issues#272

Precede a 'sev' with a 'dsb' in bakery lock code

Precede a 'sev' with a 'dsb' in bakery lock code

This patch fixes a bug in the bakery lock implementation where a data
synchronisation barrier instruction is not issued before sending an event as
ma

Precede a 'sev' with a 'dsb' in bakery lock code

This patch fixes a bug in the bakery lock implementation where a data
synchronisation barrier instruction is not issued before sending an event as
mandated by the ARMv8 ARM. This can cause a event to be signalled before the
related memory accesses have completed resulting in erroneous execution.

Fixes ARM-software/tf-issues#272

Change-Id: I5ce02bf70afb001d967b9fa4c3f77442931d5349

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Use the BL3-1 runtime console as the crash console.

This patch reassigns the crash console on Juno and FVP to use the runtime
BL3-1 console. The crash console is changed to SoC UART0 (UART2) from th

Use the BL3-1 runtime console as the crash console.

This patch reassigns the crash console on Juno and FVP to use the runtime
BL3-1 console. The crash console is changed to SoC UART0 (UART2) from the
previous FPGA UART0 (UART0) on Juno. In FVP, it is changed from UART0 to
UART1.

Fixes ARM-software/tf-issues#256

Change-Id: I7df54f86ca00ec2652c27261dd66a94c12610816

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Merge pull request #219 from jcastillo-arm/jc/tf-issues/253

Improvements to ARM GIC driver
Juno: Use the generic ARM GIC driver

Juno: Use the generic ARM GIC driver

This patch replaces the usage of the GIC private driver in Juno with
the generic ARM GIC driver. The private driver is no longer necessary
and has been removed f

Juno: Use the generic ARM GIC driver

This patch replaces the usage of the GIC private driver in Juno with
the generic ARM GIC driver. The private driver is no longer necessary
and has been removed from the Juno port.

Fixes ARM-software/tf-issues#253

Change-Id: I6aaabc252e5e6fb5fcf44ab6d0febd9b38791056

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Improvements to ARM GIC driver

This patch introduces several improvements to the ARM GIC driver:

* In function gicd_set_itargetsr(), target CPU is specified using
the same bit mask detailed in th

Improvements to ARM GIC driver

This patch introduces several improvements to the ARM GIC driver:

* In function gicd_set_itargetsr(), target CPU is specified using
the same bit mask detailed in the GICD_ITARGETSRn register instead
of the CPU linear ID, removing the dependency between bit position
and linear ID in the platform porting. The current CPU bit mask
may be obtained by reading GICD_ITARGETSR0.

* PPIs and SGIs are initialized in arm_gic_pcpu_distif_setup().
SPIs are initialized in arm_gic_distif_setup().

* By default, non secure interrupts are assigned the maximum
priority allowed to a non secure interrupt (defined by
GIC_HIGHEST_NS_PRIORITY).

* GICR base address is allowed to be NULL for GICv1 and GICv2.

Change-Id: Ie2837fe860d43b2282e582dfdb13c39c6186f232

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Merge pull request #218 from soby-mathew/sm/add_cpu_ops_warning

Add level specific cache operations and changes to errata workaround mechanism