1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <assert.h> 32 #include <arch_helpers.h> 33 #include <arm_gic.h> 34 #include <cci.h> 35 #include <css_def.h> 36 #include <debug.h> 37 #include <errno.h> 38 #include <plat_arm.h> 39 #include <platform.h> 40 #include <platform_def.h> 41 #include <psci.h> 42 #include "css_scpi.h" 43 44 unsigned long wakeup_address; 45 46 #if ARM_RECOM_STATE_ID_ENC 47 /* 48 * The table storing the valid idle power states. Ensure that the 49 * array entries are populated in ascending order of state-id to 50 * enable us to use binary search during power state validation. 51 * The table must be terminated by a NULL entry. 52 */ 53 const unsigned int arm_pm_idle_states[] = { 54 /* State-id - 0x01 */ 55 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 56 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 57 /* State-id - 0x02 */ 58 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 59 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 60 /* State-id - 0x22 */ 61 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 62 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 63 0, 64 }; 65 #endif 66 67 /******************************************************************************* 68 * Private function to program the mailbox for a cpu before it is released 69 * from reset. 70 ******************************************************************************/ 71 static void css_program_mailbox(uint64_t mpidr, uint64_t address) 72 { 73 uint64_t linear_id; 74 uint64_t mbox; 75 76 linear_id = plat_arm_calc_core_pos(mpidr); 77 mbox = TRUSTED_MAILBOXES_BASE + (linear_id << TRUSTED_MAILBOX_SHIFT); 78 *((uint64_t *) mbox) = address; 79 flush_dcache_range(mbox, sizeof(mbox)); 80 } 81 82 /******************************************************************************* 83 * Handler called when a power domain is about to be turned on. The 84 * level and mpidr determine the affinity instance. 85 ******************************************************************************/ 86 int css_pwr_domain_on(u_register_t mpidr) 87 { 88 /* 89 * SCP takes care of powering up parent power domains so we 90 * only need to care about level 0 91 */ 92 93 /* 94 * Setup mailbox with address for CPU entrypoint when it next powers up 95 */ 96 css_program_mailbox(mpidr, wakeup_address); 97 98 scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on, 99 scpi_power_on); 100 101 return PSCI_E_SUCCESS; 102 } 103 104 /******************************************************************************* 105 * Handler called when a power level has just been powered on after 106 * being turned off earlier. The target_state encodes the low power state that 107 * each level has woken up from. 108 ******************************************************************************/ 109 void css_pwr_domain_on_finish(const psci_power_state_t *target_state) 110 { 111 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 112 ARM_LOCAL_STATE_OFF); 113 114 /* 115 * Perform the common cluster specific operations i.e enable coherency 116 * if this cluster was off. 117 */ 118 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 119 ARM_LOCAL_STATE_OFF) 120 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 121 122 /* Enable the gic cpu interface */ 123 arm_gic_cpuif_setup(); 124 125 /* todo: Is this setup only needed after a cold boot? */ 126 arm_gic_pcpu_distif_setup(); 127 128 /* Clear the mailbox for this cpu. */ 129 css_program_mailbox(read_mpidr_el1(), 0); 130 } 131 132 /******************************************************************************* 133 * Common function called while turning a cpu off or suspending it. It is called 134 * from css_off() or css_suspend() when these functions in turn are called for 135 * power domain at the highest power level which will be powered down. It 136 * performs the actions common to the OFF and SUSPEND calls. 137 ******************************************************************************/ 138 static void css_power_down_common(const psci_power_state_t *target_state) 139 { 140 uint32_t cluster_state = scpi_power_on; 141 142 /* Prevent interrupts from spuriously waking up this cpu */ 143 arm_gic_cpuif_deactivate(); 144 145 /* Cluster is to be turned off, so disable coherency */ 146 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 147 ARM_LOCAL_STATE_OFF) { 148 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 149 cluster_state = scpi_power_off; 150 } 151 152 /* 153 * Ask the SCP to power down the appropriate components depending upon 154 * their state. 155 */ 156 scpi_set_css_power_state(read_mpidr_el1(), 157 scpi_power_off, 158 cluster_state, 159 scpi_power_on); 160 } 161 162 /******************************************************************************* 163 * Handler called when a power domain is about to be turned off. The 164 * target_state encodes the power state that each level should transition to. 165 ******************************************************************************/ 166 static void css_pwr_domain_off(const psci_power_state_t *target_state) 167 { 168 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 169 ARM_LOCAL_STATE_OFF); 170 171 css_power_down_common(target_state); 172 } 173 174 /******************************************************************************* 175 * Handler called when a power domain is about to be suspended. The 176 * target_state encodes the power state that each level should transition to. 177 ******************************************************************************/ 178 static void css_pwr_domain_suspend(const psci_power_state_t *target_state) 179 { 180 /* 181 * Juno has retention only at cpu level. Just return 182 * as nothing is to be done for retention. 183 */ 184 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 185 ARM_LOCAL_STATE_RET) 186 return; 187 188 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 189 ARM_LOCAL_STATE_OFF); 190 191 /* 192 * Setup mailbox with address for CPU entrypoint when it next powers up. 193 */ 194 css_program_mailbox(read_mpidr_el1(), wakeup_address); 195 196 css_power_down_common(target_state); 197 } 198 199 /******************************************************************************* 200 * Handler called when a power domain has just been powered on after 201 * having been suspended earlier. The target_state encodes the low power state 202 * that each level has woken up from. 203 * TODO: At the moment we reuse the on finisher and reinitialize the secure 204 * context. Need to implement a separate suspend finisher. 205 ******************************************************************************/ 206 static void css_pwr_domain_suspend_finish( 207 const psci_power_state_t *target_state) 208 { 209 /* 210 * Return as nothing is to be done on waking up from retention. 211 */ 212 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 213 ARM_LOCAL_STATE_RET) 214 return; 215 216 css_pwr_domain_on_finish(target_state); 217 } 218 219 /******************************************************************************* 220 * Handlers to shutdown/reboot the system 221 ******************************************************************************/ 222 static void __dead2 css_system_off(void) 223 { 224 uint32_t response; 225 226 /* Send the power down request to the SCP */ 227 response = scpi_sys_power_state(scpi_system_shutdown); 228 229 if (response != SCP_OK) { 230 ERROR("CSS System Off: SCP error %u.\n", response); 231 panic(); 232 } 233 wfi(); 234 ERROR("CSS System Off: operation not handled.\n"); 235 panic(); 236 } 237 238 static void __dead2 css_system_reset(void) 239 { 240 uint32_t response; 241 242 /* Send the system reset request to the SCP */ 243 response = scpi_sys_power_state(scpi_system_reboot); 244 245 if (response != SCP_OK) { 246 ERROR("CSS System Reset: SCP error %u.\n", response); 247 panic(); 248 } 249 wfi(); 250 ERROR("CSS System Reset: operation not handled.\n"); 251 panic(); 252 } 253 254 /******************************************************************************* 255 * Handler called when the CPU power domain is about to enter standby. 256 ******************************************************************************/ 257 void css_cpu_standby(plat_local_state_t cpu_state) 258 { 259 unsigned int scr; 260 261 assert(cpu_state == ARM_LOCAL_STATE_RET); 262 263 scr = read_scr_el3(); 264 /* Enable PhysicalIRQ bit for NS world to wake the CPU */ 265 write_scr_el3(scr | SCR_IRQ_BIT); 266 isb(); 267 dsb(); 268 wfi(); 269 270 /* 271 * Restore SCR to the original value, synchronisation of scr_el3 is 272 * done by eret while el3_exit to save some execution cycles. 273 */ 274 write_scr_el3(scr); 275 } 276 277 /******************************************************************************* 278 * Export the platform handlers to enable psci to invoke them 279 ******************************************************************************/ 280 static const plat_psci_ops_t css_ops = { 281 .pwr_domain_on = css_pwr_domain_on, 282 .pwr_domain_on_finish = css_pwr_domain_on_finish, 283 .pwr_domain_off = css_pwr_domain_off, 284 .cpu_standby = css_cpu_standby, 285 .pwr_domain_suspend = css_pwr_domain_suspend, 286 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, 287 .system_off = css_system_off, 288 .system_reset = css_system_reset, 289 .validate_power_state = arm_validate_power_state 290 }; 291 292 /******************************************************************************* 293 * Export the platform specific psci ops. 294 ******************************************************************************/ 295 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 296 const plat_psci_ops_t **psci_ops) 297 { 298 *psci_ops = &css_ops; 299 300 wakeup_address = sec_entrypoint; 301 flush_dcache_range((unsigned long)&wakeup_address, 302 sizeof(wakeup_address)); 303 return 0; 304 } 305