1/* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <gic_v2.h> 34#include <platform_def.h> 35#include <v2m_def.h> 36#include "../drivers/pwrc/fvp_pwrc.h" 37#include "../fvp_def.h" 38 39 .globl plat_secondary_cold_boot_setup 40 .globl plat_get_my_entrypoint 41 .globl platform_mem_init 42 .globl plat_is_my_cpu_primary 43 44 .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res 45 ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID 46 ldr \w_tmp, [\x_tmp] 47 ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH 48 cmp \w_tmp, #BLD_GIC_VE_MMAP 49 csel \res, \param1, \param2, eq 50 .endm 51 52 /* ----------------------------------------------------- 53 * void plat_secondary_cold_boot_setup (void); 54 * 55 * This function performs any platform specific actions 56 * needed for a secondary cpu after a cold reset e.g 57 * mark the cpu's presence, mechanism to place it in a 58 * holding pen etc. 59 * TODO: Should we read the PSYS register to make sure 60 * that the request has gone through. 61 * ----------------------------------------------------- 62 */ 63func plat_secondary_cold_boot_setup 64 /* --------------------------------------------- 65 * Power down this cpu. 66 * TODO: Do we need to worry about powering the 67 * cluster down as well here. That will need 68 * locks which we won't have unless an elf- 69 * loader zeroes out the zi section. 70 * --------------------------------------------- 71 */ 72 mrs x0, mpidr_el1 73 ldr x1, =PWRC_BASE 74 str w0, [x1, #PPOFFR_OFF] 75 76 /* --------------------------------------------- 77 * Deactivate the gic cpu interface as well 78 * --------------------------------------------- 79 */ 80 ldr x0, =VE_GICC_BASE 81 ldr x1, =BASE_GICC_BASE 82 fvp_choose_gicmmap x0, x1, x2, w2, x1 83 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) 84 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) 85 str w0, [x1, #GICC_CTLR] 86 87 /* --------------------------------------------- 88 * There is no sane reason to come out of this 89 * wfi so panic if we do. This cpu will be pow- 90 * ered on and reset by the cpu_on pm api 91 * --------------------------------------------- 92 */ 93 dsb sy 94 wfi 95cb_panic: 96 b cb_panic 97endfunc plat_secondary_cold_boot_setup 98 99 /* --------------------------------------------------------------------- 100 * unsigned long plat_get_my_entrypoint (void); 101 * 102 * Main job of this routine is to distinguish between a cold and warm 103 * boot. On FVP, this information can be queried from the power 104 * controller. The Power Control SYS Status Register (PSYSR) indicates 105 * the wake-up reason for the CPU. 106 * 107 * For a cold boot, return 0. 108 * For a warm boot, read the mailbox and return the address it contains. 109 * 110 * TODO: PSYSR is a common register and should be 111 * accessed using locks. Since its not possible 112 * to use locks immediately after a cold reset 113 * we are relying on the fact that after a cold 114 * reset all cpus will read the same WK field 115 * --------------------------------------------------------------------- 116 */ 117func plat_get_my_entrypoint 118 /* --------------------------------------------------------------------- 119 * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC 120 * WakeRequest signal" then it is a warm boot. 121 * --------------------------------------------------------------------- 122 */ 123 mrs x2, mpidr_el1 124 ldr x1, =PWRC_BASE 125 str w2, [x1, #PSYSR_OFF] 126 ldr w2, [x1, #PSYSR_OFF] 127 ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH 128 cmp w2, #WKUP_PPONR 129 beq warm_reset 130 cmp w2, #WKUP_GICREQ 131 beq warm_reset 132 133 /* Cold reset */ 134 mov x0, #0 135 ret 136 137warm_reset: 138 /* --------------------------------------------------------------------- 139 * A mailbox is maintained in the trusted SRAM. It is flushed out of the 140 * caches after every update using normal memory so it is safe to read 141 * it here with SO attributes. 142 * --------------------------------------------------------------------- 143 */ 144 mov_imm x0, MBOX_BASE 145 ldr x0, [x0] 146 cbz x0, _panic 147 ret 148 149 /* --------------------------------------------------------------------- 150 * The power controller indicates this is a warm reset but the mailbox 151 * is empty. This should never happen! 152 * --------------------------------------------------------------------- 153 */ 154_panic: 155 b _panic 156endfunc plat_get_my_entrypoint 157 158 159 /* --------------------------------------------------------------------- 160 * void platform_mem_init (void); 161 * 162 * Nothing to do on FVP, the Trusted SRAM is available straight away 163 * after reset. 164 * --------------------------------------------------------------------- 165 */ 166func platform_mem_init 167 ret 168endfunc platform_mem_init 169 170 171func plat_is_my_cpu_primary 172 mrs x0, mpidr_el1 173 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 174 cmp x0, #FVP_PRIMARY_CPU 175 cset x0, eq 176 ret 177endfunc plat_is_my_cpu_primary 178