1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <arm_def.h> 34 #include <arm_gic.h> 35 #include <assert.h> 36 #include <bl_common.h> 37 #include <cci.h> 38 #include <console.h> 39 #include <debug.h> 40 #include <mmio.h> 41 #include <plat_arm.h> 42 #include <platform.h> 43 44 45 /* 46 * The next 3 constants identify the extents of the code, RO data region and the 47 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 48 * therefore they must be page-aligned. It is the responsibility of the linker 49 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 50 * refer to page-aligned addresses. 51 */ 52 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 53 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 54 #define BL31_END (unsigned long)(&__BL31_END__) 55 56 #if USE_COHERENT_MEM 57 /* 58 * The next 2 constants identify the extents of the coherent memory region. 59 * These addresses are used by the MMU setup code and therefore they must be 60 * page-aligned. It is the responsibility of the linker script to ensure that 61 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 62 * refer to page-aligned addresses. 63 */ 64 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 65 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 66 #endif 67 68 /* 69 * Placeholder variables for copying the arguments that have been passed to 70 * BL3-1 from BL2. 71 */ 72 static entry_point_info_t bl32_image_ep_info; 73 static entry_point_info_t bl33_image_ep_info; 74 75 76 /* Weak definitions may be overridden in specific ARM standard platform */ 77 #pragma weak bl31_early_platform_setup 78 #pragma weak bl31_platform_setup 79 #pragma weak bl31_plat_arch_setup 80 #pragma weak bl31_plat_get_next_image_ep_info 81 #pragma weak plat_get_syscnt_freq 82 83 84 /******************************************************************************* 85 * Return a pointer to the 'entry_point_info' structure of the next image for the 86 * security state specified. BL3-3 corresponds to the non-secure image type 87 * while BL3-2 corresponds to the secure image type. A NULL pointer is returned 88 * if the image does not exist. 89 ******************************************************************************/ 90 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 91 { 92 entry_point_info_t *next_image_info; 93 94 assert(sec_state_is_valid(type)); 95 next_image_info = (type == NON_SECURE) 96 ? &bl33_image_ep_info : &bl32_image_ep_info; 97 /* 98 * None of the images on the ARM development platforms can have 0x0 99 * as the entrypoint 100 */ 101 if (next_image_info->pc) 102 return next_image_info; 103 else 104 return NULL; 105 } 106 107 /******************************************************************************* 108 * Perform any BL3-1 early platform setup common to ARM standard platforms. 109 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 110 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 111 * done before the MMU is initialized so that the memory layout can be used 112 * while creating page tables. BL2 has flushed this information to memory, so 113 * we are guaranteed to pick up good data. 114 ******************************************************************************/ 115 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, 116 void *plat_params_from_bl2) 117 { 118 /* Initialize the console to provide early debug support */ 119 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 120 ARM_CONSOLE_BAUDRATE); 121 122 #if RESET_TO_BL31 123 /* There are no parameters from BL2 if BL3-1 is a reset vector */ 124 assert(from_bl2 == NULL); 125 assert(plat_params_from_bl2 == NULL); 126 127 /* Populate entry point information for BL3-2 and BL3-3 */ 128 SET_PARAM_HEAD(&bl32_image_ep_info, 129 PARAM_EP, 130 VERSION_1, 131 0); 132 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 133 bl32_image_ep_info.pc = BL32_BASE; 134 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 135 136 SET_PARAM_HEAD(&bl33_image_ep_info, 137 PARAM_EP, 138 VERSION_1, 139 0); 140 /* 141 * Tell BL3-1 where the non-trusted software image 142 * is located and the entry state information 143 */ 144 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 145 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 146 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 147 148 #else 149 /* 150 * Check params passed from BL2 should not be NULL, 151 */ 152 assert(from_bl2 != NULL); 153 assert(from_bl2->h.type == PARAM_BL31); 154 assert(from_bl2->h.version >= VERSION_1); 155 /* 156 * In debug builds, we pass a special value in 'plat_params_from_bl2' 157 * to verify platform parameters from BL2 to BL3-1. 158 * In release builds, it's not used. 159 */ 160 assert(((unsigned long long)plat_params_from_bl2) == 161 ARM_BL31_PLAT_PARAM_VAL); 162 163 /* 164 * Copy BL3-2 and BL3-3 entry point information. 165 * They are stored in Secure RAM, in BL2's address space. 166 */ 167 bl32_image_ep_info = *from_bl2->bl32_ep_info; 168 bl33_image_ep_info = *from_bl2->bl33_ep_info; 169 #endif 170 } 171 172 void bl31_early_platform_setup(bl31_params_t *from_bl2, 173 void *plat_params_from_bl2) 174 { 175 arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); 176 177 /* 178 * Initialize CCI for this cluster during cold boot. 179 * No need for locks as no other CPU is active. 180 */ 181 arm_cci_init(); 182 183 /* 184 * Enable CCI coherency for the primary CPU's cluster. 185 * Earlier bootloader stages might already do this (e.g. Trusted 186 * Firmware's BL1 does it) but we can't assume so. There is no harm in 187 * executing this code twice anyway. 188 * Platform specific PSCI code will enable coherency for other 189 * clusters. 190 */ 191 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 192 } 193 194 /******************************************************************************* 195 * Perform any BL3-1 platform setup common to ARM standard platforms 196 ******************************************************************************/ 197 void arm_bl31_platform_setup(void) 198 { 199 unsigned int reg_val; 200 201 /* Initialize the gic cpu and distributor interfaces */ 202 plat_arm_gic_init(); 203 arm_gic_setup(); 204 205 #if RESET_TO_BL31 206 /* 207 * Do initial security configuration to allow DRAM/device access 208 * (if earlier BL has not already done so). 209 */ 210 plat_arm_security_setup(); 211 212 #endif /* RESET_TO_BL31 */ 213 214 /* Enable and initialize the System level generic timer */ 215 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 216 CNTCR_FCREQ(0) | CNTCR_EN); 217 218 /* Allow access to the System counter timer module */ 219 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 220 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 221 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 222 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); 223 224 reg_val = (1 << CNTNSAR_NS_SHIFT(1)); 225 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 226 227 /* Initialize power controller before setting up topology */ 228 plat_arm_pwrc_setup(); 229 } 230 231 void bl31_platform_setup(void) 232 { 233 arm_bl31_platform_setup(); 234 } 235 236 /******************************************************************************* 237 * Perform the very early platform specific architectural setup here. At the 238 * moment this is only intializes the mmu in a quick and dirty way. 239 ******************************************************************************/ 240 void arm_bl31_plat_arch_setup(void) 241 { 242 arm_configure_mmu_el3(BL31_RO_BASE, 243 (BL31_END - BL31_RO_BASE), 244 BL31_RO_BASE, 245 BL31_RO_LIMIT 246 #if USE_COHERENT_MEM 247 , BL31_COHERENT_RAM_BASE, 248 BL31_COHERENT_RAM_LIMIT 249 #endif 250 ); 251 } 252 253 void bl31_plat_arch_setup(void) 254 { 255 arm_bl31_plat_arch_setup(); 256 } 257 258 uint64_t plat_get_syscnt_freq(void) 259 { 260 uint64_t counter_base_frequency; 261 262 /* Read the frequency from Frequency modes table */ 263 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 264 265 /* The first entry of the frequency modes table must not be 0 */ 266 if (counter_base_frequency == 0) 267 panic(); 268 269 return counter_base_frequency; 270 } 271