1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <arm_config.h> 33 #include <arm_gic.h> 34 #include <assert.h> 35 #include <debug.h> 36 #include <errno.h> 37 #include <mmio.h> 38 #include <platform.h> 39 #include <plat_arm.h> 40 #include <psci.h> 41 #include <v2m_def.h> 42 #include "drivers/pwrc/fvp_pwrc.h" 43 #include "fvp_def.h" 44 #include "fvp_private.h" 45 46 unsigned long wakeup_address; 47 48 typedef volatile struct mailbox { 49 unsigned long value __aligned(CACHE_WRITEBACK_GRANULE); 50 } mailbox_t; 51 52 /******************************************************************************* 53 * Private FVP function to program the mailbox for a cpu before it is released 54 * from reset. 55 ******************************************************************************/ 56 static void fvp_program_mailbox(uint64_t mpidr, uint64_t address) 57 { 58 uint64_t linear_id; 59 mailbox_t *fvp_mboxes; 60 61 linear_id = plat_arm_calc_core_pos(mpidr); 62 fvp_mboxes = (mailbox_t *)MBOX_BASE; 63 fvp_mboxes[linear_id].value = address; 64 flush_dcache_range((unsigned long) &fvp_mboxes[linear_id], 65 sizeof(unsigned long)); 66 } 67 68 /******************************************************************************* 69 * Function which implements the common FVP specific operations to power down a 70 * cpu in response to a CPU_OFF or CPU_SUSPEND request. 71 ******************************************************************************/ 72 static void fvp_cpu_pwrdwn_common(void) 73 { 74 /* Prevent interrupts from spuriously waking up this cpu */ 75 arm_gic_cpuif_deactivate(); 76 77 /* Program the power controller to power off this cpu. */ 78 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 79 } 80 81 /******************************************************************************* 82 * Function which implements the common FVP specific operations to power down a 83 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 84 ******************************************************************************/ 85 static void fvp_cluster_pwrdwn_common(void) 86 { 87 uint64_t mpidr = read_mpidr_el1(); 88 89 /* Disable coherency if this cluster is to be turned off */ 90 fvp_cci_disable(); 91 92 /* Program the power controller to turn the cluster off */ 93 fvp_pwrc_write_pcoffr(mpidr); 94 } 95 96 /******************************************************************************* 97 * FVP handler called when a CPU is about to enter standby. 98 ******************************************************************************/ 99 void fvp_cpu_standby(plat_local_state_t cpu_state) 100 { 101 102 assert(cpu_state == ARM_LOCAL_STATE_RET); 103 104 /* 105 * Enter standby state 106 * dsb is good practice before using wfi to enter low power states 107 */ 108 dsb(); 109 wfi(); 110 } 111 112 /******************************************************************************* 113 * FVP handler called when a power domain is about to be turned on. The 114 * mpidr determines the CPU to be turned on. 115 ******************************************************************************/ 116 int fvp_pwr_domain_on(u_register_t mpidr) 117 { 118 int rc = PSCI_E_SUCCESS; 119 unsigned int psysr; 120 121 /* 122 * Ensure that we do not cancel an inflight power off request 123 * for the target cpu. That would leave it in a zombie wfi. 124 * Wait for it to power off, program the jump address for the 125 * target cpu and then program the power controller to turn 126 * that cpu on 127 */ 128 do { 129 psysr = fvp_pwrc_read_psysr(mpidr); 130 } while (psysr & PSYSR_AFF_L0); 131 132 fvp_program_mailbox(mpidr, wakeup_address); 133 fvp_pwrc_write_pponr(mpidr); 134 135 return rc; 136 } 137 138 /******************************************************************************* 139 * FVP handler called when a power domain is about to be turned off. The 140 * target_state encodes the power state that each level should transition to. 141 ******************************************************************************/ 142 void fvp_pwr_domain_off(const psci_power_state_t *target_state) 143 { 144 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 145 ARM_LOCAL_STATE_OFF); 146 147 /* 148 * If execution reaches this stage then this power domain will be 149 * suspended. Perform at least the cpu specific actions followed 150 * by the cluster specific operations if applicable. 151 */ 152 fvp_cpu_pwrdwn_common(); 153 154 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 155 ARM_LOCAL_STATE_OFF) 156 fvp_cluster_pwrdwn_common(); 157 158 } 159 160 /******************************************************************************* 161 * FVP handler called when a power domain is about to be suspended. The 162 * target_state encodes the power state that each level should transition to. 163 ******************************************************************************/ 164 void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 165 { 166 unsigned long mpidr; 167 168 /* 169 * FVP has retention only at cpu level. Just return 170 * as nothing is to be done for retention. 171 */ 172 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 173 ARM_LOCAL_STATE_RET) 174 return; 175 176 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 177 ARM_LOCAL_STATE_OFF); 178 179 /* Get the mpidr for this cpu */ 180 mpidr = read_mpidr_el1(); 181 182 /* Program the jump address for the this cpu */ 183 fvp_program_mailbox(mpidr, wakeup_address); 184 185 /* Program the power controller to enable wakeup interrupts. */ 186 fvp_pwrc_set_wen(mpidr); 187 188 /* Perform the common cpu specific operations */ 189 fvp_cpu_pwrdwn_common(); 190 191 /* Perform the common cluster specific operations */ 192 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 193 ARM_LOCAL_STATE_OFF) 194 fvp_cluster_pwrdwn_common(); 195 } 196 197 /******************************************************************************* 198 * FVP handler called when a power domain has just been powered on after 199 * being turned off earlier. The target_state encodes the low power state that 200 * each level has woken up from. 201 ******************************************************************************/ 202 void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 203 { 204 unsigned long mpidr; 205 206 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 207 ARM_LOCAL_STATE_OFF); 208 209 /* Get the mpidr for this cpu */ 210 mpidr = read_mpidr_el1(); 211 212 /* Perform the common cluster specific operations */ 213 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 214 ARM_LOCAL_STATE_OFF) { 215 /* 216 * This CPU might have woken up whilst the cluster was 217 * attempting to power down. In this case the FVP power 218 * controller will have a pending cluster power off request 219 * which needs to be cleared by writing to the PPONR register. 220 * This prevents the power controller from interpreting a 221 * subsequent entry of this cpu into a simple wfi as a power 222 * down request. 223 */ 224 fvp_pwrc_write_pponr(mpidr); 225 226 /* Enable coherency if this cluster was off */ 227 fvp_cci_enable(); 228 } 229 230 /* 231 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 232 * with a cpu power down unless the bit is set again 233 */ 234 fvp_pwrc_clr_wen(mpidr); 235 236 /* Zero the jump address in the mailbox for this cpu */ 237 fvp_program_mailbox(mpidr, 0); 238 239 /* Enable the gic cpu interface */ 240 arm_gic_cpuif_setup(); 241 242 /* TODO: This setup is needed only after a cold boot */ 243 arm_gic_pcpu_distif_setup(); 244 } 245 246 /******************************************************************************* 247 * FVP handler called when a power domain has just been powered on after 248 * having been suspended earlier. The target_state encodes the low power state 249 * that each level has woken up from. 250 * TODO: At the moment we reuse the on finisher and reinitialize the secure 251 * context. Need to implement a separate suspend finisher. 252 ******************************************************************************/ 253 void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 254 { 255 /* 256 * Nothing to be done on waking up from retention from CPU level. 257 */ 258 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 259 ARM_LOCAL_STATE_RET) 260 return; 261 262 fvp_pwr_domain_on_finish(target_state); 263 } 264 265 /******************************************************************************* 266 * FVP handlers to shutdown/reboot the system 267 ******************************************************************************/ 268 static void __dead2 fvp_system_off(void) 269 { 270 /* Write the System Configuration Control Register */ 271 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 272 V2M_CFGCTRL_START | 273 V2M_CFGCTRL_RW | 274 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 275 wfi(); 276 ERROR("FVP System Off: operation not handled.\n"); 277 panic(); 278 } 279 280 static void __dead2 fvp_system_reset(void) 281 { 282 /* Write the System Configuration Control Register */ 283 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 284 V2M_CFGCTRL_START | 285 V2M_CFGCTRL_RW | 286 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 287 wfi(); 288 ERROR("FVP System Reset: operation not handled.\n"); 289 panic(); 290 } 291 292 /******************************************************************************* 293 * Export the platform handlers to enable psci to invoke them 294 ******************************************************************************/ 295 static const plat_psci_ops_t fvp_plat_psci_ops = { 296 .cpu_standby = fvp_cpu_standby, 297 .pwr_domain_on = fvp_pwr_domain_on, 298 .pwr_domain_off = fvp_pwr_domain_off, 299 .pwr_domain_suspend = fvp_pwr_domain_suspend, 300 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 301 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 302 .system_off = fvp_system_off, 303 .system_reset = fvp_system_reset, 304 .validate_power_state = arm_validate_power_state 305 }; 306 307 /******************************************************************************* 308 * Export the platform specific psci ops & initialize the fvp power controller 309 ******************************************************************************/ 310 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 311 const plat_psci_ops_t **psci_ops) 312 { 313 *psci_ops = &fvp_plat_psci_ops; 314 wakeup_address = sec_entrypoint; 315 316 flush_dcache_range((unsigned long)&wakeup_address, 317 sizeof(wakeup_address)); 318 return 0; 319 } 320