Tegra186: mce: use udelay() to calculate timeouts

This patch modifies the timeout loop to use udelay() instead of
mdelay(). This helps with the boot time on some platforms which
issue a lot of MCE c

Tegra186: mce: use udelay() to calculate timeouts

This patch modifies the timeout loop to use udelay() instead of
mdelay(). This helps with the boot time on some platforms which
issue a lot of MCE calls and every mdelay adds up increasing the
boot time by a lot.

Change-Id: Ic50081b73e1cbc2714361235b5c396e294b8f752
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: fix MISRA Rule 8.3 violation

MISRA Rule 8.3, All declarations of an object or function
shall use the same names and type qualifiers.

This patch removes unused function(s).

Change-Id: I90

Tegra186: fix MISRA Rule 8.3 violation

MISRA Rule 8.3, All declarations of an object or function
shall use the same names and type qualifiers.

This patch removes unused function(s).

Change-Id: I90865c003d46f1dc08bfb5f4fe8a327ea42a2bb7
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Helper function to read ID_AFR0_EL1 system register

This patch provides helper function to read the ID_AFR0_EL1
system register for platforms.

Change-Id: Id5491b18e3bf9f619d98d6cc8efd9d2cf5918c9d
S

Helper function to read ID_AFR0_EL1 system register

This patch provides helper function to read the ID_AFR0_EL1
system register for platforms.

Change-Id: Id5491b18e3bf9f619d98d6cc8efd9d2cf5918c9d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: platform handlers to program MSS

Introduce platform handlers to program the MSS settings.
This allows the current driver to scale to future chips.

Change-Id: I40a27648a1a3c73b1ce

Tegra: memctrl_v2: platform handlers to program MSS

Introduce platform handlers to program the MSS settings.
This allows the current driver to scale to future chips.

Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

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plat/arm: Save BL2 descriptors to reserved memory.

On ARM platforms, the BL2 memory can be overlaid by BL31/BL32. The memory
descriptors describing the list of executable images are created in BL2
R

plat/arm: Save BL2 descriptors to reserved memory.

On ARM platforms, the BL2 memory can be overlaid by BL31/BL32. The memory
descriptors describing the list of executable images are created in BL2
R/W memory, which could be possibly corrupted later on by BL31/BL32 due
to overlay. This patch creates a reserved location in SRAM for these
descriptors and are copied over by BL2 before handing over to next BL
image.

Also this patch increases the PLAT_ARM_MAX_BL2_SIZE for juno when TBBR
is enabled.

Fixes ARM-Software/tf-issues#626

Change-Id: I755735706fa702024b4032f51ed4895b3687377f
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

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Merge pull request #1768 from bryanodonoghue/integration+linaro_warp7-tbb

Integration+linaro warp7 tbb

ti: k3: common: Add support for runtime detection of GICR base address

Valid addresses for GICR base are always a set calculable distance from
the GICD and is based on the number of cores a given in

ti: k3: common: Add support for runtime detection of GICR base address

Valid addresses for GICR base are always a set calculable distance from
the GICD and is based on the number of cores a given instance of GICv3 IP
can support. The formula for the number of address bits is given by the
ARM GIC-500 TRM section 3.2 as 2^(18+log2(cores)) with the MSB set to
one for GICR instances. Holes in the GIC address space are also
guaranteed to safely return 0 on reads. This allows us to support runtime
detection of the GICR base address by starting from GIC base address plus
BIT(18) and walking until the GICR ID register (IIDR) is detected. We
stop searching after BIT(20) to prevent searching out into space if
something goes wrong. This can be extended out if we ever have a device
with 16 or more cores.

Signed-off-by: Andrew F. Davis <afd@ti.com>

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Merge pull request #1772 from glneo/clear-proxy-queue

TI K3 Clear proxy receive queue on transmit

Merge pull request #1775 from glneo/uart-baud-rate

ti: k3: common: Allow customizing UART baud rate using build options

Merge pull request #1774 from glneo/error-message

ti: k3: drivers: sec_proxy: Switch error messages

Merge pull request #1771 from glneo/core-shutdown

TI K3 Core shutdown changes

Merge pull request #1770 from antonio-nino-diaz-arm/an/spm-mm

Undeprecate MM-based SPM

SPM: Rename folder of SPM based on MM

This implementation is no longer deprecated.

Change-Id: I68552d0fd5ba9f08fad4345e4657e8e3c5362a36
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

SPM: Rename SPM_DEPRECATED flag to SPM_MM

The SPM implementation based on MM is going to be kept for the
foreseeable future.

Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954
Signed-off-by: Anto

SPM: Rename SPM_DEPRECATED flag to SPM_MM

The SPM implementation based on MM is going to be kept for the
foreseeable future.

Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>

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ti: k3: common: Allow customizing UART baud rate using build options

To accommodate scenarios where we want to use a UART baud rate other than
the default 115,200 allow the associated compiler defin

ti: k3: common: Allow customizing UART baud rate using build options

To accommodate scenarios where we want to use a UART baud rate other than
the default 115,200 allow the associated compiler definition to be set
via the K3_USART_BAUD build option by updating the platform make file.

Since the platform make file now also contains the default value (still
115,200), go ahead and remove the redundant definition from the platform
header file.

Suggested-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>

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ti: k3: drivers: ti_sci: Clear receive queue before transmitting

Send and receive currently must be be serialized, any message already in
the receive queue when a new message is to be sent will caus

ti: k3: drivers: ti_sci: Clear receive queue before transmitting

Send and receive currently must be be serialized, any message already in
the receive queue when a new message is to be sent will cause a mismatch
with the expected response from this new message. Clear out all messages
from the response queue before sending a new request.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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ti: k3: drivers: sec_proxy: Allow clearing a Secure Proxy receive thread

It can be needed to discard all messages in a receive queue. This
can be used during some error recovery situations.

Signed-

ti: k3: drivers: sec_proxy: Allow clearing a Secure Proxy receive thread

It can be needed to discard all messages in a receive queue. This
can be used during some error recovery situations.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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ti: k3: common: Use shutdown API for PSCI core poweroff

To ensure WFI is reached before the PSC is trigger to power-down
a processor, the shutdonw API must be used.

Signed-off-by: Andrew F. Davis <

ti: k3: common: Use shutdown API for PSCI core poweroff

To ensure WFI is reached before the PSC is trigger to power-down
a processor, the shutdonw API must be used.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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ti: k3: drivers: ti_sci: Add processor shutdown API

This is a pseudo-API command consisting of a wait processor status
command and a set device state command queued back-to-back without
waiting for

ti: k3: drivers: ti_sci: Add processor shutdown API

This is a pseudo-API command consisting of a wait processor status
command and a set device state command queued back-to-back without
waiting for the System Firmware to ACK either message.

This is needed as the K3 power down specification states the System
Firmware must wait for a processor to be in WFI/WFE before powering
it down. The current implementation of System Firmware does not provide
such a command. Also given that with PSCI the core to be shutdown is the
core that is processing the shutdown request, the core cannot itself wait
for its own WFI/WFE status. To workaround this limitation, we submit
a wait processor status command followed by the actual shutdown command.
The shutdown command will not be processed until the wait command has
finished. In this way we can continue to WFI before the wait command
status has been met or timed-out and the shutdown command is processed.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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ti: k3: drivers: ti_sci: Add processor status wait API

This TI-SCI API can be used wait for a set of processor status flags to
be set or cleared. The flags are processor type specific. This command

ti: k3: drivers: ti_sci: Add processor status wait API

This TI-SCI API can be used wait for a set of processor status flags to
be set or cleared. The flags are processor type specific. This command
will not return ACK until the specified status is met. NACK will be
returned after the timeout elapses or on error.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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ti: k3: drivers: sec_proxy: Switch error messages

The logic is correct here, but the error messages are
reversed, switch them.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <

ti: k3: drivers: sec_proxy: Switch error messages

The logic is correct here, but the error messages are
reversed, switch them.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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Remove reference to DISABLE_PEDANTIC

This flag was removed in 79eb1aff7850 ("Remove `DISABLE_PEDANTIC` build
option").

Change-Id: Ic3584a4c5f0100ed9e57b068ec672b0baae8cfab
Signed-off-by: Antonio Ni

Remove reference to DISABLE_PEDANTIC

This flag was removed in 79eb1aff7850 ("Remove `DISABLE_PEDANTIC` build
option").

Change-Id: Ic3584a4c5f0100ed9e57b068ec672b0baae8cfab
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1764 from vwadekar/tf2.0-tegra-downstream-rebase-1.7.19

Tf2.0 tegra downstream rebase 1.7.19

Merge pull request #1767 from Yann-lms/updates_stm32mp1

Updates for STM32MP1

Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is re

Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is required as we observed that the MC's
arbitration bit is set before exiting the secure world.

Change-Id: Iacd01994d03b3b9cbd7b8a57fe7ab5b04e607a9f
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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