Probe for GICv3 re-distributors on core bring-up

The GICv3 distributor can have more ports than CPUs are available in
the system. Probe all re-distributors and use the matching affinity
levels as sp

Probe for GICv3 re-distributors on core bring-up

The GICv3 distributor can have more ports than CPUs are available in
the system. Probe all re-distributors and use the matching affinity
levels as specified by each core and re-distributor to decide which
re-distributor to use with which CPU core.

If a core cannot be matched with a re-distributor, the core panics and
is placed in an endless loop.

Change-Id: Ie393cfe07c7449a2383959e3c968664882e18afc

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Update year in copyright text to 2014

Change-Id: Ic7fb61aabae1d515b9e6baf3dd003807ff42da60

Move GIC setup to a separate file

GIC setup code which used to be in bl31_plat_setup.c is now in fvp_gic.c
to simplify future changes to other bootloader stages. This patch moves
code from bl31_pla

Move GIC setup to a separate file

GIC setup code which used to be in bl31_plat_setup.c is now in fvp_gic.c
to simplify future changes to other bootloader stages. This patch moves
code from bl31_plat_setup.c to fvp_gic.c, simplifies the include file
list for bl31_plat_setup.c, moves GIC declarations from the bl31.h header
file into the platform.h, and reworks files according to coding style
guide.

Change-Id: I48d82a4ba33e7114dcc88f9ca98767a06cf8f417

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Make BL31's ns_entry_info a single-cpu area

ns_entry_info used to be a per-cpu array. This is a waste of space
because it is only accessed by the primary CPU on the cold boot path.
This patch reduc

Make BL31's ns_entry_info a single-cpu area

ns_entry_info used to be a per-cpu array. This is a waste of space
because it is only accessed by the primary CPU on the cold boot path.
This patch reduces ns_entry_info to a single-cpu area.

Change-Id: I647c70c4e76069560f1aaad37a1d5910f56fba4c

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Remove useless copies of meminfo structures

Platform setup code has to reserve some memory for storing the
memory layout information. It is populated in early platform setup
code.

blx_get_sec_mem_

Remove useless copies of meminfo structures

Platform setup code has to reserve some memory for storing the
memory layout information. It is populated in early platform setup
code.

blx_get_sec_mem_layout() functions used to return a copy of this
structure. This patch modifies blx_get_sec_mem_layout() functions
so that they now directly return a pointer to their memory layout
structure. It ensures that the memory layout returned by
blx_get_sec_mem_layout() is always up-to-date and also avoids a
useless copy of the meminfo structure.

Also rename blx_get_sec_mem_layout() to blx_plat_sec_mem_layout()
to make it clear those functions are platform specific.

Change-Id: Ic7a6f9d6b6236b14865ab48a9f5eff545ce56551

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remove check on non-secure entrypoint parameter

In fvp_affinst_on/suspend, the non-secure entrypoint is always
expected to lie in the DRAM. This check will not be valid if
non-secure code executes d

remove check on non-secure entrypoint parameter

In fvp_affinst_on/suspend, the non-secure entrypoint is always
expected to lie in the DRAM. This check will not be valid if
non-secure code executes directly out of flash e.g. a baremetal
test. This patch removes this check.

Change-Id: I0436e1138fc394aae8ff1ea59ebe38b46a440b61

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psci: fix error due to a non zero context id

In the previous psci implementation, the psci_afflvl_power_on_finish()
function would run into an error condition if the value of the context
id paramete

psci: fix error due to a non zero context id

In the previous psci implementation, the psci_afflvl_power_on_finish()
function would run into an error condition if the value of the context
id parameter in the cpu_on and cpu_suspend psci calls was != 0. The
parameter was being restored as the return value of the affinity level
0 finisher function. A non zero context id would be treated as an
error condition. This would prevent successful wake up of the cpu from
a power down state. Also, the contents of the general purpose
registers were not being cleared upon return to the non-secure world
after a cpu power up. This could potentially allow the non-secure
world to view secure data.

This patch ensures that all general purpose registers are set to ~0
prior to the final eret that drops the execution to the non-secure
world. The context id is used to initialize the general purpose
register x0 prior to re-entry into the non-secure world and is no
longer restored as a function return value. A platform helper
(platform_get_stack()) has been introduced to facilitate this change.

Change-Id: I2454911ffd75705d6aa8609a5d250d9b26fa097c

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clear wakeup enable bit upon resuming from suspend

The FVP specific code that gets called after a cpu has been physically
powered on after having been turned off or suspended earlier does not
clear

clear wakeup enable bit upon resuming from suspend

The FVP specific code that gets called after a cpu has been physically
powered on after having been turned off or suspended earlier does not
clear the PWRC.PWKUPR.WEN bit. Not doing so causes problems if: a cpu
is suspended, woken from suspend, powered down through a cpu_off call
& receives a spurious interrupt. Since the WEN bit is not cleared
after the cpu woke up from suspend, the spurious wakeup will power the
cpu on. Since the cpu_off call clears the jump address in the mailbox
this spurious wakeup will cause the cpu to crash.

This patch fixes this issue by clearing the WEN bit whenever a cpu is
powered up.

Change-Id: Ic91f5dffe1ed01d76bc7fc807acf0ecd3e38ce5b

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Enable third party contributions

- Add instructions for contributing to ARM Trusted Firmware.

- Update copyright text in all files to acknowledge contributors.

Change-Id: I9311aac81b00c6c167d2f8c8

Enable third party contributions

- Add instructions for contributing to ARM Trusted Firmware.

- Update copyright text in all files to acknowledge contributors.

Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5

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Properly initialise the C runtime environment

This patch makes sure the C runtime environment is properly
initialised before executing any C code.

- Zero-initialise NOBITS sections (e.g. the bss

Properly initialise the C runtime environment

This patch makes sure the C runtime environment is properly
initialised before executing any C code.

- Zero-initialise NOBITS sections (e.g. the bss section).
- Relocate BL1 data from ROM to RAM.

Change-Id: I0da81b417b2f0d1f7ef667cc5131b1e47e22571f

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Various improvements/cleanups on the linker scripts

- Check at link-time that bootloader images will fit in memory
at run time and that they won't overlap each other.
- Remove text and rodat

Various improvements/cleanups on the linker scripts

- Check at link-time that bootloader images will fit in memory
at run time and that they won't overlap each other.
- Remove text and rodata orphan sections.
- Define new linker symbols to remove the need for platform setup
code to know the order of sections.
- Reduce the size of the raw binary images by cutting some sections
out of the disk image and allocating them at load time, whenever
possible.
- Rework alignment constraints on sections.
- Remove unused linker symbols.
- Homogenize linker symbols names across all BLs.
- Add some comments in the linker scripts.

Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9

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fvp: Remove call to bl2_get_ns_mem_layout() function

On FVP platforms, for now it is assumed that the normal-world
bootloader is already sitting in its final memory location.
Therefore, BL2 doesn't

fvp: Remove call to bl2_get_ns_mem_layout() function

On FVP platforms, for now it is assumed that the normal-world
bootloader is already sitting in its final memory location.
Therefore, BL2 doesn't need to load it and so it doesn't need
to know the extents of the non-trusted DRAM.

Change-Id: I33177ab43ca242edc8958f2fa8d994e7cf3e0843

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AArch64: Remove EL-agnostic TLB helper functions

Also, don't invalidate the TLBs in disable_mmu() function, it's better
to do it in enable_mmu() function just before actually enabling the
MMU.

Chan

AArch64: Remove EL-agnostic TLB helper functions

Also, don't invalidate the TLBs in disable_mmu() function, it's better
to do it in enable_mmu() function just before actually enabling the
MMU.

Change-Id: Ib32d6660019b0b2c17254156aad4be67ab4970e1

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fvp: Remove unnecessary initializers

Global and static variables are expected to be initialised to zero
by default. This is specified by the C99 standard. This patch
removes some unnecessary initia

fvp: Remove unnecessary initializers

Global and static variables are expected to be initialised to zero
by default. This is specified by the C99 standard. This patch
removes some unnecessary initialisations of such variables.

It fixes a compilation warning at the same time:
plat/fvp/bl31_plat_setup.c:82:3: warning: missing braces around
initializer [-Wmissing-braces]
section("tzfw_coherent_mem"))) = {0};
^
plat/fvp/bl31_plat_setup.c:82:3: warning: (near initialization for
‘ns_entry_info[0]’) [-Wmissing-braces]

Note that GCC should not have emitted this warning message in the
first place. The C Standard permits braces to be elided around
subaggregate initializers. See this GCC bug report:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119

Change-Id: I13cb0c344feb9803bca8819f976377741fa6bc35

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Move generic architectural setup out of blx_plat_arch_setup().

blx_plat_arch_setup() should only perform platform-specific
architectural setup, e.g. enabling the MMU. This patch moves
generic archi

Move generic architectural setup out of blx_plat_arch_setup().

blx_plat_arch_setup() should only perform platform-specific
architectural setup, e.g. enabling the MMU. This patch moves
generic architectural setup code out of blx_plat_arch_setup().

Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6

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Do not enable CCI on Foundation FVP

- The Foundation FVP only has one cluster and does not have
CCI.

Change-Id: If91e81ff72c52e448150089c4cfea3e4d6ae1232

Writing to the FVP LED register should be a 32bit access.

- Writing to this register with a 64bit access can cause a
Systen Error Exception on some models.

Change-Id: Ibcf5bdf7ab55707db61c16298f2

Writing to the FVP LED register should be a 32bit access.

- Writing to this register with a 64bit access can cause a
Systen Error Exception on some models.

Change-Id: Ibcf5bdf7ab55707db61c16298f25caff50e1ff7e

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ARMv8 Trusted Firmware release v0.2