xref: /rk3399_ARM-atf/bl31/aarch64/runtime_exceptions.S (revision a43d431b80541ea436b71f967c5749babf978c7a) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <cm_macros.S>
34#include <context.h>
35#include <platform.h>
36#include <runtime_svc.h>
37
38	.globl	runtime_exceptions
39	.globl	el3_exit
40
41	.macro save_x18_to_x29_sp_el0
42	stp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
43	stp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
44	stp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
45	stp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
46	stp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
47	stp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
48	mrs	x18, sp_el0
49	str	x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
50	.endm
51
52	.section	.vectors, "ax"; .align 11
53
54	.align	7
55runtime_exceptions:
56	/* -----------------------------------------------------
57	 * Current EL with _sp_el0 : 0x0 - 0x180
58	 * -----------------------------------------------------
59	 */
60sync_exception_sp_el0:
61	/* -----------------------------------------------------
62	 * We don't expect any synchronous exceptions from EL3
63	 * -----------------------------------------------------
64	 */
65	bl	dump_state_and_die
66	check_vector_size sync_exception_sp_el0
67
68	.align	7
69	/* -----------------------------------------------------
70	 * EL3 code is non-reentrant. Any asynchronous exception
71	 * is a serious error. Loop infinitely.
72	 * -----------------------------------------------------
73	 */
74irq_sp_el0:
75	bl	dump_intr_state_and_die
76	check_vector_size irq_sp_el0
77
78	.align	7
79fiq_sp_el0:
80	bl	dump_intr_state_and_die
81	check_vector_size fiq_sp_el0
82
83	.align	7
84serror_sp_el0:
85	bl	dump_state_and_die
86	check_vector_size serror_sp_el0
87
88	/* -----------------------------------------------------
89	 * Current EL with SPx: 0x200 - 0x380
90	 * -----------------------------------------------------
91	 */
92	.align	7
93sync_exception_sp_elx:
94	/* -----------------------------------------------------
95	 * This exception will trigger if anything went wrong
96	 * during a previous exception entry or exit or while
97	 * handling an earlier unexpected synchronous exception.
98	 * There is a high probability that SP_EL3 is corrupted.
99	 * -----------------------------------------------------
100	 */
101	bl	dump_state_and_die
102	check_vector_size sync_exception_sp_elx
103
104	.align	7
105irq_sp_elx:
106	bl	dump_intr_state_and_die
107	check_vector_size irq_sp_elx
108
109	.align	7
110fiq_sp_elx:
111	bl	dump_intr_state_and_die
112	check_vector_size fiq_sp_elx
113
114	.align	7
115serror_sp_elx:
116	bl	dump_state_and_die
117	check_vector_size serror_sp_elx
118
119	/* -----------------------------------------------------
120	 * Lower EL using AArch64 : 0x400 - 0x580
121	 * -----------------------------------------------------
122	 */
123	.align	7
124sync_exception_aarch64:
125	/* -----------------------------------------------------
126	 * This exception vector will be the entry point for
127	 * SMCs and traps that are unhandled at lower ELs most
128	 * commonly. SP_EL3 should point to a valid cpu context
129	 * where the general purpose and system register state
130	 * can be saved.
131	 * -----------------------------------------------------
132	 */
133	handle_sync_exception
134	check_vector_size sync_exception_aarch64
135
136	.align	7
137	/* -----------------------------------------------------
138	 * Asynchronous exceptions from lower ELs are not
139	 * currently supported. Report their occurrence.
140	 * -----------------------------------------------------
141	 */
142irq_aarch64:
143	bl	dump_intr_state_and_die
144	check_vector_size irq_aarch64
145
146	.align	7
147fiq_aarch64:
148	bl	dump_intr_state_and_die
149	check_vector_size fiq_aarch64
150
151	.align	7
152serror_aarch64:
153	bl	dump_state_and_die
154	check_vector_size serror_aarch64
155
156	/* -----------------------------------------------------
157	 * Lower EL using AArch32 : 0x600 - 0x780
158	 * -----------------------------------------------------
159	 */
160	.align	7
161sync_exception_aarch32:
162	/* -----------------------------------------------------
163	 * This exception vector will be the entry point for
164	 * SMCs and traps that are unhandled at lower ELs most
165	 * commonly. SP_EL3 should point to a valid cpu context
166	 * where the general purpose and system register state
167	 * can be saved.
168	 * -----------------------------------------------------
169	 */
170	handle_sync_exception
171	check_vector_size sync_exception_aarch32
172
173	.align	7
174	/* -----------------------------------------------------
175	 * Asynchronous exceptions from lower ELs are not
176	 * currently supported. Report their occurrence.
177	 * -----------------------------------------------------
178	 */
179irq_aarch32:
180	bl	dump_intr_state_and_die
181	check_vector_size irq_aarch32
182
183	.align	7
184fiq_aarch32:
185	bl	dump_intr_state_and_die
186	check_vector_size fiq_aarch32
187
188	.align	7
189serror_aarch32:
190	bl	dump_state_and_die
191	check_vector_size serror_aarch32
192
193	.align	7
194
195	/* -----------------------------------------------------
196	 * The following code handles secure monitor calls.
197	 * Depending upon the execution state from where the SMC
198	 * has been invoked, it frees some general purpose
199	 * registers to perform the remaining tasks. They
200	 * involve finding the runtime service handler that is
201	 * the target of the SMC & switching to runtime stacks
202	 * (SP_EL0) before calling the handler.
203	 *
204	 * Note that x30 has been explicitly saved and can be
205	 * used here
206	 * -----------------------------------------------------
207	 */
208func smc_handler
209smc_handler32:
210	/* Check whether aarch32 issued an SMC64 */
211	tbnz	x0, #FUNCID_CC_SHIFT, smc_prohibited
212
213	/* -----------------------------------------------------
214	 * Since we're are coming from aarch32, x8-x18 need to
215	 * be saved as per SMC32 calling convention. If a lower
216	 * EL in aarch64 is making an SMC32 call then it must
217	 * have saved x8-x17 already therein.
218	 * -----------------------------------------------------
219	 */
220	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
221	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
222	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
223	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
224	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
225
226	/* x4-x7, x18, sp_el0 are saved below */
227
228smc_handler64:
229	/* -----------------------------------------------------
230	 * Populate the parameters for the SMC handler. We
231	 * already have x0-x4 in place. x5 will point to a
232	 * cookie (not used now). x6 will point to the context
233	 * structure (SP_EL3) and x7 will contain flags we need
234	 * to pass to the handler Hence save x5-x7. Note that x4
235	 * only needs to be preserved for AArch32 callers but we
236	 * do it for AArch64 callers as well for convenience
237	 * -----------------------------------------------------
238	 */
239	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
240	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
241
242	/* Save rest of the gpregs and sp_el0*/
243	save_x18_to_x29_sp_el0
244
245	mov	x5, xzr
246	mov	x6, sp
247
248	/* Get the unique owning entity number */
249	ubfx	x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
250	ubfx	x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
251	orr	x16, x16, x15, lsl #FUNCID_OEN_WIDTH
252
253	adr	x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
254
255	/* Load descriptor index from array of indices */
256	adr	x14, rt_svc_descs_indices
257	ldrb	w15, [x14, x16]
258
259	/* -----------------------------------------------------
260	 * Restore the saved C runtime stack value which will
261	 * become the new SP_EL0 i.e. EL3 runtime stack. It was
262	 * saved in the 'cpu_context' structure prior to the last
263	 * ERET from EL3.
264	 * -----------------------------------------------------
265	 */
266	ldr	x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
267
268	/*
269	 * Any index greater than 127 is invalid. Check bit 7 for
270	 * a valid index
271	 */
272	tbnz	w15, 7, smc_unknown
273
274	/* Switch to SP_EL0 */
275	msr	spsel, #0
276
277	/* -----------------------------------------------------
278	 * Get the descriptor using the index
279	 * x11 = (base + off), x15 = index
280	 *
281	 * handler = (base + off) + (index << log2(size))
282	 * -----------------------------------------------------
283	 */
284	lsl	w10, w15, #RT_SVC_SIZE_LOG2
285	ldr	x15, [x11, w10, uxtw]
286
287	/* -----------------------------------------------------
288	 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
289	 * is a world switch during SMC handling.
290	 * TODO: Revisit if all system registers can be saved
291	 * later.
292	 * -----------------------------------------------------
293	 */
294	mrs	x16, spsr_el3
295	mrs	x17, elr_el3
296	mrs	x18, scr_el3
297	stp	x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
298	stp	x18, xzr, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
299
300	/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
301	bfi	x7, x18, #0, #1
302
303	mov	sp, x12
304
305	/* -----------------------------------------------------
306	 * Call the Secure Monitor Call handler and then drop
307	 * directly into el3_exit() which will program any
308	 * remaining architectural state prior to issuing the
309	 * ERET to the desired lower EL.
310	 * -----------------------------------------------------
311	 */
312#if DEBUG
313	cbz	x15, rt_svc_fw_critical_error
314#endif
315	blr	x15
316
317	/* -----------------------------------------------------
318	 * This routine assumes that the SP_EL3 is pointing to
319	 * a valid context structure from where the gp regs and
320	 * other special registers can be retrieved.
321	 *
322	 * Keep it in the same section as smc_handler as this
323	 * function uses a fall-through to el3_exit
324	 * -----------------------------------------------------
325	 */
326el3_exit: ; .type el3_exit, %function
327	/* -----------------------------------------------------
328	 * Save the current SP_EL0 i.e. the EL3 runtime stack
329	 * which will be used for handling the next SMC. Then
330	 * switch to SP_EL3
331	 * -----------------------------------------------------
332	 */
333	mov	x17, sp
334	msr	spsel, #1
335	str	x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
336
337	/* -----------------------------------------------------
338	 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
339	 * -----------------------------------------------------
340	 */
341	ldp	x18, xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
342	ldp	x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
343	msr	scr_el3, x18
344	msr	spsr_el3, x16
345	msr	elr_el3, x17
346
347	/* Restore saved general purpose registers and return */
348	b	restore_gp_registers_eret
349
350smc_unknown:
351	/*
352	 * Here we restore x4-x18 regardless of where we came from. AArch32
353	 * callers will find the registers contents unchanged, but AArch64
354	 * callers will find the registers modified (with stale earlier NS
355	 * content). Either way, we aren't leaking any secure information
356	 * through them
357	 */
358	mov	w0, #SMC_UNK
359	b	restore_gp_registers_callee_eret
360
361smc_prohibited:
362	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
363	mov	w0, #SMC_UNK
364	eret
365
366rt_svc_fw_critical_error:
367	msr	spsel, #1 /* Switch to SP_ELx */
368	bl	dump_state_and_die
369
370	/* -----------------------------------------------------
371	 * The following functions are used to saved and restore
372	 * all the general pupose registers. Ideally we would
373	 * only save and restore the callee saved registers when
374	 * a world switch occurs but that type of implementation
375	 * is more complex. So currently we will always save and
376	 * restore these registers on entry and exit of EL3.
377	 * These are not macros to ensure their invocation fits
378	 * within the 32 instructions per exception vector.
379	 * -----------------------------------------------------
380	 */
381func save_gp_registers
382	stp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
383	stp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
384	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
385	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
386	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
387	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
388	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
389	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
390	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
391	save_x18_to_x29_sp_el0
392	ret
393
394func restore_gp_registers_eret
395	ldp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
396	ldp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
397
398restore_gp_registers_callee_eret:
399	ldp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
400	ldp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
401	ldp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
402	ldp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
403	ldp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
404	ldp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
405	ldp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
406	ldp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
407	ldp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
408	ldp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
409	ldp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
410	ldp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
411	ldp	x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
412	msr	sp_el0, x17
413	ldp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
414	eret
415