1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <cm_macros.S> 35 36 37 .globl bl31_entrypoint 38 39 40 /* ----------------------------------------------------- 41 * bl31_entrypoint() is the cold boot entrypoint, 42 * executed only by the primary cpu. 43 * ----------------------------------------------------- 44 */ 45 46func bl31_entrypoint 47 /* --------------------------------------------- 48 * Preceding bootloader has populated x0 with a 49 * pointer to a 'bl31_args' structure & x1 50 * with any other optional information 51 * --------------------------------------------- 52 */ 53 mov x20, x0 54 mov x21, x1 55 56 /* --------------------------------------------- 57 * Set the exception vector to something sane. 58 * --------------------------------------------- 59 */ 60 adr x1, early_exceptions 61 msr vbar_el3, x1 62 63 /* --------------------------------------------------------------------- 64 * The initial state of the Architectural feature trap register 65 * (CPTR_EL3) is unknown and it must be set to a known state. All 66 * feature traps are disabled. Some bits in this register are marked as 67 * Reserved and should not be modified. 68 * 69 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 70 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 71 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 72 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 73 * access to trace functionality is not supported, this bit is RES0. 74 * CPTR_EL3.TFP: This causes instructions that access the registers 75 * associated with Floating Point and Advanced SIMD execution to trap 76 * to EL3 when executed from any exception level, unless trapped to EL1 77 * or EL2. 78 * --------------------------------------------------------------------- 79 */ 80 mrs x1, cptr_el3 81 bic w1, w1, #TCPAC_BIT 82 bic w1, w1, #TTA_BIT 83 bic w1, w1, #TFP_BIT 84 msr cptr_el3, x1 85 86 /* --------------------------------------------- 87 * Enable the instruction cache. 88 * --------------------------------------------- 89 */ 90 mrs x1, sctlr_el3 91 orr x1, x1, #SCTLR_I_BIT 92 msr sctlr_el3, x1 93 isb 94 95 /* --------------------------------------------- 96 * This is BL31 which is expected to be executed 97 * only by the primary cpu (at least for now). 98 * So, make sure no secondary has lost its way. 99 * --------------------------------------------- 100 */ 101 mrs x0, mpidr_el1 102 bl platform_is_primary_cpu 103 cbz x0, _panic 104 105 /* --------------------------------------------- 106 * Zero out NOBITS sections. There are 2 of them: 107 * - the .bss section; 108 * - the coherent memory section. 109 * --------------------------------------------- 110 */ 111 ldr x0, =__BSS_START__ 112 ldr x1, =__BSS_SIZE__ 113 bl zeromem16 114 115 ldr x0, =__COHERENT_RAM_START__ 116 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 117 bl zeromem16 118 119 /* --------------------------------------------- 120 * Use SP_EL0 for the C runtime stack. 121 * --------------------------------------------- 122 */ 123 msr spsel, #0 124 125 /* -------------------------------------------- 126 * Give ourselves a small coherent stack to 127 * ease the pain of initializing the MMU 128 * -------------------------------------------- 129 */ 130 mrs x0, mpidr_el1 131 bl platform_set_coherent_stack 132 133 /* --------------------------------------------- 134 * Perform platform specific early arch. setup 135 * --------------------------------------------- 136 */ 137 mov x0, x20 138 mov x1, x21 139 bl bl31_early_platform_setup 140 bl bl31_plat_arch_setup 141 142 /* --------------------------------------------- 143 * Give ourselves a stack allocated in Normal 144 * -IS-WBWA memory 145 * --------------------------------------------- 146 */ 147 mrs x0, mpidr_el1 148 bl platform_set_stack 149 150 /* --------------------------------------------- 151 * Jump to main function. 152 * --------------------------------------------- 153 */ 154 bl bl31_main 155 156 b el3_exit 157 158_panic: 159 wfi 160 b _panic 161