1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34 35 36 .globl tsp_entrypoint 37 .globl tsp_cpu_on_entry 38 .globl tsp_cpu_off_entry 39 .globl tsp_cpu_suspend_entry 40 .globl tsp_cpu_resume_entry 41 .globl tsp_fast_smc_entry 42 .globl tsp_fiq_entry 43 44 /* --------------------------------------------- 45 * Populate the params in x0-x7 from the pointer 46 * to the smc args structure in x0. 47 * --------------------------------------------- 48 */ 49 .macro restore_args_call_smc 50 ldp x6, x7, [x0, #TSP_ARG6] 51 ldp x4, x5, [x0, #TSP_ARG4] 52 ldp x2, x3, [x0, #TSP_ARG2] 53 ldp x0, x1, [x0, #TSP_ARG0] 54 smc #0 55 .endm 56 57 .macro save_eret_context reg1 reg2 58 mrs \reg1, elr_el1 59 mrs \reg2, spsr_el1 60 stp \reg1, \reg2, [sp, #-0x10]! 61 stp x30, x18, [sp, #-0x10]! 62 .endm 63 64 .macro restore_eret_context reg1 reg2 65 ldp x30, x18, [sp], #0x10 66 ldp \reg1, \reg2, [sp], #0x10 67 msr elr_el1, \reg1 68 msr spsr_el1, \reg2 69 .endm 70 71 .section .text, "ax" 72 .align 3 73 74func tsp_entrypoint 75 76 /* --------------------------------------------- 77 * The entrypoint is expected to be executed 78 * only by the primary cpu (at least for now). 79 * So, make sure no secondary has lost its way. 80 * --------------------------------------------- 81 */ 82 mrs x0, mpidr_el1 83 bl platform_is_primary_cpu 84 cbz x0, tsp_entrypoint_panic 85 86 /* --------------------------------------------- 87 * Set the exception vector to something sane. 88 * --------------------------------------------- 89 */ 90 adr x0, tsp_exceptions 91 msr vbar_el1, x0 92 93 /* --------------------------------------------- 94 * Enable the instruction cache. 95 * --------------------------------------------- 96 */ 97 mrs x0, sctlr_el1 98 orr x0, x0, #SCTLR_I_BIT 99 msr sctlr_el1, x0 100 isb 101 102 /* --------------------------------------------- 103 * Zero out NOBITS sections. There are 2 of them: 104 * - the .bss section; 105 * - the coherent memory section. 106 * --------------------------------------------- 107 */ 108 ldr x0, =__BSS_START__ 109 ldr x1, =__BSS_SIZE__ 110 bl zeromem16 111 112 ldr x0, =__COHERENT_RAM_START__ 113 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 114 bl zeromem16 115 116 /* -------------------------------------------- 117 * Give ourselves a small coherent stack to 118 * ease the pain of initializing the MMU 119 * -------------------------------------------- 120 */ 121 mrs x0, mpidr_el1 122 bl platform_set_coherent_stack 123 124 /* --------------------------------------------- 125 * Perform early platform setup & platform 126 * specific early arch. setup e.g. mmu setup 127 * --------------------------------------------- 128 */ 129 bl bl32_early_platform_setup 130 bl bl32_plat_arch_setup 131 132 /* --------------------------------------------- 133 * Give ourselves a stack allocated in Normal 134 * -IS-WBWA memory 135 * --------------------------------------------- 136 */ 137 mrs x0, mpidr_el1 138 bl platform_set_stack 139 140 /* --------------------------------------------- 141 * Jump to main function. 142 * --------------------------------------------- 143 */ 144 bl tsp_main 145 146 /* --------------------------------------------- 147 * Tell TSPD that we are done initialising 148 * --------------------------------------------- 149 */ 150 mov x1, x0 151 mov x0, #TSP_ENTRY_DONE 152 smc #0 153 154tsp_entrypoint_panic: 155 b tsp_entrypoint_panic 156 157 /*--------------------------------------------- 158 * This entrypoint is used by the TSPD when this 159 * cpu is to be turned off through a CPU_OFF 160 * psci call to ask the TSP to perform any 161 * bookeeping necessary. In the current 162 * implementation, the TSPD expects the TSP to 163 * re-initialise its state so nothing is done 164 * here except for acknowledging the request. 165 * --------------------------------------------- 166 */ 167func tsp_cpu_off_entry 168 bl tsp_cpu_off_main 169 restore_args_call_smc 170 171 /*--------------------------------------------- 172 * This entrypoint is used by the TSPD when this 173 * cpu is turned on using a CPU_ON psci call to 174 * ask the TSP to initialise itself i.e. setup 175 * the mmu, stacks etc. Minimal architectural 176 * state will be initialised by the TSPD when 177 * this function is entered i.e. Caches and MMU 178 * will be turned off, the execution state 179 * will be aarch64 and exceptions masked. 180 * --------------------------------------------- 181 */ 182func tsp_cpu_on_entry 183 /* --------------------------------------------- 184 * Set the exception vector to something sane. 185 * --------------------------------------------- 186 */ 187 adr x0, tsp_exceptions 188 msr vbar_el1, x0 189 190 /* --------------------------------------------- 191 * Enable the instruction cache. 192 * --------------------------------------------- 193 */ 194 mrs x0, sctlr_el1 195 orr x0, x0, #SCTLR_I_BIT 196 msr sctlr_el1, x0 197 isb 198 199 /* -------------------------------------------- 200 * Give ourselves a small coherent stack to 201 * ease the pain of initializing the MMU 202 * -------------------------------------------- 203 */ 204 mrs x0, mpidr_el1 205 bl platform_set_coherent_stack 206 207 /* --------------------------------------------- 208 * Initialise the MMU 209 * --------------------------------------------- 210 */ 211 bl enable_mmu_el1 212 213 /* --------------------------------------------- 214 * Give ourselves a stack allocated in Normal 215 * -IS-WBWA memory 216 * --------------------------------------------- 217 */ 218 mrs x0, mpidr_el1 219 bl platform_set_stack 220 221 /* --------------------------------------------- 222 * Enter C runtime to perform any remaining 223 * book keeping 224 * --------------------------------------------- 225 */ 226 bl tsp_cpu_on_main 227 restore_args_call_smc 228 229 /* Should never reach here */ 230tsp_cpu_on_entry_panic: 231 b tsp_cpu_on_entry_panic 232 233 /*--------------------------------------------- 234 * This entrypoint is used by the TSPD when this 235 * cpu is to be suspended through a CPU_SUSPEND 236 * psci call to ask the TSP to perform any 237 * bookeeping necessary. In the current 238 * implementation, the TSPD saves and restores 239 * the EL1 state. 240 * --------------------------------------------- 241 */ 242func tsp_cpu_suspend_entry 243 bl tsp_cpu_suspend_main 244 restore_args_call_smc 245 246 /*--------------------------------------------- 247 * This entrypoint is used by the TSPD to pass 248 * control for handling a pending S-EL1 FIQ. 249 * 'x0' contains a magic number which indicates 250 * this. TSPD expects control to be handed back 251 * at the end of FIQ processing. This is done 252 * through an SMC. The handover agreement is: 253 * 254 * 1. PSTATE.DAIF are set upon entry. 'x1' has 255 * the ELR_EL3 from the non-secure state. 256 * 2. TSP has to preserve the callee saved 257 * general purpose registers, SP_EL1/EL0 and 258 * LR. 259 * 3. TSP has to preserve the system and vfp 260 * registers (if applicable). 261 * 4. TSP can use 'x0-x18' to enable its C 262 * runtime. 263 * 5. TSP returns to TSPD using an SMC with 264 * 'x0' = TSP_HANDLED_S_EL1_FIQ 265 * --------------------------------------------- 266 */ 267func tsp_fiq_entry 268#if DEBUG 269 mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) 270 movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) 271 cmp x0, x2 272 b.ne tsp_fiq_entry_panic 273#endif 274 /*--------------------------------------------- 275 * Save any previous context needed to perform 276 * an exception return from S-EL1 e.g. context 277 * from a previous IRQ. Update statistics and 278 * handle the FIQ before returning to the TSPD. 279 * IRQ/FIQs are not enabled since that will 280 * complicate the implementation. Execution 281 * will be transferred back to the normal world 282 * in any case. A non-zero return value from the 283 * fiq handler is an error. 284 * --------------------------------------------- 285 */ 286 save_eret_context x2 x3 287 bl tsp_update_sync_fiq_stats 288 bl tsp_fiq_handler 289 cbnz x0, tsp_fiq_entry_panic 290 restore_eret_context x2 x3 291 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) 292 movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) 293 smc #0 294 295tsp_fiq_entry_panic: 296 b tsp_fiq_entry_panic 297 298 /*--------------------------------------------- 299 * This entrypoint is used by the TSPD when this 300 * cpu resumes execution after an earlier 301 * CPU_SUSPEND psci call to ask the TSP to 302 * restore its saved context. In the current 303 * implementation, the TSPD saves and restores 304 * EL1 state so nothing is done here apart from 305 * acknowledging the request. 306 * --------------------------------------------- 307 */ 308func tsp_cpu_resume_entry 309 bl tsp_cpu_resume_main 310 restore_args_call_smc 311tsp_cpu_resume_panic: 312 b tsp_cpu_resume_panic 313 314 /*--------------------------------------------- 315 * This entrypoint is used by the TSPD to ask 316 * the TSP to service a fast smc request. 317 * --------------------------------------------- 318 */ 319func tsp_fast_smc_entry 320 bl tsp_fast_smc_handler 321 restore_args_call_smc 322tsp_fast_smc_entry_panic: 323 b tsp_fast_smc_entry_panic 324 325