AArch32: Enable override of plat_set_my_stack/plat_get_my_stack

This patch makes the default MP definitions of plat_get_my_stack()
and plat_set_my_stack() as weak so that they can be overridden by
t

AArch32: Enable override of plat_set_my_stack/plat_get_my_stack

This patch makes the default MP definitions of plat_get_my_stack()
and plat_set_my_stack() as weak so that they can be overridden by
the AArch32 Secure Payload if it requires.

Change-Id: I3b6ddff5750443a776505e3023ff2934227592b6
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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rockchip: plat_pm.c: Change callbacks implement for our SOCs.

Remove struct rockchip_pm_ops_cb and instead of using weak functions
implement; in this way we want the codes look clear and simple;

Ch

rockchip: plat_pm.c: Change callbacks implement for our SOCs.

Remove struct rockchip_pm_ops_cb and instead of using weak functions
implement; in this way we want the codes look clear and simple;

Change-Id: Ib9e8a5e932fdfc2b3e6a1ec502c40dfe720ac400
Signed-off-by: tony.xie <tony.xie@rock-chips.com>

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Tegra: per-soc `get_target_pwr_state` handler

This patch implements a per-soc handler to calculate the target
power state for the cluster/system. A weak implementation of the
handler is provided for

Tegra: per-soc `get_target_pwr_state` handler

This patch implements a per-soc handler to calculate the target
power state for the cluster/system. A weak implementation of the
handler is provided for platforms to use by default.

For SoCs with multiple CPU clusters, this handler would provide
the individual cluster/system state, allowing the PSCI service to
flush caches during cluster/system power down.

Change-Id: I568cdb42204f9841a8430bd9105bd694f71cf91d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: relocate BL32 image to TZDRAM memory

This patch adds support to relocate the BL32 image from the NS
memory to TZDRAM during cold boot. The NS memory buffer is
cleared out after the process co

Tegra: relocate BL32 image to TZDRAM memory

This patch adds support to relocate the BL32 image from the NS
memory to TZDRAM during cold boot. The NS memory buffer is
cleared out after the process completes.

Change-Id: I1a033ffe73b8c309449f874d5187708d0a8846d2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: get BL31 arguments from previous bootloader

This patch implements handlers which platforms can override to
get the BL31 arguments passed by the previous bootloader.

Change-Id: I6b9628a984644

Tegra: get BL31 arguments from previous bootloader

This patch implements handlers which platforms can override to
get the BL31 arguments passed by the previous bootloader.

Change-Id: I6b9628a984644ce1b5de5aa6d7cd890e57241d89
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: return BL32 entry point info if it is valid

This patch returns pointer to the BL32 entrypoint info only if
it is valid.

Change-Id: I71ce3c4626681753c94f3a7bbaa50c26c74874cb
Signed-off-by: Va

Tegra: return BL32 entry point info if it is valid

This patch returns pointer to the BL32 entrypoint info only if
it is valid.

Change-Id: I71ce3c4626681753c94f3a7bbaa50c26c74874cb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: configure TZDRAM fence during early setup

This patch configures the TZDRAM fence during early platform
setup to allow the memory controller to enable DRAM encryption
before the TZDRAM actuall

Tegra: configure TZDRAM fence during early setup

This patch configures the TZDRAM fence during early platform
setup to allow the memory controller to enable DRAM encryption
before the TZDRAM actually gets used.

Change-Id: I0169ef9dda75699527b4e30c9e617a9036ba1d76
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: restore TZRAM settings on "System Resume"

This patch restores the TZRAM fence and the access permissions
on exiting the "System Suspend" state.

Change-Id: Ie313fca5a861c73f80df9639b01115780f

Tegra: restore TZRAM settings on "System Resume"

This patch restores the TZRAM fence and the access permissions
on exiting the "System Suspend" state.

Change-Id: Ie313fca5a861c73f80df9639b01115780fb6e217
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: enable ECC/Parity protection for Cortex-A57 CPUs

This patch enables L2 ECC and Parity Protection for ARM Cortex-A57 CPUs
for Tegra SoCs.

Change-Id: I038fcd529991d0201a4951ce2730ab71b1c980f9

Tegra: enable ECC/Parity protection for Cortex-A57 CPUs

This patch enables L2 ECC and Parity Protection for ARM Cortex-A57 CPUs
for Tegra SoCs.

Change-Id: I038fcd529991d0201a4951ce2730ab71b1c980f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: GIC: differentiate between FIQs targeted towards EL3/S-EL1

This patch modifies the secure IRQ registration process to allow platforms
to specify the target CPUs as well as the owner of the IR

Tegra: GIC: differentiate between FIQs targeted towards EL3/S-EL1

This patch modifies the secure IRQ registration process to allow platforms
to specify the target CPUs as well as the owner of the IRQ. IRQs "owned"
by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted
OS would return INTR_TYPE_S_EL1 as a result.

Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: implement FIQ interrupt handler

This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.

Tegra: implement FIQ interrupt handler

This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.

The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.

Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: GIC: enable FIQ interrupt handling

Tegra chips support multiple FIQ interrupt sources. These interrupts
are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
new FIQ handler woul

Tegra: GIC: enable FIQ interrupt handling

Tegra chips support multiple FIQ interrupt sources. These interrupts
are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
new FIQ handler would be added in a subsequent change which can be
registered by the platform code.

This patch adds the GIC programming as part of the tegra_gic_setup()
which now takes an array of all the FIQ interrupts to be enabled for
the platform. The Tegra132 and Tegra210 platforms right now do not
register for any FIQ interrupts themselves, but will definitely use
this support in the future.

Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: implement common handler `plat_get_target_pwr_state()`

This patch adds a platform handler to calculate the proper target power
level at the specified affinity level.

Tegra platforms assign a

Tegra: implement common handler `plat_get_target_pwr_state()`

This patch adds a platform handler to calculate the proper target power
level at the specified affinity level.

Tegra platforms assign a local state value in order of decreasing depth
of the power state i.e. for two power states X & Y, if X < Y then X
represents a shallower power state than Y. As a result, the coordinated
target local power state for a power domain will be the maximum of the
requested local power state values.

Change-Id: I67360684b7f5b783fcfdd605b96da5375fa05417
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: include platform_def.h to access UART macros

This patch includes platform_def.h required to access UART macros -
"TEGRA_BOOT_UART_CLK_IN_HZ" and "TEGRA_CONSOLE_BAUDRATE" from
tegra_helpers.S.

Tegra: include platform_def.h to access UART macros

This patch includes platform_def.h required to access UART macros -
"TEGRA_BOOT_UART_CLK_IN_HZ" and "TEGRA_CONSOLE_BAUDRATE" from
tegra_helpers.S.

Change-Id: Ieb63968a48dc299d03e81ddeb1ccc871cf3397a1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: allow SiP smc calls from Secure World

This patch removes the restriction of allowing SiP calls only from the
non-secure world. The secure world can issue SiP calls as a result of
this patch n

Tegra: allow SiP smc calls from Secure World

This patch removes the restriction of allowing SiP calls only from the
non-secure world. The secure world can issue SiP calls as a result of
this patch now.

Change-Id: Idd64e893ae8e114bba0196872d3ec544cac150bf
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: handler for per-soc early setup

This patch adds a weak handler for early platform setup which
can be overriden by the soc-specific handlers to perform any
early setup tasks.

Change-Id: I1a7a

Tegra: handler for per-soc early setup

This patch adds a weak handler for early platform setup which
can be overriden by the soc-specific handlers to perform any
early setup tasks.

Change-Id: I1a7a98d59b2332a3030c6dca5a9b7be977177326
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: relocate code to BL31_BASE during cold boot

This patch adds support to relocate BL3-1 code to BL31_BASE in case
we cold boot to a different address. This is particularly useful to
maintain co

Tegra: relocate code to BL31_BASE during cold boot

This patch adds support to relocate BL3-1 code to BL31_BASE in case
we cold boot to a different address. This is particularly useful to
maintain compatibility with legacy BL2 code.

This patch also checks to see if the image base address matches either
the TZDRAM or TZSRAM base.

Change-Id: I72c96d7f89076701a6ac2537d4c06565c54dab9c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: Disable A57/A53 cache non-temporal hints

This change disables the cache non-temporal hints for A57 and
A53 CPUs on Tegra.

Change-Id: I279d95aec5afbc3ca3cc4b34aa16de3f2c83a4fc
Signed-off-by:

Tegra: Disable A57/A53 cache non-temporal hints

This change disables the cache non-temporal hints for A57 and
A53 CPUs on Tegra.

Change-Id: I279d95aec5afbc3ca3cc4b34aa16de3f2c83a4fc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #835 from rockchip-linux/rk3399-atf-cleanup-20170210

RK3399 ARM TF clean up 20170210

rockchip: rk3399: enable secure accessing for SRAM

Sorry to miss the security configuration for SRAM, if we don't support
it, somebody may modify the comment of SRAM in the non-secure space.
Let's f

rockchip: rk3399: enable secure accessing for SRAM

Sorry to miss the security configuration for SRAM, if we don't support
it, somebody may modify the comment of SRAM in the non-secure space.
Let's fix this issue.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

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rockchip: rk3399: Use tFC value instead of tRFC value

This fixes code that set a tFC value in a register using the tRFC
value instead.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

rockchip: rk3399: Fix CAS latency setting

The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.

Signed-off-by: Derek Basehore <dbasehore

rockchip: rk3399: Fix CAS latency setting

The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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rockchip: rk3399: disable training modules after DDR DFS

On resume, we use the DFS hardware to switch frequency index,
followed by a full training sequence on that index. Leaving
the DFS training mo

rockchip: rk3399: disable training modules after DDR DFS

On resume, we use the DFS hardware to switch frequency index,
followed by a full training sequence on that index. Leaving
the DFS training modules enabled causes issues with the full
training done at resume. We also only needs these enabled
during a call to ddr_set_rate during runtime, so there's no
issue disabling them at the end of ddr_set_rate.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

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rockchip: rk3399: Move DQS drive strength setting to M0

This moves the setting of the DQS drive strength to the M0 to minimize
the impact on DDR transactions. We need to have the DQS drive strength

rockchip: rk3399: Move DQS drive strength setting to M0

This moves the setting of the DQS drive strength to the M0 to minimize
the impact on DDR transactions. We need to have the DQS drive strength
changed for data training, which is triggered by the M0, but it also
needs to be changed back when data training is finished.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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rockchip: rk3399: Remove dram dfs optimization

This removes an optimization to not recalculate parameters if the
frequency index being switched to hold the next frequency. This is
because some regis

rockchip: rk3399: Remove dram dfs optimization

This removes an optimization to not recalculate parameters if the
frequency index being switched to hold the next frequency. This is
because some registers do not have a copy per frequency index, so this
optimization might be causing problems.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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