1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl31.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <cortex_a57.h> 38 #include <cortex_a53.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <errno.h> 42 #include <memctrl.h> 43 #include <mmio.h> 44 #include <platform.h> 45 #include <platform_def.h> 46 #include <stddef.h> 47 #include <tegra_def.h> 48 #include <tegra_private.h> 49 50 /******************************************************************************* 51 * Declarations of linker defined symbols which will help us find the layout 52 * of trusted SRAM 53 ******************************************************************************/ 54 extern unsigned long __RO_START__; 55 extern unsigned long __RO_END__; 56 extern unsigned long __BL31_END__; 57 58 extern uint64_t tegra_bl31_phys_base; 59 extern uint64_t tegra_console_base; 60 61 /* 62 * The next 3 constants identify the extents of the code, RO data region and the 63 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 64 * therefore they must be page-aligned. It is the responsibility of the linker 65 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 66 * refer to page-aligned addresses. 67 */ 68 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 69 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 70 #define BL31_END (unsigned long)(&__BL31_END__) 71 72 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 73 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 74 .tzdram_size = (uint64_t)TZDRAM_SIZE 75 }; 76 77 /******************************************************************************* 78 * This variable holds the non-secure image entry address 79 ******************************************************************************/ 80 extern uint64_t ns_image_entrypoint; 81 82 /******************************************************************************* 83 * The following platform setup functions are weakly defined. They 84 * provide typical implementations that will be overridden by a SoC. 85 ******************************************************************************/ 86 #pragma weak plat_early_platform_setup 87 88 void plat_early_platform_setup(void) 89 { 90 ; /* do nothing */ 91 } 92 93 /******************************************************************************* 94 * Return a pointer to the 'entry_point_info' structure of the next image for 95 * security state specified. BL33 corresponds to the non-secure image type 96 * while BL32 corresponds to the secure image type. 97 ******************************************************************************/ 98 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 99 { 100 if (type == NON_SECURE) 101 return &bl33_image_ep_info; 102 103 /* return BL32 entry point info if it is valid */ 104 if (type == SECURE && bl32_image_ep_info.pc) 105 return &bl32_image_ep_info; 106 107 return NULL; 108 } 109 110 /******************************************************************************* 111 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 112 * passes this platform specific information. 113 ******************************************************************************/ 114 plat_params_from_bl2_t *bl31_get_plat_params(void) 115 { 116 return &plat_bl31_params_from_bl2; 117 } 118 119 /******************************************************************************* 120 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 121 * info. 122 ******************************************************************************/ 123 void bl31_early_platform_setup(bl31_params_t *from_bl2, 124 void *plat_params_from_bl2) 125 { 126 plat_params_from_bl2_t *plat_params = 127 (plat_params_from_bl2_t *)plat_params_from_bl2; 128 #if DEBUG 129 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 130 #endif 131 132 /* 133 * Copy BL3-3, BL3-2 entry point information. 134 * They are stored in Secure RAM, in BL2's address space. 135 */ 136 assert(from_bl2->bl33_ep_info); 137 bl33_image_ep_info = *from_bl2->bl33_ep_info; 138 139 if (from_bl2->bl32_ep_info) 140 bl32_image_ep_info = *from_bl2->bl32_ep_info; 141 142 /* 143 * Parse platform specific parameters - TZDRAM aperture base and size 144 */ 145 assert(plat_params); 146 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 147 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 148 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 149 150 /* 151 * It is very important that we run either from TZDRAM or TZSRAM base. 152 * Add an explicit check here. 153 */ 154 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 155 (TEGRA_TZRAM_BASE != BL31_BASE)) 156 panic(); 157 158 /* 159 * Get the base address of the UART controller to be used for the 160 * console 161 */ 162 assert(plat_params->uart_id); 163 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 164 165 /* 166 * Configure the UART port to be used as the console 167 */ 168 assert(tegra_console_base); 169 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 170 TEGRA_CONSOLE_BAUDRATE); 171 172 /* Initialise crash console */ 173 plat_crash_console_init(); 174 175 /* 176 * Do initial security configuration to allow DRAM/device access. 177 */ 178 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 179 plat_bl31_params_from_bl2.tzdram_size); 180 181 /* Early platform setup for Tegra SoCs */ 182 plat_early_platform_setup(); 183 184 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? 185 "Denver" : "ARM", read_mpidr()); 186 } 187 188 /******************************************************************************* 189 * Initialize the gic, configure the SCR. 190 ******************************************************************************/ 191 void bl31_platform_setup(void) 192 { 193 uint32_t tmp_reg; 194 195 /* Initialize the gic cpu and distributor interfaces */ 196 plat_gic_setup(); 197 198 /* 199 * Initialize delay timer 200 */ 201 tegra_delay_timer_init(); 202 203 /* 204 * Setup secondary CPU POR infrastructure. 205 */ 206 plat_secondary_setup(); 207 208 /* 209 * Initial Memory Controller configuration. 210 */ 211 tegra_memctrl_setup(); 212 213 /* 214 * Set up the TZRAM memory aperture to allow only secure world 215 * access 216 */ 217 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 218 219 /* Set the next EL to be AArch64 */ 220 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 221 write_scr(tmp_reg); 222 223 INFO("BL3-1: Tegra platform setup complete\n"); 224 } 225 226 /******************************************************************************* 227 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 228 ******************************************************************************/ 229 void bl31_plat_runtime_setup(void) 230 { 231 /* Initialize the runtime console */ 232 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 233 TEGRA_CONSOLE_BAUDRATE); 234 } 235 236 /******************************************************************************* 237 * Perform the very early platform specific architectural setup here. At the 238 * moment this only intializes the mmu in a quick and dirty way. 239 ******************************************************************************/ 240 void bl31_plat_arch_setup(void) 241 { 242 unsigned long bl31_base_pa = tegra_bl31_phys_base; 243 unsigned long total_base = bl31_base_pa; 244 unsigned long total_size = BL32_BASE - BL31_RO_BASE; 245 unsigned long ro_start = bl31_base_pa; 246 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; 247 const mmap_region_t *plat_mmio_map = NULL; 248 #if USE_COHERENT_MEM 249 unsigned long coh_start, coh_size; 250 #endif 251 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 252 253 /* add memory regions */ 254 mmap_add_region(total_base, total_base, 255 total_size, 256 MT_MEMORY | MT_RW | MT_SECURE); 257 mmap_add_region(ro_start, ro_start, 258 ro_size, 259 MT_MEMORY | MT_RO | MT_SECURE); 260 261 /* map TZDRAM used by BL31 as coherent memory */ 262 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 263 mmap_add_region(params_from_bl2->tzdram_base, 264 params_from_bl2->tzdram_base, 265 BL31_SIZE, 266 MT_DEVICE | MT_RW | MT_SECURE); 267 } 268 269 #if USE_COHERENT_MEM 270 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 271 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 272 273 mmap_add_region(coh_start, coh_start, 274 coh_size, 275 MT_DEVICE | MT_RW | MT_SECURE); 276 #endif 277 278 /* add MMIO space */ 279 plat_mmio_map = plat_get_mmio_map(); 280 if (plat_mmio_map) 281 mmap_add(plat_mmio_map); 282 else 283 WARN("MMIO map not available\n"); 284 285 /* set up translation tables */ 286 init_xlat_tables(); 287 288 /* enable the MMU */ 289 enable_mmu_el3(0); 290 291 INFO("BL3-1: Tegra: MMU enabled\n"); 292 } 293 294 /******************************************************************************* 295 * Check if the given NS DRAM range is valid 296 ******************************************************************************/ 297 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 298 { 299 uint64_t end = base + size_in_bytes - 1; 300 301 /* 302 * Check if the NS DRAM address is valid 303 */ 304 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || 305 (base >= end)) { 306 ERROR("NS address is out-of-bounds!\n"); 307 return -EFAULT; 308 } 309 310 /* 311 * TZDRAM aperture contains the BL31 and BL32 images, so we need 312 * to check if the NS DRAM range overlaps the TZDRAM aperture. 313 */ 314 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 315 ERROR("NS address overlaps TZDRAM!\n"); 316 return -ENOTSUP; 317 } 318 319 /* valid NS address */ 320 return 0; 321 } 322