1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl31.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <cortex_a57.h> 38 #include <cortex_a53.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <errno.h> 42 #include <memctrl.h> 43 #include <mmio.h> 44 #include <platform.h> 45 #include <platform_def.h> 46 #include <stddef.h> 47 #include <tegra_def.h> 48 #include <tegra_private.h> 49 50 /******************************************************************************* 51 * Declarations of linker defined symbols which will help us find the layout 52 * of trusted SRAM 53 ******************************************************************************/ 54 extern unsigned long __RO_START__; 55 extern unsigned long __RO_END__; 56 extern unsigned long __BL31_END__; 57 58 extern uint64_t tegra_bl31_phys_base; 59 extern uint64_t tegra_console_base; 60 61 /* 62 * The next 3 constants identify the extents of the code, RO data region and the 63 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 64 * therefore they must be page-aligned. It is the responsibility of the linker 65 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 66 * refer to page-aligned addresses. 67 */ 68 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 69 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 70 #define BL31_END (unsigned long)(&__BL31_END__) 71 72 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 73 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 74 .tzdram_size = (uint64_t)TZDRAM_SIZE 75 }; 76 77 /******************************************************************************* 78 * This variable holds the non-secure image entry address 79 ******************************************************************************/ 80 extern uint64_t ns_image_entrypoint; 81 82 /******************************************************************************* 83 * Return a pointer to the 'entry_point_info' structure of the next image for 84 * security state specified. BL33 corresponds to the non-secure image type 85 * while BL32 corresponds to the secure image type. 86 ******************************************************************************/ 87 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 88 { 89 if (type == NON_SECURE) 90 return &bl33_image_ep_info; 91 92 if (type == SECURE) 93 return &bl32_image_ep_info; 94 95 return NULL; 96 } 97 98 /******************************************************************************* 99 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 100 * passes this platform specific information. 101 ******************************************************************************/ 102 plat_params_from_bl2_t *bl31_get_plat_params(void) 103 { 104 return &plat_bl31_params_from_bl2; 105 } 106 107 /******************************************************************************* 108 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 109 * info. 110 ******************************************************************************/ 111 void bl31_early_platform_setup(bl31_params_t *from_bl2, 112 void *plat_params_from_bl2) 113 { 114 plat_params_from_bl2_t *plat_params = 115 (plat_params_from_bl2_t *)plat_params_from_bl2; 116 #if DEBUG 117 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 118 #endif 119 120 /* 121 * Copy BL3-3, BL3-2 entry point information. 122 * They are stored in Secure RAM, in BL2's address space. 123 */ 124 assert(from_bl2->bl33_ep_info); 125 bl33_image_ep_info = *from_bl2->bl33_ep_info; 126 127 if (from_bl2->bl32_ep_info) 128 bl32_image_ep_info = *from_bl2->bl32_ep_info; 129 130 /* 131 * Parse platform specific parameters - TZDRAM aperture base and size 132 */ 133 assert(plat_params); 134 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 135 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 136 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 137 138 /* 139 * It is very important that we run either from TZDRAM or TZSRAM base. 140 * Add an explicit check here. 141 */ 142 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 143 (TEGRA_TZRAM_BASE != BL31_BASE)) 144 panic(); 145 146 /* 147 * Get the base address of the UART controller to be used for the 148 * console 149 */ 150 assert(plat_params->uart_id); 151 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 152 153 /* 154 * Configure the UART port to be used as the console 155 */ 156 assert(tegra_console_base); 157 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 158 TEGRA_CONSOLE_BAUDRATE); 159 160 /* Initialise crash console */ 161 plat_crash_console_init(); 162 163 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? 164 "Denver" : "ARM", read_mpidr()); 165 } 166 167 /******************************************************************************* 168 * Initialize the gic, configure the SCR. 169 ******************************************************************************/ 170 void bl31_platform_setup(void) 171 { 172 uint32_t tmp_reg; 173 174 /* 175 * Initialize delay timer 176 */ 177 tegra_delay_timer_init(); 178 179 /* 180 * Setup secondary CPU POR infrastructure. 181 */ 182 plat_secondary_setup(); 183 184 /* 185 * Initial Memory Controller configuration. 186 */ 187 tegra_memctrl_setup(); 188 189 /* 190 * Do initial security configuration to allow DRAM/device access. 191 */ 192 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 193 plat_bl31_params_from_bl2.tzdram_size); 194 195 /* 196 * Set up the TZRAM memory aperture to allow only secure world 197 * access 198 */ 199 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 200 201 /* Set the next EL to be AArch64 */ 202 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 203 write_scr(tmp_reg); 204 205 /* Initialize the gic cpu and distributor interfaces */ 206 tegra_gic_setup(); 207 208 INFO("BL3-1: Tegra platform setup complete\n"); 209 } 210 211 /******************************************************************************* 212 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 213 ******************************************************************************/ 214 void bl31_plat_runtime_setup(void) 215 { 216 /* Initialize the runtime console */ 217 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 218 TEGRA_CONSOLE_BAUDRATE); 219 } 220 221 /******************************************************************************* 222 * Perform the very early platform specific architectural setup here. At the 223 * moment this only intializes the mmu in a quick and dirty way. 224 ******************************************************************************/ 225 void bl31_plat_arch_setup(void) 226 { 227 unsigned long bl31_base_pa = tegra_bl31_phys_base; 228 unsigned long total_base = bl31_base_pa; 229 unsigned long total_size = BL32_BASE - BL31_RO_BASE; 230 unsigned long ro_start = bl31_base_pa; 231 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; 232 const mmap_region_t *plat_mmio_map = NULL; 233 #if USE_COHERENT_MEM 234 unsigned long coh_start, coh_size; 235 #endif 236 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 237 238 /* add memory regions */ 239 mmap_add_region(total_base, total_base, 240 total_size, 241 MT_MEMORY | MT_RW | MT_SECURE); 242 mmap_add_region(ro_start, ro_start, 243 ro_size, 244 MT_MEMORY | MT_RO | MT_SECURE); 245 246 /* map TZDRAM used by BL31 as coherent memory */ 247 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 248 mmap_add_region(params_from_bl2->tzdram_base, 249 params_from_bl2->tzdram_base, 250 BL31_SIZE, 251 MT_DEVICE | MT_RW | MT_SECURE); 252 } 253 254 #if USE_COHERENT_MEM 255 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 256 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 257 258 mmap_add_region(coh_start, coh_start, 259 coh_size, 260 MT_DEVICE | MT_RW | MT_SECURE); 261 #endif 262 263 /* add MMIO space */ 264 plat_mmio_map = plat_get_mmio_map(); 265 if (plat_mmio_map) 266 mmap_add(plat_mmio_map); 267 else 268 WARN("MMIO map not available\n"); 269 270 /* set up translation tables */ 271 init_xlat_tables(); 272 273 /* enable the MMU */ 274 enable_mmu_el3(0); 275 276 INFO("BL3-1: Tegra: MMU enabled\n"); 277 } 278 279 /******************************************************************************* 280 * Check if the given NS DRAM range is valid 281 ******************************************************************************/ 282 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 283 { 284 uint64_t end = base + size_in_bytes - 1; 285 286 /* 287 * Check if the NS DRAM address is valid 288 */ 289 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || 290 (base >= end)) { 291 ERROR("NS address is out-of-bounds!\n"); 292 return -EFAULT; 293 } 294 295 /* 296 * TZDRAM aperture contains the BL31 and BL32 images, so we need 297 * to check if the NS DRAM range overlaps the TZDRAM aperture. 298 */ 299 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 300 ERROR("NS address overlaps TZDRAM!\n"); 301 return -ENOTSUP; 302 } 303 304 /* valid NS address */ 305 return 0; 306 } 307