1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __TEGRA_DEF_H__ 32 #define __TEGRA_DEF_H__ 33 34 #include <platform_def.h> 35 36 /******************************************************************************* 37 * Power down state IDs 38 ******************************************************************************/ 39 #define PSTATE_ID_CORE_POWERDN 7 40 #define PSTATE_ID_CLUSTER_IDLE 16 41 #define PSTATE_ID_CLUSTER_POWERDN 17 42 #define PSTATE_ID_SOC_POWERDN 27 43 44 /******************************************************************************* 45 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 46 * call as the `state-id` field in the 'power state' parameter. 47 ******************************************************************************/ 48 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 49 50 /******************************************************************************* 51 * Platform power states (used by PSCI framework) 52 * 53 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 54 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 55 ******************************************************************************/ 56 #define PLAT_MAX_RET_STATE 1 57 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) 58 59 /******************************************************************************* 60 * Secure IRQ definitions 61 ******************************************************************************/ 62 #define TEGRA_SEC_IRQ_TARGET_MASK 0xF /* 4 A57's or 4 A53's */ 63 64 /******************************************************************************* 65 * GIC memory map 66 ******************************************************************************/ 67 #define TEGRA_GICD_BASE 0x50041000 68 #define TEGRA_GICC_BASE 0x50042000 69 70 /******************************************************************************* 71 * Tegra Memory Select Switch Controller constants 72 ******************************************************************************/ 73 #define TEGRA_MSELECT_BASE 0x50060000 74 75 #define MSELECT_CONFIG 0x0 76 #define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29) 77 #define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28) 78 #define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27) 79 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25) 80 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24) 81 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 82 UNSUPPORTED_TX_ERR_MASTER1_BIT) 83 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 84 ENABLE_WRAP_INCR_MASTER1_BIT | \ 85 ENABLE_WRAP_INCR_MASTER0_BIT) 86 87 /******************************************************************************* 88 * Tegra micro-seconds timer constants 89 ******************************************************************************/ 90 #define TEGRA_TMRUS_BASE 0x60005010 91 92 /******************************************************************************* 93 * Tegra Clock and Reset Controller constants 94 ******************************************************************************/ 95 #define TEGRA_CAR_RESET_BASE 0x60006000 96 97 /******************************************************************************* 98 * Tegra Flow Controller constants 99 ******************************************************************************/ 100 #define TEGRA_FLOWCTRL_BASE 0x60007000 101 102 /******************************************************************************* 103 * Tegra Secure Boot Controller constants 104 ******************************************************************************/ 105 #define TEGRA_SB_BASE 0x6000C200 106 107 /******************************************************************************* 108 * Tegra Exception Vectors constants 109 ******************************************************************************/ 110 #define TEGRA_EVP_BASE 0x6000F000 111 112 /******************************************************************************* 113 * Tegra UART controller base addresses 114 ******************************************************************************/ 115 #define TEGRA_UARTA_BASE 0x70006000 116 #define TEGRA_UARTB_BASE 0x70006040 117 #define TEGRA_UARTC_BASE 0x70006200 118 #define TEGRA_UARTD_BASE 0x70006300 119 #define TEGRA_UARTE_BASE 0x70006400 120 121 /******************************************************************************* 122 * Tegra Power Mgmt Controller constants 123 ******************************************************************************/ 124 #define TEGRA_PMC_BASE 0x7000E400 125 126 /******************************************************************************* 127 * Tegra Memory Controller constants 128 ******************************************************************************/ 129 #define TEGRA_MC_BASE 0x70019000 130 131 /******************************************************************************* 132 * Tegra TZRAM constants 133 ******************************************************************************/ 134 #define TEGRA_TZRAM_BASE 0x7C010000 135 #define TEGRA_TZRAM_SIZE 0x10000 136 137 #endif /* __TEGRA_DEF_H__ */ 138