Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): manage io_policies with FCONF
feat(fdts): add IO policies for STM32MP1

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): use FCONF to configure platform
feat(fdts): add STM32MP1 fw-config DT files

Merge "feat(plat/st): improve FIP image loading from MMC" into integration

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): use FIP to load images
refactor(plat/st): updates for OP-TEE
feat(lib/optee): introduce optee_header_is_valid

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): use FIP to load images
refactor(plat/st): updates for OP-TEE
feat(lib/optee): introduce optee_header_is_valid()

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fix(plat/marvell/a3k): enable workaround for erratum 1530924

Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53
revisions from r0p0 to r0p4.

Enable the workaround for this err

fix(plat/marvell/a3k): enable workaround for erratum 1530924

Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53
revisions from r0p0 to r0p4.

Enable the workaround for this erratum.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I753225040e49e956788d5617cd7ce76d5e6ea8e8

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feat(plat/st): add a new DDR firewall management

Based on FCONF framework, define DDR firewall regions
from firmware config file instead of static defines.

Change-Id: I471e15410ca286d9079a86e3dc347

feat(plat/st): add a new DDR firewall management

Based on FCONF framework, define DDR firewall regions
from firmware config file instead of static defines.

Change-Id: I471e15410ca286d9079a86e3dc3474f66d37b5ab
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge changes from topic "advk-serror" into integration

* changes:
fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default
fix(plat/marvell/a3k): update information about PCIe abort hack

fix(plat/qti/sc7180): qti smc addition

Adding QTI SIP SMC CALL to detect qti platform supporting ARM 64 SMC
calls or not.

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I323132

fix(plat/qti/sc7180): qti smc addition

Adding QTI SIP SMC CALL to detect qti platform supporting ARM 64 SMC
calls or not.

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3231325a6ffe5aa69856dd25ac2c0a2004484e4b

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Merge changes I0ae8a6ea,I0b4fc83e into integration

* changes:
feat(tc): Enable SVE for both secure and non-secure world
feat(tc): populate HW_CONFIG in BL31

feat(tc): Enable SVE for both secure and non-secure world

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0ae8a6ea3245373a17af76c9b7dc3f38f3711091

feat(tc): populate HW_CONFIG in BL31

BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate

feat(tc): populate HW_CONFIG in BL31

BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate fconf.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0b4fc83e6e0a0b9401f692516654eb9a3b037616

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refactor(plat/st): use TZC400 bindings

This avoids duplicate define of TZC_REGION_NSEC_ALL_ACCESS_RDWR.
And remove the previous TZC400 definitions from stm32mp1_def.h.

Change-Id: I6c72c2a18731f69d8

refactor(plat/st): use TZC400 bindings

This avoids duplicate define of TZC_REGION_NSEC_ALL_ACCESS_RDWR.
And remove the previous TZC400 definitions from stm32mp1_def.h.

Change-Id: I6c72c2a18731f69d855fbce8ce822a21da9364fa
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): manage io_policies with FCONF

Introduced IO policies management through the trusted
boot firmware config device tree for UUID references.

Change-Id: Ibeeabede51b0514ebba26dbbdae58736

feat(plat/st): manage io_policies with FCONF

Introduced IO policies management through the trusted
boot firmware config device tree for UUID references.

Change-Id: Ibeeabede51b0514ebba26dbbdae587363b2aa0a7
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): use FCONF to configure platform

Add required code to support FCONF on STM32MP1 platform.
The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2.
It will be used to config

feat(plat/st): use FCONF to configure platform

Add required code to support FCONF on STM32MP1 platform.
The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2.
It will be used to configure the addresses where to load other binaries.
BL2 should be agnostic of which BL32 is in the FIP (OP-TEE or SP_min),
so optee_utils.c is always compiled, and some OP-TEE flags are removed.

Change-Id: Id957b49b0117864136250bfc416664f815043ada
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): improve FIP image loading from MMC

Instead of using a scratch buffer of 512 bytes, we can directly use the
image address and max size. The mmc_block_dev_spec struct info is then
overw

feat(plat/st): improve FIP image loading from MMC

Instead of using a scratch buffer of 512 bytes, we can directly use the
image address and max size. The mmc_block_dev_spec struct info is then
overwritten for each image with this info, except FW_CONFIG and GPT
table which will still use the scratch buffer.
This allows using multiple blocks read on MMC, and so improves the boot
time.
A cache invalidate is required for the remaining data not used from the
first and last blocks read. It is not required for FW_CONFIG_ID,
as it is in scratch buffer in SYSRAM, and also because bl_mem_params
struct is overwritten in this case. This should also not be done if
the image is not found (OP-TEE extra binaries when using SP_min).

Change-Id: If3ecfdfe35bb9db66284036ca49c4bd1be4fd121
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): use FIP to load images

BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP fil

feat(plat/st): use FIP to load images

BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP file.
One DTB is created for each BL. To reduce their sizes, 2 new dtsi file are
in charge of removing useless nodes for a given BL. This is done because
BL2 and BL32 share the same device tree files base.

The previous way of booting is still available, the compilation flag
STM32MP_USE_STM32IMAGE has to be set to 1 in the make command. Some files
are duplicated and their names modified with _stm32_ to avoid too much
switches in the code.

Change-Id: I1ffada0af58486d4cf6044511b51e56b52269817
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "feat(fvp): enable external SP images in BL2 config" into integration

refactor(plat/st): updates for OP-TEE

Protect BL32 (SP_min) with MMU if OP-TEE is not used.
Validate OP-TEE header with optee_header_is_valid().
Use default values in bl2_mem_params_descs[]. They wi

refactor(plat/st): updates for OP-TEE

Protect BL32 (SP_min) with MMU if OP-TEE is not used.
Validate OP-TEE header with optee_header_is_valid().
Use default values in bl2_mem_params_descs[]. They will be overwritten
in bl2_plat_handle_post_image_load() if OP-TEE is used.

Change-Id: I8614f3a17caa827561614d0f25f30ee90c4ec3fe
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "feat(board/rdn2): add tzc master source ids for soc dma" into integration

fix(arm_fpga): reserve BL31 memory

Embarrassingly we never told the non-secure world that secure firmware
lives in the first few hundred KBs of DRAM, so any non-secure payload
could happily overwrit

fix(arm_fpga): reserve BL31 memory

Embarrassingly we never told the non-secure world that secure firmware
lives in the first few hundred KBs of DRAM, so any non-secure payload
could happily overwrite TF-A, and we couldn't even blame it.

Advertise the BL31 region in the reserved-memory DT node, so non-secure
world stays out of it.

This fixes Linux booting on FPGAs with less memory than usual.

Change-Id: I7fbe7d42c0b251c0ccc43d7c50ca902013d152ec
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I3c20611a,Ib1671011,I5eab3f33,Ib149b3ea into integration

* changes:
refactor(plat/nxp): refine api to read SVR register
refactor(plat/nxp): each errata use a seperate source file

Merge changes I3c20611a,Ib1671011,I5eab3f33,Ib149b3ea into integration

* changes:
refactor(plat/nxp): refine api to read SVR register
refactor(plat/nxp): each errata use a seperate source file
refactor(plat/nxp): use a unified errata api
refactor(plat/soc-lx2160): move errata to common directory

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fix(arm_fpga): limit BL31 memory usage

At the moment we specified the BL31 memory limits to 1MB; since we
typically have gigabytes of DRAM, we can be quite generous.

However the default parameters

fix(arm_fpga): limit BL31 memory usage

At the moment we specified the BL31 memory limits to 1MB; since we
typically have gigabytes of DRAM, we can be quite generous.

However the default parameters expect the devicetree binary at
0x80070000, so we should actually make sure we have no code or data
beyond that point.

Limit the ARM FPGA BL31 memory footprint to this available 7*64K region.
We stay within the limit at the moment, with more than half of it
reserved for stacks, so this could be downsized later should we run
into problems.

The PIE addresses stay as they are, since the default addresses do not
apply there anywhere, and the build is broken anyway.

Change-Id: I7768af1a93ff67096f4359fc5f5feb66464bafaa
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fvp): enable external SP images in BL2 config

Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Ser

feat(fvp): enable external SP images in BL2 config

Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Services). This commit implements a workaround to enable adding
SP UUIDs to the list at build time.

Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: Iff85d3778596d23d777dec458f131bd7a8647031

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feat(arm_fpga): support GICv4 images

Up until now we relied on the GICs used in our FPGA images to be GICv3
compliant, without the "direct virtual injection" feature (aka GICv4)
enabled.
To support

feat(arm_fpga): support GICv4 images

Up until now we relied on the GICs used in our FPGA images to be GICv3
compliant, without the "direct virtual injection" feature (aka GICv4)
enabled.
To support newer images which have GICv4 compliant GICs, enable the
newly introduced GICv4 detection code, and use that also when we adjust
the redistributor region size in the devicetree.

This allows the same BL31 image to be used with GICv3 or GICv4 FPGA
images.

Change-Id: I9f6435a6d5150983625efe3650a8b7d1ef11b1d1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec

feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec or not. This just changes the number of 64K MMIO pages
we expect per redistributor.

To support firmware builds which run on variable systems (emulators,
fast model or FPGAs), let's make this decision at runtime.
The GIC specification provides several architected flags to learn the
size of the MMIO frame per redistributor, we use GICR_TYPER[VLPI] here.

Provide a (static inline) function to return the size of each
redistributor.
We keep the GIC_ENABLE_V4_EXTN build time variable around, but change
its meaning to enable this autodetection code. Systems not defining this
rely on a "pure" GICv3 (as before), but platforms setting it to "1" can
now deal with both configurations.

Change-Id: I9ede4acf058846157a0a9e2ef6103bf07c7655d9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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