1 /* 2 * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 21 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 22 U(FVP_MAX_PE_PER_CPU)) 23 24 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 25 PLATFORM_CORE_COUNT + U(1)) 26 27 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 28 29 /* 30 * Other platform porting definitions are provided by included headers 31 */ 32 33 /* 34 * Required ARM standard platform porting definitions 35 */ 36 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 37 38 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 39 40 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 41 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 42 43 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 44 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 45 46 #if ENABLE_RME 47 #define PLAT_ARM_RMM_BASE (RMM_BASE) 48 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 49 #endif 50 51 /* 52 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 53 * max size of BL32 image. 54 */ 55 #if defined(SPD_spmd) 56 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 57 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 58 #endif 59 60 /* virtual address used by dynamic mem_protect for chunk_base */ 61 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 62 63 /* No SCP in FVP */ 64 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 65 66 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 67 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 68 69 #define PLAT_HW_CONFIG_DTB_BASE ULL(0x82000000) 70 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) 71 72 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 73 PLAT_HW_CONFIG_DTB_BASE, \ 74 PLAT_HW_CONFIG_DTB_SIZE, \ 75 MT_MEMORY | MT_RO | MT_NS) 76 /* 77 * Load address of BL33 for this platform port 78 */ 79 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 80 81 /* 82 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 83 * plat_arm_mmap array defined for each BL stage. 84 */ 85 #if defined(IMAGE_BL31) 86 # if SPM_MM 87 # define PLAT_ARM_MMAP_ENTRIES 10 88 # if ENABLE_RME 89 # define MAX_XLAT_TABLES 10 90 # else 91 # define MAX_XLAT_TABLES 9 92 # endif 93 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 94 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 95 # else 96 # define PLAT_ARM_MMAP_ENTRIES 9 97 # if USE_DEBUGFS 98 # if ENABLE_RME 99 # define MAX_XLAT_TABLES 9 100 # else 101 # define MAX_XLAT_TABLES 8 102 # endif 103 # else 104 # if ENABLE_RME 105 # define MAX_XLAT_TABLES 8 106 # else 107 # define MAX_XLAT_TABLES 7 108 # endif 109 # endif 110 # endif 111 #elif defined(IMAGE_BL32) 112 # define PLAT_ARM_MMAP_ENTRIES 9 113 # define MAX_XLAT_TABLES 6 114 #elif !USE_ROMLIB 115 # define PLAT_ARM_MMAP_ENTRIES 11 116 # define MAX_XLAT_TABLES 5 117 #else 118 # define PLAT_ARM_MMAP_ENTRIES 12 119 # define MAX_XLAT_TABLES 6 120 #endif 121 122 /* 123 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 124 * plus a little space for growth. 125 */ 126 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 127 128 /* 129 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 130 */ 131 132 #if USE_ROMLIB 133 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 134 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 135 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 136 #else 137 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 138 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 139 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 140 #endif 141 142 /* 143 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 144 * little space for growth. 145 */ 146 #if TRUSTED_BOARD_BOOT 147 #if COT_DESC_IN_DTB 148 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) 149 #else 150 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 151 #endif 152 #else 153 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 154 #endif 155 156 #if RESET_TO_BL31 157 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 158 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 159 ARM_SHARED_RAM_SIZE - \ 160 ARM_L0_GPT_SIZE) 161 #else 162 /* 163 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 164 * calculated using the current BL31 PROGBITS debug size plus the sizes of 165 * BL2 and BL1-RW 166 */ 167 #define PLAT_ARM_MAX_BL31_SIZE (UL(0x3D000) - ARM_L0_GPT_SIZE) 168 #endif /* RESET_TO_BL31 */ 169 170 #ifndef __aarch64__ 171 #if RESET_TO_SP_MIN 172 /* Size of Trusted SRAM - the first 4KB of shared memory */ 173 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 174 ARM_SHARED_RAM_SIZE) 175 #else 176 /* 177 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 178 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 179 * BL2 and BL1-RW 180 */ 181 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 182 #endif /* RESET_TO_SP_MIN */ 183 #endif 184 185 /* 186 * Size of cacheable stacks 187 */ 188 #if defined(IMAGE_BL1) 189 # if TRUSTED_BOARD_BOOT 190 # define PLATFORM_STACK_SIZE UL(0x1000) 191 # else 192 # define PLATFORM_STACK_SIZE UL(0x500) 193 # endif 194 #elif defined(IMAGE_BL2) 195 # if TRUSTED_BOARD_BOOT 196 # define PLATFORM_STACK_SIZE UL(0x1000) 197 # else 198 # define PLATFORM_STACK_SIZE UL(0x440) 199 # endif 200 #elif defined(IMAGE_BL2U) 201 # define PLATFORM_STACK_SIZE UL(0x400) 202 #elif defined(IMAGE_BL31) 203 # define PLATFORM_STACK_SIZE UL(0x800) 204 #elif defined(IMAGE_BL32) 205 # define PLATFORM_STACK_SIZE UL(0x440) 206 #elif defined(IMAGE_RMM) 207 # define PLATFORM_STACK_SIZE UL(0x440) 208 #endif 209 210 #define MAX_IO_DEVICES 3 211 #define MAX_IO_HANDLES 4 212 213 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 214 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 215 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 216 217 #if ARM_GPT_SUPPORT 218 /* 219 * Offset of the FIP in the GPT image. BL1 component uses this option 220 * as it does not load the partition table to get the FIP base 221 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 222 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 223 */ 224 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 225 #endif /* ARM_GPT_SUPPORT */ 226 227 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 228 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 229 230 /* 231 * PL011 related constants 232 */ 233 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 234 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 235 236 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 237 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 238 239 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 240 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 241 242 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 243 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 244 245 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 246 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 247 248 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 249 250 /* CCI related constants */ 251 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 252 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 253 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 254 255 /* CCI-500/CCI-550 on Base platform */ 256 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 257 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 258 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 259 260 /* CCN related constants. Only CCN 502 is currently supported */ 261 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 262 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 263 264 /* System timer related constants */ 265 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 266 267 /* Mailbox base address */ 268 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 269 270 271 /* TrustZone controller related constants 272 * 273 * Currently only filters 0 and 2 are connected on Base FVP. 274 * Filter 0 : CPU clusters (no access to DRAM by default) 275 * Filter 1 : not connected 276 * Filter 2 : LCDs (access to VRAM allowed by default) 277 * Filter 3 : not connected 278 * Programming unconnected filters will have no effect at the 279 * moment. These filter could, however, be connected in future. 280 * So care should be taken not to configure the unused filters. 281 * 282 * Allow only non-secure access to all DRAM to supported devices. 283 * Give access to the CPUs and Virtio. Some devices 284 * would normally use the default ID so allow that too. 285 */ 286 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 287 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 288 289 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 290 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 291 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 292 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 293 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 294 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 295 296 /* 297 * GIC related constants to cater for both GICv2 and GICv3 instances of an 298 * FVP. They could be overridden at runtime in case the FVP implements the 299 * legacy VE memory map. 300 */ 301 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 302 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 303 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 304 305 /* 306 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 307 * terminology. On a GICv2 system or mode, the lists will be merged and treated 308 * as Group 0 interrupts. 309 */ 310 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 311 ARM_G1S_IRQ_PROPS(grp), \ 312 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 313 GIC_INTR_CFG_LEVEL), \ 314 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 315 GIC_INTR_CFG_LEVEL) 316 317 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 318 319 #if SDEI_IN_FCONF 320 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 321 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 322 #else 323 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 324 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 325 #endif 326 327 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 328 PLAT_SP_IMAGE_NS_BUF_SIZE) 329 330 #define PLAT_SP_PRI PLAT_RAS_PRI 331 332 /* 333 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 334 */ 335 #ifdef __aarch64__ 336 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 337 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 338 #else 339 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 340 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 341 #endif 342 343 #endif /* PLATFORM_DEF_H */ 344