1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/partition/partition.h> 18 #include <lib/fconf/fconf.h> 19 #include <lib/fconf/fconf_dyn_cfg_getter.h> 20 #ifdef SPD_opteed 21 #include <lib/optee_utils.h> 22 #endif 23 #include <lib/utils.h> 24 #include <plat/arm/common/plat_arm.h> 25 #include <plat/common/platform.h> 26 27 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 28 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 29 30 /* Base address of fw_config received from BL1 */ 31 static uintptr_t config_base; 32 33 /* 34 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 35 * for `meminfo_t` data structure and fw_configs passed from BL1. 36 */ 37 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 38 39 /* Weak definitions may be overridden in specific ARM standard platform */ 40 #pragma weak bl2_early_platform_setup2 41 #pragma weak bl2_platform_setup 42 #pragma weak bl2_plat_arch_setup 43 #pragma weak bl2_plat_sec_mem_layout 44 #if MEASURED_BOOT 45 #pragma weak bl2_plat_get_hash 46 #endif 47 48 #if ENABLE_RME 49 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 50 bl2_tzram_layout.total_base, \ 51 bl2_tzram_layout.total_size, \ 52 MT_MEMORY | MT_RW | MT_ROOT) 53 #else 54 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 55 bl2_tzram_layout.total_base, \ 56 bl2_tzram_layout.total_size, \ 57 MT_MEMORY | MT_RW | MT_SECURE) 58 #endif /* ENABLE_RME */ 59 60 #pragma weak arm_bl2_plat_handle_post_image_load 61 62 /******************************************************************************* 63 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 64 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 65 * Copy it to a safe location before its reclaimed by later BL2 functionality. 66 ******************************************************************************/ 67 void arm_bl2_early_platform_setup(uintptr_t fw_config, 68 struct meminfo *mem_layout) 69 { 70 /* Initialize the console to provide early debug support */ 71 arm_console_boot_init(); 72 73 /* Setup the BL2 memory layout */ 74 bl2_tzram_layout = *mem_layout; 75 76 config_base = fw_config; 77 78 /* Initialise the IO layer and register platform IO devices */ 79 plat_arm_io_setup(); 80 81 /* Load partition table */ 82 #if ARM_GPT_SUPPORT 83 partition_init(GPT_IMAGE_ID); 84 #endif /* ARM_GPT_SUPPORT */ 85 86 } 87 88 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 89 { 90 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 91 92 generic_delay_timer_init(); 93 } 94 95 /* 96 * Perform BL2 preload setup. Currently we initialise the dynamic 97 * configuration here. 98 */ 99 void bl2_plat_preload_setup(void) 100 { 101 arm_bl2_dyn_cfg_init(); 102 103 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 104 /* Always use the FIP from bank 0 */ 105 arm_set_fip_addr(0U); 106 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 107 } 108 109 /* 110 * Perform ARM standard platform setup. 111 */ 112 void arm_bl2_platform_setup(void) 113 { 114 /* Initialize the secure environment */ 115 plat_arm_security_setup(); 116 117 #if defined(PLAT_ARM_MEM_PROT_ADDR) 118 arm_nor_psci_do_static_mem_protect(); 119 #endif 120 } 121 122 void bl2_platform_setup(void) 123 { 124 arm_bl2_platform_setup(); 125 } 126 127 /******************************************************************************* 128 * Perform the very early platform specific architectural setup here. At the 129 * moment this is only initializes the mmu in a quick and dirty way. 130 ******************************************************************************/ 131 void arm_bl2_plat_arch_setup(void) 132 { 133 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 134 /* 135 * Ensure ARM platforms don't use coherent memory in BL2 unless 136 * cryptocell integration is enabled. 137 */ 138 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 139 #endif 140 141 const mmap_region_t bl_regions[] = { 142 MAP_BL2_TOTAL, 143 ARM_MAP_BL_RO, 144 #if USE_ROMLIB 145 ARM_MAP_ROMLIB_CODE, 146 ARM_MAP_ROMLIB_DATA, 147 #endif 148 #if ARM_CRYPTOCELL_INTEG 149 ARM_MAP_BL_COHERENT_RAM, 150 #endif 151 ARM_MAP_BL_CONFIG_REGION, 152 {0} 153 }; 154 155 setup_page_tables(bl_regions, plat_arm_get_mmap()); 156 157 #ifdef __aarch64__ 158 enable_mmu_el1(0); 159 #else 160 enable_mmu_svc_mon(0); 161 #endif 162 163 arm_setup_romlib(); 164 } 165 166 void bl2_plat_arch_setup(void) 167 { 168 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 169 170 arm_bl2_plat_arch_setup(); 171 172 /* Fill the properties struct with the info from the config dtb */ 173 fconf_populate("FW_CONFIG", config_base); 174 175 /* TB_FW_CONFIG was also loaded by BL1 */ 176 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 177 assert(tb_fw_config_info != NULL); 178 179 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 180 } 181 182 int arm_bl2_handle_post_image_load(unsigned int image_id) 183 { 184 int err = 0; 185 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 186 #ifdef SPD_opteed 187 bl_mem_params_node_t *pager_mem_params = NULL; 188 bl_mem_params_node_t *paged_mem_params = NULL; 189 #endif 190 assert(bl_mem_params != NULL); 191 192 switch (image_id) { 193 #ifdef __aarch64__ 194 case BL32_IMAGE_ID: 195 #ifdef SPD_opteed 196 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 197 assert(pager_mem_params); 198 199 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 200 assert(paged_mem_params); 201 202 err = parse_optee_header(&bl_mem_params->ep_info, 203 &pager_mem_params->image_info, 204 &paged_mem_params->image_info); 205 if (err != 0) { 206 WARN("OPTEE header parse error.\n"); 207 } 208 #endif 209 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 210 break; 211 #endif 212 213 case BL33_IMAGE_ID: 214 /* BL33 expects to receive the primary CPU MPID (through r0) */ 215 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 216 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 217 break; 218 219 #ifdef SCP_BL2_BASE 220 case SCP_BL2_IMAGE_ID: 221 /* The subsequent handling of SCP_BL2 is platform specific */ 222 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 223 if (err) { 224 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 225 } 226 break; 227 #endif 228 default: 229 /* Do nothing in default case */ 230 break; 231 } 232 233 return err; 234 } 235 236 /******************************************************************************* 237 * This function can be used by the platforms to update/use image 238 * information for given `image_id`. 239 ******************************************************************************/ 240 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 241 { 242 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 243 /* For Secure Partitions we don't need post processing */ 244 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 245 (image_id < MAX_NUMBER_IDS)) { 246 return 0; 247 } 248 #endif 249 return arm_bl2_handle_post_image_load(image_id); 250 } 251 252 int bl2_plat_handle_post_image_load(unsigned int image_id) 253 { 254 return arm_bl2_plat_handle_post_image_load(image_id); 255 } 256 257 #if MEASURED_BOOT 258 /* Read TCG_DIGEST_SIZE bytes of BL2 hash data */ 259 void bl2_plat_get_hash(void *data) 260 { 261 arm_bl2_get_hash(data); 262 } 263 #endif 264