1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/debugfs.h> 15 #include <lib/extensions/ras.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 /* 23 * Placeholder variables for copying the arguments that have been passed to 24 * BL31 from BL2. 25 */ 26 static entry_point_info_t bl32_image_ep_info; 27 static entry_point_info_t bl33_image_ep_info; 28 #if ENABLE_RME 29 static entry_point_info_t rmm_image_ep_info; 30 #endif 31 32 #if !RESET_TO_BL31 33 /* 34 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 35 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 36 */ 37 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 38 #endif 39 40 /* Weak definitions may be overridden in specific ARM standard platform */ 41 #pragma weak bl31_early_platform_setup2 42 #pragma weak bl31_platform_setup 43 #pragma weak bl31_plat_arch_setup 44 #pragma weak bl31_plat_get_next_image_ep_info 45 46 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 47 BL31_START, \ 48 BL31_END - BL31_START, \ 49 MT_MEMORY | MT_RW | EL3_PAS) 50 #if RECLAIM_INIT_CODE 51 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 52 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 53 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED); 54 55 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 56 ~(PAGE_SIZE - 1)) 57 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \ 58 ~(PAGE_SIZE - 1)) 59 60 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 61 BL_INIT_CODE_BASE, \ 62 BL_INIT_CODE_END \ 63 - BL_INIT_CODE_BASE, \ 64 MT_CODE | EL3_PAS) 65 #endif 66 67 #if SEPARATE_NOBITS_REGION 68 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 69 BL31_NOBITS_BASE, \ 70 BL31_NOBITS_LIMIT \ 71 - BL31_NOBITS_BASE, \ 72 MT_MEMORY | MT_RW | EL3_PAS) 73 74 #endif 75 /******************************************************************************* 76 * Return a pointer to the 'entry_point_info' structure of the next image for the 77 * security state specified. BL33 corresponds to the non-secure image type 78 * while BL32 corresponds to the secure image type. A NULL pointer is returned 79 * if the image does not exist. 80 ******************************************************************************/ 81 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 82 { 83 entry_point_info_t *next_image_info; 84 85 assert(sec_state_is_valid(type)); 86 if (type == NON_SECURE) { 87 next_image_info = &bl33_image_ep_info; 88 } 89 #if ENABLE_RME 90 else if (type == REALM) { 91 next_image_info = &rmm_image_ep_info; 92 } 93 #endif 94 else { 95 next_image_info = &bl32_image_ep_info; 96 } 97 98 /* 99 * None of the images on the ARM development platforms can have 0x0 100 * as the entrypoint 101 */ 102 if (next_image_info->pc) 103 return next_image_info; 104 else 105 return NULL; 106 } 107 108 /******************************************************************************* 109 * Perform any BL31 early platform setup common to ARM standard platforms. 110 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 111 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 112 * done before the MMU is initialized so that the memory layout can be used 113 * while creating page tables. BL2 has flushed this information to memory, so 114 * we are guaranteed to pick up good data. 115 ******************************************************************************/ 116 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 117 uintptr_t hw_config, void *plat_params_from_bl2) 118 { 119 /* Initialize the console to provide early debug support */ 120 arm_console_boot_init(); 121 122 #if RESET_TO_BL31 123 /* There are no parameters from BL2 if BL31 is a reset vector */ 124 assert(from_bl2 == NULL); 125 assert(plat_params_from_bl2 == NULL); 126 127 # ifdef BL32_BASE 128 /* Populate entry point information for BL32 */ 129 SET_PARAM_HEAD(&bl32_image_ep_info, 130 PARAM_EP, 131 VERSION_1, 132 0); 133 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 134 bl32_image_ep_info.pc = BL32_BASE; 135 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 136 137 #if defined(SPD_spmd) 138 /* SPM (hafnium in secure world) expects SPM Core manifest base address 139 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 140 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 141 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 142 * keep it in the last page. 143 */ 144 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 145 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 146 #endif 147 148 # endif /* BL32_BASE */ 149 150 /* Populate entry point information for BL33 */ 151 SET_PARAM_HEAD(&bl33_image_ep_info, 152 PARAM_EP, 153 VERSION_1, 154 0); 155 /* 156 * Tell BL31 where the non-trusted software image 157 * is located and the entry state information 158 */ 159 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 160 161 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 162 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 163 164 #else /* RESET_TO_BL31 */ 165 166 /* 167 * In debug builds, we pass a special value in 'plat_params_from_bl2' 168 * to verify platform parameters from BL2 to BL31. 169 * In release builds, it's not used. 170 */ 171 assert(((unsigned long long)plat_params_from_bl2) == 172 ARM_BL31_PLAT_PARAM_VAL); 173 174 /* 175 * Check params passed from BL2 should not be NULL, 176 */ 177 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 178 assert(params_from_bl2 != NULL); 179 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 180 assert(params_from_bl2->h.version >= VERSION_2); 181 182 bl_params_node_t *bl_params = params_from_bl2->head; 183 184 /* 185 * Copy BL33, BL32 and RMM (if present), entry point information. 186 * They are stored in Secure RAM, in BL2's address space. 187 */ 188 while (bl_params != NULL) { 189 if (bl_params->image_id == BL32_IMAGE_ID) { 190 bl32_image_ep_info = *bl_params->ep_info; 191 } 192 #if ENABLE_RME 193 else if (bl_params->image_id == RMM_IMAGE_ID) { 194 rmm_image_ep_info = *bl_params->ep_info; 195 } 196 #endif 197 else if (bl_params->image_id == BL33_IMAGE_ID) { 198 bl33_image_ep_info = *bl_params->ep_info; 199 } 200 201 bl_params = bl_params->next_params_info; 202 } 203 204 if (bl33_image_ep_info.pc == 0U) 205 panic(); 206 #if ENABLE_RME 207 if (rmm_image_ep_info.pc == 0U) 208 panic(); 209 #endif 210 #endif /* RESET_TO_BL31 */ 211 212 # if ARM_LINUX_KERNEL_AS_BL33 213 /* 214 * According to the file ``Documentation/arm64/booting.txt`` of the 215 * Linux kernel tree, Linux expects the physical address of the device 216 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 217 * must be 0. 218 */ 219 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 220 bl33_image_ep_info.args.arg1 = 0U; 221 bl33_image_ep_info.args.arg2 = 0U; 222 bl33_image_ep_info.args.arg3 = 0U; 223 # endif 224 225 #if defined(SPD_spmd) 226 /* 227 * Hafnium in normal world expects its manifest address in x0, In CI 228 * configuration manifest is preloaded at 0x80000000(start of DRAM). 229 */ 230 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; 231 #endif 232 } 233 234 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 235 u_register_t arg2, u_register_t arg3) 236 { 237 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 238 239 /* 240 * Initialize Interconnect for this cluster during cold boot. 241 * No need for locks as no other CPU is active. 242 */ 243 plat_arm_interconnect_init(); 244 245 /* 246 * Enable Interconnect coherency for the primary CPU's cluster. 247 * Earlier bootloader stages might already do this (e.g. Trusted 248 * Firmware's BL1 does it) but we can't assume so. There is no harm in 249 * executing this code twice anyway. 250 * Platform specific PSCI code will enable coherency for other 251 * clusters. 252 */ 253 plat_arm_interconnect_enter_coherency(); 254 } 255 256 /******************************************************************************* 257 * Perform any BL31 platform setup common to ARM standard platforms 258 ******************************************************************************/ 259 void arm_bl31_platform_setup(void) 260 { 261 /* Initialize the GIC driver, cpu and distributor interfaces */ 262 plat_arm_gic_driver_init(); 263 plat_arm_gic_init(); 264 265 #if RESET_TO_BL31 266 /* 267 * Do initial security configuration to allow DRAM/device access 268 * (if earlier BL has not already done so). 269 */ 270 plat_arm_security_setup(); 271 272 #if defined(PLAT_ARM_MEM_PROT_ADDR) 273 arm_nor_psci_do_dyn_mem_protect(); 274 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 275 276 #endif /* RESET_TO_BL31 */ 277 278 /* Enable and initialize the System level generic timer */ 279 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 280 CNTCR_FCREQ(0U) | CNTCR_EN); 281 282 /* Allow access to the System counter timer module */ 283 arm_configure_sys_timer(); 284 285 /* Initialize power controller before setting up topology */ 286 plat_arm_pwrc_setup(); 287 288 #if RAS_EXTENSION 289 ras_init(); 290 #endif 291 292 #if USE_DEBUGFS 293 debugfs_init(); 294 #endif /* USE_DEBUGFS */ 295 } 296 297 /******************************************************************************* 298 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 299 * standard platforms 300 * Perform BL31 platform setup 301 ******************************************************************************/ 302 void arm_bl31_plat_runtime_setup(void) 303 { 304 console_switch_state(CONSOLE_FLAG_RUNTIME); 305 306 /* Initialize the runtime console */ 307 arm_console_runtime_init(); 308 309 #if RECLAIM_INIT_CODE 310 arm_free_init_memory(); 311 #endif 312 313 #if PLAT_RO_XLAT_TABLES 314 arm_xlat_make_tables_readonly(); 315 #endif 316 } 317 318 #if RECLAIM_INIT_CODE 319 /* 320 * Make memory for image boot time code RW to reclaim it as stack for the 321 * secondary cores, or RO where it cannot be reclaimed: 322 * 323 * |-------- INIT SECTION --------| 324 * ----------------------------------------- 325 * | CORE 0 | CORE 1 | CORE 2 | EXTRA | 326 * | STACK | STACK | STACK | SPACE | 327 * ----------------------------------------- 328 * <-------------------> <------> 329 * MAKE RW AND XN MAKE 330 * FOR STACKS RO AND XN 331 */ 332 void arm_free_init_memory(void) 333 { 334 int ret = 0; 335 336 if (BL_STACKS_END < BL_INIT_CODE_END) { 337 /* Reclaim some of the init section as stack if possible. */ 338 if (BL_INIT_CODE_BASE < BL_STACKS_END) { 339 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 340 BL_STACKS_END - BL_INIT_CODE_BASE, 341 MT_RW_DATA); 342 } 343 /* Make the rest of the init section read-only. */ 344 ret |= xlat_change_mem_attributes(BL_STACKS_END, 345 BL_INIT_CODE_END - BL_STACKS_END, 346 MT_RO_DATA); 347 } else { 348 /* The stacks cover the init section, so reclaim it all. */ 349 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 350 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 351 MT_RW_DATA); 352 } 353 354 if (ret != 0) { 355 ERROR("Could not reclaim initialization code"); 356 panic(); 357 } 358 } 359 #endif 360 361 void __init bl31_platform_setup(void) 362 { 363 arm_bl31_platform_setup(); 364 } 365 366 void bl31_plat_runtime_setup(void) 367 { 368 arm_bl31_plat_runtime_setup(); 369 } 370 371 /******************************************************************************* 372 * Perform the very early platform specific architectural setup shared between 373 * ARM standard platforms. This only does basic initialization. Later 374 * architectural setup (bl31_arch_setup()) does not do anything platform 375 * specific. 376 ******************************************************************************/ 377 void __init arm_bl31_plat_arch_setup(void) 378 { 379 const mmap_region_t bl_regions[] = { 380 MAP_BL31_TOTAL, 381 #if RECLAIM_INIT_CODE 382 MAP_BL_INIT_CODE, 383 #endif 384 #if SEPARATE_NOBITS_REGION 385 MAP_BL31_NOBITS, 386 #endif 387 ARM_MAP_BL_RO, 388 #if USE_ROMLIB 389 ARM_MAP_ROMLIB_CODE, 390 ARM_MAP_ROMLIB_DATA, 391 #endif 392 #if USE_COHERENT_MEM 393 ARM_MAP_BL_COHERENT_RAM, 394 #endif 395 {0} 396 }; 397 398 setup_page_tables(bl_regions, plat_arm_get_mmap()); 399 400 enable_mmu_el3(0); 401 402 arm_setup_romlib(); 403 } 404 405 void __init bl31_plat_arch_setup(void) 406 { 407 arm_bl31_plat_arch_setup(); 408 } 409