1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/debugfs.h> 15 #include <lib/extensions/ras.h> 16 #include <lib/gpt/gpt.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_compat.h> 19 #include <plat/arm/common/arm_pas_def.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 #include <platform_def.h> 23 24 /* 25 * Placeholder variables for copying the arguments that have been passed to 26 * BL31 from BL2. 27 */ 28 static entry_point_info_t bl32_image_ep_info; 29 static entry_point_info_t bl33_image_ep_info; 30 #if ENABLE_RME 31 static entry_point_info_t rmm_image_ep_info; 32 #endif 33 34 #if !RESET_TO_BL31 35 /* 36 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 37 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 38 */ 39 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 40 #endif 41 42 /* Weak definitions may be overridden in specific ARM standard platform */ 43 #pragma weak bl31_early_platform_setup2 44 #pragma weak bl31_platform_setup 45 #pragma weak bl31_plat_arch_setup 46 #pragma weak bl31_plat_get_next_image_ep_info 47 48 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 49 BL31_START, \ 50 BL31_END - BL31_START, \ 51 MT_MEMORY | MT_RW | EL3_PAS) 52 #if RECLAIM_INIT_CODE 53 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 54 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 55 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED); 56 57 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 58 ~(PAGE_SIZE - 1)) 59 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \ 60 ~(PAGE_SIZE - 1)) 61 62 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 63 BL_INIT_CODE_BASE, \ 64 BL_INIT_CODE_END \ 65 - BL_INIT_CODE_BASE, \ 66 MT_CODE | EL3_PAS) 67 #endif 68 69 #if SEPARATE_NOBITS_REGION 70 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 71 BL31_NOBITS_BASE, \ 72 BL31_NOBITS_LIMIT \ 73 - BL31_NOBITS_BASE, \ 74 MT_MEMORY | MT_RW | EL3_PAS) 75 76 #endif 77 /******************************************************************************* 78 * Return a pointer to the 'entry_point_info' structure of the next image for the 79 * security state specified. BL33 corresponds to the non-secure image type 80 * while BL32 corresponds to the secure image type. A NULL pointer is returned 81 * if the image does not exist. 82 ******************************************************************************/ 83 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 84 { 85 entry_point_info_t *next_image_info; 86 87 assert(sec_state_is_valid(type)); 88 if (type == NON_SECURE) { 89 next_image_info = &bl33_image_ep_info; 90 } 91 #if ENABLE_RME 92 else if (type == REALM) { 93 next_image_info = &rmm_image_ep_info; 94 } 95 #endif 96 else { 97 next_image_info = &bl32_image_ep_info; 98 } 99 100 /* 101 * None of the images on the ARM development platforms can have 0x0 102 * as the entrypoint 103 */ 104 if (next_image_info->pc) 105 return next_image_info; 106 else 107 return NULL; 108 } 109 110 /******************************************************************************* 111 * Perform any BL31 early platform setup common to ARM standard platforms. 112 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 113 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 114 * done before the MMU is initialized so that the memory layout can be used 115 * while creating page tables. BL2 has flushed this information to memory, so 116 * we are guaranteed to pick up good data. 117 ******************************************************************************/ 118 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 119 uintptr_t hw_config, void *plat_params_from_bl2) 120 { 121 /* Initialize the console to provide early debug support */ 122 arm_console_boot_init(); 123 124 #if RESET_TO_BL31 125 /* There are no parameters from BL2 if BL31 is a reset vector */ 126 assert(from_bl2 == NULL); 127 assert(plat_params_from_bl2 == NULL); 128 129 # ifdef BL32_BASE 130 /* Populate entry point information for BL32 */ 131 SET_PARAM_HEAD(&bl32_image_ep_info, 132 PARAM_EP, 133 VERSION_1, 134 0); 135 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 136 bl32_image_ep_info.pc = BL32_BASE; 137 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 138 139 #if defined(SPD_spmd) 140 /* SPM (hafnium in secure world) expects SPM Core manifest base address 141 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 142 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 143 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 144 * keep it in the last page. 145 */ 146 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 147 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 148 #endif 149 150 # endif /* BL32_BASE */ 151 152 /* Populate entry point information for BL33 */ 153 SET_PARAM_HEAD(&bl33_image_ep_info, 154 PARAM_EP, 155 VERSION_1, 156 0); 157 /* 158 * Tell BL31 where the non-trusted software image 159 * is located and the entry state information 160 */ 161 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 162 163 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 164 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 165 166 #else /* RESET_TO_BL31 */ 167 168 /* 169 * In debug builds, we pass a special value in 'plat_params_from_bl2' 170 * to verify platform parameters from BL2 to BL31. 171 * In release builds, it's not used. 172 */ 173 assert(((unsigned long long)plat_params_from_bl2) == 174 ARM_BL31_PLAT_PARAM_VAL); 175 176 /* 177 * Check params passed from BL2 should not be NULL, 178 */ 179 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 180 assert(params_from_bl2 != NULL); 181 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 182 assert(params_from_bl2->h.version >= VERSION_2); 183 184 bl_params_node_t *bl_params = params_from_bl2->head; 185 186 /* 187 * Copy BL33, BL32 and RMM (if present), entry point information. 188 * They are stored in Secure RAM, in BL2's address space. 189 */ 190 while (bl_params != NULL) { 191 if (bl_params->image_id == BL32_IMAGE_ID) { 192 bl32_image_ep_info = *bl_params->ep_info; 193 } 194 #if ENABLE_RME 195 else if (bl_params->image_id == RMM_IMAGE_ID) { 196 rmm_image_ep_info = *bl_params->ep_info; 197 } 198 #endif 199 else if (bl_params->image_id == BL33_IMAGE_ID) { 200 bl33_image_ep_info = *bl_params->ep_info; 201 } 202 203 bl_params = bl_params->next_params_info; 204 } 205 206 if (bl33_image_ep_info.pc == 0U) 207 panic(); 208 #if ENABLE_RME 209 if (rmm_image_ep_info.pc == 0U) 210 panic(); 211 #endif 212 #endif /* RESET_TO_BL31 */ 213 214 # if ARM_LINUX_KERNEL_AS_BL33 215 /* 216 * According to the file ``Documentation/arm64/booting.txt`` of the 217 * Linux kernel tree, Linux expects the physical address of the device 218 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 219 * must be 0. 220 */ 221 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 222 bl33_image_ep_info.args.arg1 = 0U; 223 bl33_image_ep_info.args.arg2 = 0U; 224 bl33_image_ep_info.args.arg3 = 0U; 225 # endif 226 227 #if defined(SPD_spmd) 228 /* 229 * Hafnium in normal world expects its manifest address in x0, In CI 230 * configuration manifest is preloaded at 0x80000000(start of DRAM). 231 */ 232 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; 233 #endif 234 235 #if ENABLE_RME 236 /* 237 * Initialise Granule Protection library and enable GPC 238 * for the primary processor. The tables were initialised 239 * in BL2, so there is no need to provide any PAS here. 240 */ 241 gpt_init_params_t gpt_params = { 242 PLATFORM_PGS, 243 PLATFORM_PPS, 244 PLATFORM_L0GPTSZ, 245 NULL, 246 0U, 247 ARM_L0_GPT_ADDR_BASE, ARM_L0_GPT_SIZE, 248 ARM_L1_GPT_ADDR_BASE, ARM_L1_GPT_SIZE 249 }; 250 251 /* Initialise the global granule tables. */ 252 if (gpt_init(&gpt_params) < 0) { 253 panic(); 254 } 255 #endif /* ENABLE_RME */ 256 } 257 258 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 259 u_register_t arg2, u_register_t arg3) 260 { 261 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 262 263 /* 264 * Initialize Interconnect for this cluster during cold boot. 265 * No need for locks as no other CPU is active. 266 */ 267 plat_arm_interconnect_init(); 268 269 /* 270 * Enable Interconnect coherency for the primary CPU's cluster. 271 * Earlier bootloader stages might already do this (e.g. Trusted 272 * Firmware's BL1 does it) but we can't assume so. There is no harm in 273 * executing this code twice anyway. 274 * Platform specific PSCI code will enable coherency for other 275 * clusters. 276 */ 277 plat_arm_interconnect_enter_coherency(); 278 } 279 280 /******************************************************************************* 281 * Perform any BL31 platform setup common to ARM standard platforms 282 ******************************************************************************/ 283 void arm_bl31_platform_setup(void) 284 { 285 /* Initialize the GIC driver, cpu and distributor interfaces */ 286 plat_arm_gic_driver_init(); 287 plat_arm_gic_init(); 288 289 #if RESET_TO_BL31 290 /* 291 * Do initial security configuration to allow DRAM/device access 292 * (if earlier BL has not already done so). 293 */ 294 plat_arm_security_setup(); 295 296 #if defined(PLAT_ARM_MEM_PROT_ADDR) 297 arm_nor_psci_do_dyn_mem_protect(); 298 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 299 300 #endif /* RESET_TO_BL31 */ 301 302 /* Enable and initialize the System level generic timer */ 303 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 304 CNTCR_FCREQ(0U) | CNTCR_EN); 305 306 /* Allow access to the System counter timer module */ 307 arm_configure_sys_timer(); 308 309 /* Initialize power controller before setting up topology */ 310 plat_arm_pwrc_setup(); 311 312 #if RAS_EXTENSION 313 ras_init(); 314 #endif 315 316 #if USE_DEBUGFS 317 debugfs_init(); 318 #endif /* USE_DEBUGFS */ 319 } 320 321 /******************************************************************************* 322 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 323 * standard platforms 324 * Perform BL31 platform setup 325 ******************************************************************************/ 326 void arm_bl31_plat_runtime_setup(void) 327 { 328 console_switch_state(CONSOLE_FLAG_RUNTIME); 329 330 /* Initialize the runtime console */ 331 arm_console_runtime_init(); 332 333 #if RECLAIM_INIT_CODE 334 arm_free_init_memory(); 335 #endif 336 337 #if PLAT_RO_XLAT_TABLES 338 arm_xlat_make_tables_readonly(); 339 #endif 340 } 341 342 #if RECLAIM_INIT_CODE 343 /* 344 * Make memory for image boot time code RW to reclaim it as stack for the 345 * secondary cores, or RO where it cannot be reclaimed: 346 * 347 * |-------- INIT SECTION --------| 348 * ----------------------------------------- 349 * | CORE 0 | CORE 1 | CORE 2 | EXTRA | 350 * | STACK | STACK | STACK | SPACE | 351 * ----------------------------------------- 352 * <-------------------> <------> 353 * MAKE RW AND XN MAKE 354 * FOR STACKS RO AND XN 355 */ 356 void arm_free_init_memory(void) 357 { 358 int ret = 0; 359 360 if (BL_STACKS_END < BL_INIT_CODE_END) { 361 /* Reclaim some of the init section as stack if possible. */ 362 if (BL_INIT_CODE_BASE < BL_STACKS_END) { 363 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 364 BL_STACKS_END - BL_INIT_CODE_BASE, 365 MT_RW_DATA); 366 } 367 /* Make the rest of the init section read-only. */ 368 ret |= xlat_change_mem_attributes(BL_STACKS_END, 369 BL_INIT_CODE_END - BL_STACKS_END, 370 MT_RO_DATA); 371 } else { 372 /* The stacks cover the init section, so reclaim it all. */ 373 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 374 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 375 MT_RW_DATA); 376 } 377 378 if (ret != 0) { 379 ERROR("Could not reclaim initialization code"); 380 panic(); 381 } 382 } 383 #endif 384 385 void __init bl31_platform_setup(void) 386 { 387 arm_bl31_platform_setup(); 388 } 389 390 void bl31_plat_runtime_setup(void) 391 { 392 arm_bl31_plat_runtime_setup(); 393 } 394 395 /******************************************************************************* 396 * Perform the very early platform specific architectural setup shared between 397 * ARM standard platforms. This only does basic initialization. Later 398 * architectural setup (bl31_arch_setup()) does not do anything platform 399 * specific. 400 ******************************************************************************/ 401 void __init arm_bl31_plat_arch_setup(void) 402 { 403 const mmap_region_t bl_regions[] = { 404 MAP_BL31_TOTAL, 405 #if ENABLE_RME 406 ARM_MAP_L0_GPT_REGION, 407 #endif 408 #if RECLAIM_INIT_CODE 409 MAP_BL_INIT_CODE, 410 #endif 411 #if SEPARATE_NOBITS_REGION 412 MAP_BL31_NOBITS, 413 #endif 414 ARM_MAP_BL_RO, 415 #if USE_ROMLIB 416 ARM_MAP_ROMLIB_CODE, 417 ARM_MAP_ROMLIB_DATA, 418 #endif 419 #if USE_COHERENT_MEM 420 ARM_MAP_BL_COHERENT_RAM, 421 #endif 422 {0} 423 }; 424 425 setup_page_tables(bl_regions, plat_arm_get_mmap()); 426 427 enable_mmu_el3(0); 428 429 arm_setup_romlib(); 430 } 431 432 void __init bl31_plat_arch_setup(void) 433 { 434 arm_bl31_plat_arch_setup(); 435 } 436