1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/gpt/gpt.h> 22 #ifdef SPD_opteed 23 #include <lib/optee_utils.h> 24 #endif 25 #include <lib/utils.h> 26 #include <plat/arm/common/arm_pas_def.h> 27 #include <plat/arm/common/plat_arm.h> 28 #include <plat/common/platform.h> 29 30 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 31 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 32 33 /* Base address of fw_config received from BL1 */ 34 static uintptr_t config_base; 35 36 /* 37 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 38 * for `meminfo_t` data structure and fw_configs passed from BL1. 39 */ 40 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 41 42 /* Weak definitions may be overridden in specific ARM standard platform */ 43 #pragma weak bl2_early_platform_setup2 44 #pragma weak bl2_platform_setup 45 #pragma weak bl2_plat_arch_setup 46 #pragma weak bl2_plat_sec_mem_layout 47 #if MEASURED_BOOT 48 #pragma weak bl2_plat_get_hash 49 #endif 50 51 #if ENABLE_RME 52 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 53 bl2_tzram_layout.total_base, \ 54 bl2_tzram_layout.total_size, \ 55 MT_MEMORY | MT_RW | MT_ROOT) 56 #else 57 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 58 bl2_tzram_layout.total_base, \ 59 bl2_tzram_layout.total_size, \ 60 MT_MEMORY | MT_RW | MT_SECURE) 61 #endif /* ENABLE_RME */ 62 63 #pragma weak arm_bl2_plat_handle_post_image_load 64 65 /******************************************************************************* 66 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 67 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 68 * Copy it to a safe location before its reclaimed by later BL2 functionality. 69 ******************************************************************************/ 70 void arm_bl2_early_platform_setup(uintptr_t fw_config, 71 struct meminfo *mem_layout) 72 { 73 /* Initialize the console to provide early debug support */ 74 arm_console_boot_init(); 75 76 /* Setup the BL2 memory layout */ 77 bl2_tzram_layout = *mem_layout; 78 79 config_base = fw_config; 80 81 /* Initialise the IO layer and register platform IO devices */ 82 plat_arm_io_setup(); 83 84 /* Load partition table */ 85 #if ARM_GPT_SUPPORT 86 partition_init(GPT_IMAGE_ID); 87 #endif /* ARM_GPT_SUPPORT */ 88 89 } 90 91 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 92 { 93 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 94 95 generic_delay_timer_init(); 96 } 97 98 /* 99 * Perform BL2 preload setup. Currently we initialise the dynamic 100 * configuration here. 101 */ 102 void bl2_plat_preload_setup(void) 103 { 104 arm_bl2_dyn_cfg_init(); 105 106 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 107 /* Always use the FIP from bank 0 */ 108 arm_set_fip_addr(0U); 109 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 110 } 111 112 /* 113 * Perform ARM standard platform setup. 114 */ 115 void arm_bl2_platform_setup(void) 116 { 117 #if !ENABLE_RME 118 /* Initialize the secure environment */ 119 plat_arm_security_setup(); 120 #endif 121 122 #if defined(PLAT_ARM_MEM_PROT_ADDR) 123 arm_nor_psci_do_static_mem_protect(); 124 #endif 125 } 126 127 void bl2_platform_setup(void) 128 { 129 arm_bl2_platform_setup(); 130 } 131 132 #if ENABLE_RME 133 static void arm_bl2_plat_gpt_setup(void) 134 { 135 /* 136 * The GPT library might modify the gpt regions structure to optimize 137 * the layout, so the array cannot be constant. 138 */ 139 pas_region_t pas_regions[] = { 140 ARM_PAS_GPI_ANY, 141 ARM_PAS_KERNEL, 142 ARM_PAS_TZC, 143 ARM_PAS_REALM, 144 ARM_PAS_EL3_DRAM, 145 ARM_PAS_GPTS 146 }; 147 148 gpt_init_params_t gpt_params = { 149 PLATFORM_PGS, 150 PLATFORM_PPS, 151 PLATFORM_L0GPTSZ, 152 pas_regions, 153 (unsigned int)(sizeof(pas_regions)/sizeof(pas_region_t)), 154 ARM_L0_GPT_ADDR_BASE, ARM_L0_GPT_SIZE, 155 ARM_L1_GPT_ADDR_BASE, ARM_L1_GPT_SIZE 156 }; 157 158 /* Initialise the global granule tables */ 159 INFO("Enabling Granule Protection Checks\n"); 160 if (gpt_init(&gpt_params) < 0) { 161 panic(); 162 } 163 164 gpt_enable(); 165 } 166 #endif /* ENABLE_RME */ 167 168 /******************************************************************************* 169 * Perform the very early platform specific architectural setup here. 170 * When RME is enabled the secure environment is initialised before 171 * initialising and enabling Granule Protection. 172 * This function initialises the MMU in a quick and dirty way. 173 ******************************************************************************/ 174 void arm_bl2_plat_arch_setup(void) 175 { 176 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 177 /* 178 * Ensure ARM platforms don't use coherent memory in BL2 unless 179 * cryptocell integration is enabled. 180 */ 181 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 182 #endif 183 184 const mmap_region_t bl_regions[] = { 185 MAP_BL2_TOTAL, 186 ARM_MAP_BL_RO, 187 #if USE_ROMLIB 188 ARM_MAP_ROMLIB_CODE, 189 ARM_MAP_ROMLIB_DATA, 190 #endif 191 #if ARM_CRYPTOCELL_INTEG 192 ARM_MAP_BL_COHERENT_RAM, 193 #endif 194 ARM_MAP_BL_CONFIG_REGION, 195 #if ENABLE_RME 196 ARM_MAP_L0_GPT_REGION, 197 #endif 198 {0} 199 }; 200 201 #if ENABLE_RME 202 /* Initialise the secure environment */ 203 plat_arm_security_setup(); 204 205 /* Initialise and enable Granule Protection */ 206 arm_bl2_plat_gpt_setup(); 207 #endif 208 setup_page_tables(bl_regions, plat_arm_get_mmap()); 209 210 #ifdef __aarch64__ 211 #if ENABLE_RME 212 /* BL2 runs in EL3 when RME enabled. */ 213 assert(get_armv9_2_feat_rme_support() != 0U); 214 enable_mmu_el3(0); 215 #else 216 enable_mmu_el1(0); 217 #endif 218 #else 219 enable_mmu_svc_mon(0); 220 #endif 221 222 arm_setup_romlib(); 223 } 224 225 void bl2_plat_arch_setup(void) 226 { 227 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 228 229 arm_bl2_plat_arch_setup(); 230 231 /* Fill the properties struct with the info from the config dtb */ 232 fconf_populate("FW_CONFIG", config_base); 233 234 /* TB_FW_CONFIG was also loaded by BL1 */ 235 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 236 assert(tb_fw_config_info != NULL); 237 238 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 239 } 240 241 int arm_bl2_handle_post_image_load(unsigned int image_id) 242 { 243 int err = 0; 244 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 245 #ifdef SPD_opteed 246 bl_mem_params_node_t *pager_mem_params = NULL; 247 bl_mem_params_node_t *paged_mem_params = NULL; 248 #endif 249 assert(bl_mem_params != NULL); 250 251 switch (image_id) { 252 #ifdef __aarch64__ 253 case BL32_IMAGE_ID: 254 #ifdef SPD_opteed 255 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 256 assert(pager_mem_params); 257 258 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 259 assert(paged_mem_params); 260 261 err = parse_optee_header(&bl_mem_params->ep_info, 262 &pager_mem_params->image_info, 263 &paged_mem_params->image_info); 264 if (err != 0) { 265 WARN("OPTEE header parse error.\n"); 266 } 267 #endif 268 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 269 break; 270 #endif 271 272 case BL33_IMAGE_ID: 273 /* BL33 expects to receive the primary CPU MPID (through r0) */ 274 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 275 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 276 break; 277 278 #ifdef SCP_BL2_BASE 279 case SCP_BL2_IMAGE_ID: 280 /* The subsequent handling of SCP_BL2 is platform specific */ 281 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 282 if (err) { 283 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 284 } 285 break; 286 #endif 287 default: 288 /* Do nothing in default case */ 289 break; 290 } 291 292 return err; 293 } 294 295 /******************************************************************************* 296 * This function can be used by the platforms to update/use image 297 * information for given `image_id`. 298 ******************************************************************************/ 299 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 300 { 301 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 302 /* For Secure Partitions we don't need post processing */ 303 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 304 (image_id < MAX_NUMBER_IDS)) { 305 return 0; 306 } 307 #endif 308 return arm_bl2_handle_post_image_load(image_id); 309 } 310 311 int bl2_plat_handle_post_image_load(unsigned int image_id) 312 { 313 return arm_bl2_plat_handle_post_image_load(image_id); 314 } 315 316 #if MEASURED_BOOT 317 /* Read TCG_DIGEST_SIZE bytes of BL2 hash data */ 318 void bl2_plat_get_hash(void *data) 319 { 320 arm_bl2_get_hash(data); 321 } 322 #endif 323