feat(mt8188): add emi mpu protection for APU secure memory

Add emi mpu protection of APU secure memory.

Change-Id: I949cfce97565d8a313caae4ea41af60a171042a6
Signed-off-by: Chungying Lu <chungying.l

feat(mt8188): add emi mpu protection for APU secure memory

Add emi mpu protection of APU secure memory.

Change-Id: I949cfce97565d8a313caae4ea41af60a171042a6
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8188): add devapc setting of apusys rcx

Apusys rcx is a subsys in apusys, and it is a basic domain of APU and
it connects several components in APU.
The devapc control of apusys rcx is also i

feat(mt8188): add devapc setting of apusys rcx

Apusys rcx is a subsys in apusys, and it is a basic domain of APU and
it connects several components in APU.
The devapc control of apusys rcx is also inside APU and it can only be
set when APU is powered on.
Then apusys kernel driver will trigger rcx devapc init by ATF smc call.

Change-Id: If4249f22a08690b1e4f5aa5f0cbfb54ccacf90e1
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): add backup/restore function when power on/off

Add APU backup/restore function when power on/off.

Change-Id: Id0451bd12f402e1acabeb5c12266a2e01836e9dd
Signed-off-by: Chungying Lu <chun

feat(mt8188): add backup/restore function when power on/off

Add APU backup/restore function when power on/off.

Change-Id: Id0451bd12f402e1acabeb5c12266a2e01836e9dd
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mediatek): add APU bootup control smc call

Add APU bootup control smc call.
The steps of bootup flow:
1. set up APU config.
2. reset APU.
3. set up APU boot config.
4. boot APU.

Change

feat(mediatek): add APU bootup control smc call

Add APU bootup control smc call.
The steps of bootup flow:
1. set up APU config.
2. reset APU.
3. set up APU boot config.
4. boot APU.

Change-Id: I9e930070a64c7c4dcaa3a8b3d28b897823e9f53c
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8188): enable apusys mailbox mpu protect

Enable apusys mailbox mpu protect.

Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by:

feat(mt8188): enable apusys mailbox mpu protect

Enable apusys mailbox mpu protect.

Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): enable apusys domain remap

Enable apusys domain remap to protect no-protect memory.
- Remap request which from domain 5 to domain 14.
- Remap request which from domain 7 to domain

feat(mt8188): enable apusys domain remap

Enable apusys domain remap to protect no-protect memory.
- Remap request which from domain 5 to domain 14.
- Remap request which from domain 7 to domain 14.

Change-Id: Iccd188e3b8edbe916fa9767c841a844b66c6011f
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): add apusys ao devapc setting

Apusys ao devapc is a set of control registers inside APU, and it
controls the access permission of APU ao domain.
Moreover, apusys ao devapc must be set a

feat(mt8188): add apusys ao devapc setting

Apusys ao devapc is a set of control registers inside APU, and it
controls the access permission of APU ao domain.
Moreover, apusys ao devapc must be set after apusys power init, so
we need to place the drivers in TF-A instead of coreboot.

Change-Id: Ife849c32d4dd9dca15432d4b8a51753fde61b148
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

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feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB

Increase TZRAM_SIZE to 256KB for MT8188 APUSYS.

Change-Id: Iabe1a4aeb79ba23c3e963170a8eb9ce19f2925f3
Signed-off-by: Karl Li <karl.li@mediatek.c

feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB

Increase TZRAM_SIZE to 256KB for MT8188 APUSYS.

Change-Id: Iabe1a4aeb79ba23c3e963170a8eb9ce19f2925f3
Signed-off-by: Karl Li <karl.li@mediatek.com>

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refactor(fvp): nv ctr addr static helper function

Adding a static helper function plat_get_nv_ctr_addr() to be used by
both plat_set_nv_ctr() and plat_get_nv_ctr() to return the
non-volatile counter

refactor(fvp): nv ctr addr static helper function

Adding a static helper function plat_get_nv_ctr_addr() to be used by
both plat_set_nv_ctr() and plat_get_nv_ctr() to return the
non-volatile counter address stored in the platform.

Change-Id: I5124c19e4537bb369724aa0160cc55a3cb1ab7eb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "fix(fiptool): move juno plat_fiptool.mk" into integration

feat(qemu-sbsa): handle GIC base

QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marci

feat(qemu-sbsa): handle GIC base

QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I383919bd172acc8873292a0c5e4469651dc96fb9

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feat(qemu-sbsa): handle platform version

QEMU provides platform version information via DT. We want to use it
in firmware to handle differences between platform versions.

Signed-off-by: Marcin Jusz

feat(qemu-sbsa): handle platform version

QEMU provides platform version information via DT. We want to use it
in firmware to handle differences between platform versions.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I8def66dac9dd5d7ab0e459baa40e27a11b65f0ba

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Merge changes from topic "cot_cca_nvctr" into integration

* changes:
feat(fvp): mock support for CCA NV ctr
feat(auth): add CCA NV ctr to CCA CoT
feat(build): pass CCA NV ctr option to cert_cr

Merge changes from topic "cot_cca_nvctr" into integration

* changes:
feat(fvp): mock support for CCA NV ctr
feat(auth): add CCA NV ctr to CCA CoT
feat(build): pass CCA NV ctr option to cert_create
feat(cert-create): add new option for CCA NV ctr

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fix(sc7280): update pwr_domain_suspend

Change-Id: I0ee6598e9a9a01aea49e05307c68bde9993debba
Signed-off-by: Wing Li <wingers@google.com>

fix(fvp): update pwr_domain_suspend

Change-Id: Ied4063ac6e685368818b2296c2d1800f4b272b86
Signed-off-by: Wing Li <wingers@google.com>

Merge changes from topic "bk/errata_refactor" into integration

* changes:
feat(cpus): wrappers to propagate AArch32 errata info
feat(cpus): add a way to automatically report errata
feat(cpus):

Merge changes from topic "bk/errata_refactor" into integration

* changes:
feat(cpus): wrappers to propagate AArch32 errata info
feat(cpus): add a way to automatically report errata
feat(cpus): add a concise way to implement AArch64 errata
refactor(cpus): convert print_errata_status to C
refactor(cpus): rename errata_report.h to errata.h
refactor(cpus): move cpu_ops field defines to a header

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Merge "feat: define memory ranges for tc platform" into integration

fix(st): flush UART at the end of uart_read()

Add a flush to ensure that the programmer get time to read the last
command sent.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic1f718d

fix(st): flush UART at the end of uart_read()

Add a flush to ensure that the programmer get time to read the last
command sent.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic1f718d2754f27945f12c04563663b46274810a7

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fix(stm32mp1): use the BSEC nodes compatible for stm32mp13

Device tree alignment with kernel and latest binding for BSEC node:
the rev2.0 is used on STM32MP13x devices with the new compatible
compat

fix(stm32mp1): use the BSEC nodes compatible for stm32mp13

Device tree alignment with kernel and latest binding for BSEC node:
the rev2.0 is used on STM32MP13x devices with the new compatible
compatible = "st,stm32mp13-bsec".

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I76f86f2951eff4af91d22dfb926969fd842a36ce

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fix(stm32mp1): properly check PSCI functions return

The psci_get_pstate_* helpers return unsigned int values,
update the code accordingly. Remove the useless pstate variable.
This corrects MISRA C20

fix(stm32mp1): properly check PSCI functions return

The psci_get_pstate_* helpers return unsigned int values,
update the code accordingly. Remove the useless pstate variable.
This corrects MISRA C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean
type.

Change-Id: Idc7e756f4ba2bc0d66a327763013f77f86fe16b2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(cpus): convert print_errata_status to C

The function is called in a fully initialised C environment and calls
into other C functions. The Aarch differences are minimal and are hidden
by the

refactor(cpus): convert print_errata_status to C

The function is called in a fully initialised C environment and calls
into other C functions. The Aarch differences are minimal and are hidden
by the pre-existing headers. Converting it results into cleaner code
that is the same across both Aarch64 and Aarch32.

To avoid having to do very ugly pointer arithmetic, define a C struct
for the cpu_ops for both Aarch64 and Aarch32.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Idc07c4064e03143c88a4a0e2d10ceda70ba19a50

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refactor(cpus): rename errata_report.h to errata.h

The ERRATA_XXX macros, used in cpu_helpers.S, are necessary for the
check_errata_xxx family of functions. The CPU_REV should be used in the
cpu fil

refactor(cpus): rename errata_report.h to errata.h

The ERRATA_XXX macros, used in cpu_helpers.S, are necessary for the
check_errata_xxx family of functions. The CPU_REV should be used in the
cpu files but for whatever reason the values have been hard-coded so far
(at the cost of readability). It's evident this file is not strictly for
status reporting.

The new purpose of this file is to make it a one-stop-shop for all
things errata.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1ce22dd36df5aa0bcfc5f2772251f91af8703dfb

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Merge "fix(zynqmp): handling of type el3 interrrupts" into integration

feat(fvp): mock support for CCA NV ctr

AEM FVP does not have a third CCA NV counter so the
implementation will fake it by returning the Trusted
NV counter value when the caller requests the CCA NV
c

feat(fvp): mock support for CCA NV ctr

AEM FVP does not have a third CCA NV counter so the
implementation will fake it by returning the Trusted
NV counter value when the caller requests the CCA NV
counter. This allows us to use the CCA CoT on AEM FVP
nonetheless.

The FVP platform port now gets its own version of
plat_get_nv_ctr() as it now need to diverge from the
common implementation provided at the Arm development
platforms level.

Change-Id: I3258f837249a539d943d6d783406ba222bd4554e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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fix(build): include Cortex-A78AE cpu file for FVP

So far, the FVP platform.mk file did not include the corresponding file
for Cortex-A78AE, causing the FVP to hang when executing the
plat_reset_hand

fix(build): include Cortex-A78AE cpu file for FVP

So far, the FVP platform.mk file did not include the corresponding file
for Cortex-A78AE, causing the FVP to hang when executing the
plat_reset_handler function. The file is now included to address the
problem and to allow the new CI config for Cortex-A78AE to work
properly.

Change-Id: I8dd460831b354d8ca54841d5561df40ff193ee06
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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