1 /* 2 * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef APUSYS_RV_H 8 #define APUSYS_RV_H 9 10 #include <platform_def.h> 11 12 #define APU_SEC_FW_IOVA (0x200000UL) 13 14 /* APU_SCTRL_REVISER */ 15 #define UP_NORMAL_DOMAIN_NS (APU_REVISER + 0x0000) 16 #define UP_PRI_DOMAIN_NS (APU_REVISER + 0x0004) 17 #define UP_IOMMU_CTRL (APU_REVISER + 0x0008) 18 #define UP_CORE0_VABASE0 (APU_REVISER + 0x000c) 19 #define UP_CORE0_MVABASE0 (APU_REVISER + 0x0010) 20 #define UP_CORE0_VABASE1 (APU_REVISER + 0x0014) 21 #define UP_CORE0_MVABASE1 (APU_REVISER + 0x0018) 22 #define USERFW_CTXT (APU_REVISER + 0x1000) 23 #define SECUREFW_CTXT (APU_REVISER + 0x1004) 24 #define UP_NORMAL_DOMAIN (7) 25 #define UP_NORMAL_NS (1) 26 #define UP_PRI_DOMAIN (5) 27 #define UP_PRI_NS (1) 28 #define UP_DOMAIN_SHIFT (0) 29 #define UP_NS_SHIFT (4) 30 #define MMU_EN BIT(0) 31 #define MMU_CTRL BIT(1) 32 #define MMU_CTRL_LOCK BIT(2) 33 #define VLD BIT(0) 34 #define PARTIAL_ENABLE BIT(1) 35 #define THREAD_NUM_PRI (1) 36 #define THREAD_NUM_NORMAL (0) 37 #define THREAD_NUM_SHIFT (2) 38 #define VASIZE_1MB BIT(0) 39 #define CFG_4GB_SEL_EN BIT(2) 40 #define CFG_4GB_SEL (0) 41 #define MVA_34BIT_SHIFT (2) 42 43 /* APU_MD32_SYSCTRL */ 44 #define MD32_SYS_CTRL (APU_MD32_SYSCTRL + 0x0000) 45 #define MD32_CLK_CTRL (APU_MD32_SYSCTRL + 0x00b8) 46 #define UP_WAKE_HOST_MASK0 (APU_MD32_SYSCTRL + 0x00bc) 47 #define UP_WAKE_HOST_MASK1 (APU_MD32_SYSCTRL + 0x00c0) 48 #define MD32_SYS_CTRL_RST (0) 49 #define MD32_G2B_CG_EN BIT(11) 50 #define MD32_DBG_EN BIT(10) 51 #define MD32_DM_AWUSER_IOMMU_EN BIT(9) 52 #define MD32_DM_ARUSER_IOMMU_EN BIT(7) 53 #define MD32_PM_AWUSER_IOMMU_EN BIT(5) 54 #define MD32_PM_ARUSER_IOMMU_EN BIT(3) 55 #define MD32_SOFT_RSTN BIT(0) 56 #define MD32_CLK_EN (1) 57 #define WDT_IRQ_EN BIT(0) 58 #define MBOX0_IRQ_EN BIT(21) 59 #define MBOX1_IRQ_EN BIT(22) 60 #define MBOX2_IRQ_EN BIT(23) 61 #define RESET_DEALY_US (10) 62 63 /* APU_AO_CTRL */ 64 #define MD32_PRE_DEFINE (APU_AO_CTRL + 0x0000) 65 #define MD32_BOOT_CTRL (APU_AO_CTRL + 0x0004) 66 #define MD32_RUNSTALL (APU_AO_CTRL + 0x0008) 67 #define PREDEFINE_NON_CACHE (0) 68 #define PREDEFINE_TCM (1) 69 #define PREDEFINE_CACHE (2) 70 #define PREDEFINE_CACHE_TCM (3) 71 #define PREDEF_1G_OFS (0) 72 #define PREDEF_2G_OFS (2) 73 #define PREDEF_3G_OFS (4) 74 #define PREDEF_4G_OFS (6) 75 #define MD32_RUN (0) 76 #define MD32_STALL (1) 77 78 /* APU_MD32_WDT */ 79 #define WDT_INT (APU_MD32_WDT + 0x0) 80 #define WDT_INT_W1C (1) 81 82 /* APU MBOX */ 83 #define MBOX_FUNC_CFG (0xb0) 84 #define MBOX_DOMAIN_CFG (0xe0) 85 #define MBOX_CTRL_LOCK BIT(0) 86 #define MBOX_NO_MPU_SHIFT (16) 87 #define MBOX_RX_NS_SHIFT (16) 88 #define MBOX_RX_DOMAIN_SHIFT (17) 89 #define MBOX_TX_NS_SHIFT (24) 90 #define MBOX_TX_DOMAIN_SHIFT (25) 91 #define MBOX_SIZE (0x100) 92 #define MBOX_NUM (8) 93 94 #define APU_MBOX(i) (((i) < MBOX_NUM) ? (APU_MBOX0 + MBOX_SIZE * (i)) : \ 95 (APU_MBOX1 + MBOX_SIZE * ((i) - MBOX_NUM))) 96 #define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG) 97 #define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG) 98 99 void apusys_rv_mbox_mpu_init(void); 100 int apusys_kernel_apusys_rv_setup_reviser(void); 101 int apusys_kernel_apusys_rv_reset_mp(void); 102 int apusys_kernel_apusys_rv_setup_boot(void); 103 int apusys_kernel_apusys_rv_start_mp(void); 104 int apusys_kernel_apusys_rv_stop_mp(void); 105 106 #endif /* APUSYS_RV_H */ 107