fix(rcar3): add missing image_base/size assignment to BL33 image loading path

Align BL33 image loading behavior in BL2 with BL3x image
loading behavior. BL31/BL32 image load already assigns
bl_mem_p

fix(rcar3): add missing image_base/size assignment to BL33 image loading path

Align BL33 image loading behavior in BL2 with BL3x image
loading behavior. BL31/BL32 image load already assigns
bl_mem_params->image_info.image_base and
bl_mem_params->image_info.image_size, but this assignment
is missing for BL33 image load.

This assignment is essential after retrieving the destination
address and size via rcar_get_dest_addr_from_cert(), so that
the parameters are passed correctly to the next stage. Without
this assignment, the BL33 image might not be loaded or validated
properly.

This change is not considered a vulnerability fix, but rather
a correction to ensure consistency and completeness in the BL2
image load logic.

Fixes: 4f7e0fa38fdb ("fix(rcar3): fix load address range check")
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Commit message update
Change-Id: I3c7c70f7f8d64b53e8c0f5ed61c71031b99fcde0

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feat(rdaspen): add DSU support

- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the

feat(rdaspen): add DSU support

- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the DSU-120AE TRM.
- Enable the `PRESERVE_DSU_PMU_REGS` flag to save and restore DSU
cluster PMU registers across cluster power cycles.

Change-Id: I7f820981cd164a689324a525b506c2979bddb572
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): enable tbb on rd-aspen platform

Enable Trusted board boot on RD-Aspen platform.

Included the non-volatile(NV) memory region, to
ensure rollback protection.

Added Mbed TLS library in

feat(rdaspen): enable tbb on rd-aspen platform

Enable Trusted board boot on RD-Aspen platform.

Included the non-volatile(NV) memory region, to
ensure rollback protection.

Added Mbed TLS library initialization for MbedTLS
library.

Change-Id: I7940952c152b0243a91b38804cf16d3050ec2d4b
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(rdaspen): add BL31 for RD-Aspen platform

Implement BL31 for RD-Aspen platform.

* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL ima

feat(rdaspen): add BL31 for RD-Aspen platform

Implement BL31 for RD-Aspen platform.

* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL image information that gets
used by BL2 to load the images

Change-Id: I5f389c4a6ef9bc106b3b29c9aecbd890d91d99b3
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>

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feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* C

feat(rdaspen): introduce Arm RD-Aspen platform

Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree

This platform contains:
* Cortex-A720AE, Armv9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 512 KB is reserved for TF-A
* 4GiB of DRAM in two partitions (extensible)

It also adds:
* FW_CONFIG and HW_CONFIG device trees

Change-Id: I4ba3e4bf1fed8f3640f7eda815607b0a5cab9500
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>

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feat(arm): implement arm platform GPT logging

The arm platform specific implementation of
logging corrupted primary GPT.

Change-Id: I73127668bcbf80e8fd2556da582fdcfc9ff9d524
Signed-off-by: Xialin L

feat(arm): implement arm platform GPT logging

The arm platform specific implementation of
logging corrupted primary GPT.

Change-Id: I73127668bcbf80e8fd2556da582fdcfc9ff9d524
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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feat(guid-partition): platform hook to log corrupted GPT

Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information

feat(guid-partition): platform hook to log corrupted GPT

Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information

Change-Id: Ie1af7eb6d97ec76f3f6d1cffad292782bdedda21
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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feat(fvp): add stub implementation for plat_lfa_notify_activate()

Introduce a stub for plat_lfa_notify_activate() in the FVP platform
code. This provides a placeholder implementation that always ret

feat(fvp): add stub implementation for plat_lfa_notify_activate()

Introduce a stub for plat_lfa_notify_activate() in the FVP platform
code. This provides a placeholder implementation that always returns
success as currently no notification is required.

Change-Id: I0e0813327af4f55e0aef12bd80a472d103ea317d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(intel): configure SCR1 for 32/16 non-secure SMRs and context banks

Update SCR1 register (0xFA000004) programming to:
- Set NSNUMSMRGO[14:8] = 0x20 to allocate 32 Stream Mapping Register
groups

fix(intel): configure SCR1 for 32/16 non-secure SMRs and context banks

Update SCR1 register (0xFA000004) programming to:
- Set NSNUMSMRGO[14:8] = 0x20 to allocate 32 Stream Mapping Register
groups for non-secure context.
- Set NSNUMCBO[5:0] = 0x10 to allocate 16 Context Banks for non-secure
context.

This change aligns with the requirement for SDM SMMU AFRL in Linux to
use 32 Context Banks. Secure and non-secure resources are now balanced,
with indices 0–31 reserved for non-secure and the rest for secure.

Change-Id: I6466a36278040d95b877f66a3800f13339d13bc8
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update the AES GCM/GCM_GHASH modes return data size

On the Agilex5 platform, in FCS AES method if block mode is
GCM/GCM_GHASH mode then the data size written to the destination
buffer is

fix(intel): update the AES GCM/GCM_GHASH modes return data size

On the Agilex5 platform, in FCS AES method if block mode is
GCM/GCM_GHASH mode then the data size written to the destination
buffer is at index[7] instead of [3] as in other cases.

Change-Id: Ide664f594ea63aaee7f74d21e8e2986de48e94a2
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): undo setting USB 3.1 reset pulse bit in BL2

During testing of USB 3.1 in FreeRTOS, it is reported, setting
the reset pulse override bit is affecting the enumeration of
USB devices attach

fix(intel): undo setting USB 3.1 reset pulse bit in BL2

During testing of USB 3.1 in FreeRTOS, it is reported, setting
the reset pulse override bit is affecting the enumeration of
USB devices attached to the USB 3.1 controller. Hence,
reverting the bit change to its default state.

Change-Id: I5746a7ff6b579c39416a462ebef6696f4aa57051
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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refactor(fvp): always build RAS files

Their processing introduces a circular dependency with the
initialization of ENABLE_FEAT_RAS when it's not set on the commandline.
However, building them when E

refactor(fvp): always build RAS files

Their processing introduces a circular dependency with the
initialization of ENABLE_FEAT_RAS when it's not set on the commandline.
However, building them when ENABLE_FEAT_RAS=0 will not produce any side
effects and the code will never be called. So we can always build the
files to remove the circular check.

Change-Id: I44f90daa193c9b2c853f3fd9b54b67ccc7bace83
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(fvp): give fvp_ras.c better dependencies

PLATFORM_TEST_RAS_FFH should default to 0 when unset. It will always be
defined on the commandline so it needs to be checked for truthfulness.
SDEI_SUPPO

fix(fvp): give fvp_ras.c better dependencies

PLATFORM_TEST_RAS_FFH should default to 0 when unset. It will always be
defined on the commandline so it needs to be checked for truthfulness.
SDEI_SUPPORT will also be used so it must be set.

Change-Id: I0fed6ef40eee82a3624de7bc0c85f5662af4ca3a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpufeat): add ras files to the build from a common location

If ENABLE_FEAT_RAS is unset on the build commandline the platform.mk
will run and make its decisions with the flag unset, after which

fix(cpufeat): add ras files to the build from a common location

If ENABLE_FEAT_RAS is unset on the build commandline the platform.mk
will run and make its decisions with the flag unset, after which
arch_features.mk will run and enable the feature. The result in the RAS
case is a build failure due to missing symbols.

Nvidia works around this by setting ENABLE_FEAT_RAS manually despite the
arch_features.mk setting.

Every platform that enables ENABLE_FEAT_RAS also pulls in
std_err_record.c and ras_common.c. So fix the build failure by having
these files be pulled into the build from common code in bl31.mk.

Change-Id: I018869d3f1904821523ac88d70e88eb90959784b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(imx): check if the cluster id is valid

Check if the cluster id is valid, if not, return directly.

NXP would like to thank Giorgiomaria Cicero and Gabriele Serra from
Accelerat for their respons

fix(imx): check if the cluster id is valid

Check if the cluster id is valid, if not, return directly.

NXP would like to thank Giorgiomaria Cicero and Gabriele Serra from
Accelerat for their responsible disclosure

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I69997512fc080daa9579f92a4de9e47531185bcf

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Merge "fix(intel): correct condition to process unused entries" into integration

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whet

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whether the platform might want to use something different. The thinking
was to provide a default and then let each platform override it, however
the order was swapped.

To fix this, put the gic_set_gicr_frames() in bl31_platform_setup()
rather than arm_bl31_platform_setup(). This way, platforms that use the
default can still enjoy it automatically pulled in from common code,
platforms that need fully custom gicr_frames can simply set it, and
platforms that override bl31_platform_setup() for unrelated reasons only
have to redo the call to gic_set_gicr_frames(). This has a tiny benefit
over the old approach in that there will never be 2 gicr_frames arrays.

Change-Id: I734737d3bd37ddbb3286abcdd92c88676c68cdc3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(xilinx): deprecate PM_REQ_SUSPEND EEMI API

Deprecate the use of the PM_REQ_SUSPEND EEMI API from the Versal,
Versal-Net and Versal Gen 2 platforms. This is because the API is
intended for suspe

feat(xilinx): deprecate PM_REQ_SUSPEND EEMI API

Deprecate the use of the PM_REQ_SUSPEND EEMI API from the Versal,
Versal-Net and Versal Gen 2 platforms. This is because the API is
intended for suspending cross-subsystems, and the same functionality
can now be achieved using the ForcePowerdown API. Therefore,
continuing to use PM_REQ_SUSPEND API may no longer be necessary.
Hence deprecating the same.

Change-Id: I967d7803da4cf433fabfe8d87c32305954f69884
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being generated and subsequent address fault.

Note that FEAT_CPA is a trivial implementation that exists in
some hardware purely so it can run CPA2-enabled instructions
without crashing but they don't actually have checked arithmetic,
so FEAT_CPA is not explicitly enabled in TF-A.

Change-Id: I6d2ca7a7e4b986bb9e917aa8baf8091a271c168b
Signed-off-by: John Powell <john.powell@arm.com>

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feat(ti): de-assert AINACTS at boot

De-asserting AINACTS at startup to enable ACP interface. This is
required to enable limited system level IO coherency via ACP port
(eg.: DMA traffic on AM62L driv

feat(ti): de-assert AINACTS at boot

De-asserting AINACTS at startup to enable ACP interface. This is
required to enable limited system level IO coherency via ACP port
(eg.: DMA traffic on AM62L driving ASEL = 14/15).

Change-Id: Iceaf992dec5dc37eae6dc06895585ea712f23496
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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feat(arm): handle RMM ep_info during LFA

Update the logic for next image handoff to correctly manage the
RMM entry point information when LFA is in progress.
This ensures control is passed back into

feat(arm): handle RMM ep_info during LFA

Update the logic for next image handoff to correctly manage the
RMM entry point information when LFA is in progress.
This ensures control is passed back into RMM during the
activation sequence.

This change only affects during LFA run, normal boot behavior
is unchanged.

Change-Id: I8f85e9a7e0a7e9dab196c69ecf55abb9e7717982
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "refactor(tc): neaten platform code after TC2 removal" into integration

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition table at
runtime, so a fixed offset is unnecessary. Also cleaned up the FIP
address handling comment for clarity.

Change-Id: I03f003a9307d66d16666eefcff1f45bb010779c9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when t

fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when the linker garbage collects it. It is also removed.

CPU_DATA_PLAT_PCPU_OFFSET is also removed as its only use is in
rcar_lock_get() and related macros which are never called since all
calls of these macros lack an argument.

Change-Id: I883ab58c56b4082e0e8b19a8d8f6186945bcc58e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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