1 /*
2 * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <assert.h>
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <common/desc_image_load.h>
15 #include <drivers/cadence/cdns_sdmmc.h>
16 #include <drivers/generic_delay_timer.h>
17 #include <drivers/synopsys/dw_mmc.h>
18 #include <drivers/ti/uart/uart_16550.h>
19 #include <lib/mmio.h>
20 #include <lib/xlat_tables/xlat_tables_v2.h>
21
22 #include "agilex5_clock_manager.h"
23 #include "agilex5_ddr.h"
24 #include "agilex5_memory_controller.h"
25 #include "agilex5_mmc.h"
26 #include "agilex5_pinmux.h"
27 #include "agilex5_power_manager.h"
28 #include "agilex5_system_manager.h"
29 #include "ccu/ncore_ccu.h"
30 #include "combophy/combophy.h"
31 #include "nand/nand.h"
32 #include "qspi/cadence_qspi.h"
33 #include "sdmmc/sdmmc.h"
34 /* TODO: DTB not available */
35 // #include "socfpga_dt.h"
36 #include "socfpga_emac.h"
37 #include "socfpga_f2sdram_manager.h"
38 #include "socfpga_handoff.h"
39 #include "socfpga_mailbox.h"
40 #include "socfpga_private.h"
41 #include "socfpga_reset_manager.h"
42 #include "socfpga_ros.h"
43 #include "socfpga_vab.h"
44 #include "wdt/watchdog.h"
45
46
47 /* Declare mmc_info */
48 static struct mmc_device_info mmc_info;
49
50 /* Declare cadence idmac descriptor */
51 extern struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT] __aligned(8);
52
53 const mmap_region_t agilex_plat_mmap[] = {
54 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
55 MT_MEMORY | MT_RW | MT_NS),
56 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE,
57 MT_DEVICE | MT_RW | MT_NS),
58 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE,
59 MT_DEVICE | MT_RW | MT_SECURE),
60 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
61 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
62 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE,
63 MT_DEVICE | MT_RW | MT_SECURE),
64 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
65 MT_DEVICE | MT_RW | MT_NS),
66 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE,
67 MT_DEVICE | MT_RW | MT_SECURE),
68 {0},
69 };
70
71 boot_source_type boot_source = BOOT_SOURCE;
72
bl2_el3_early_platform_setup(u_register_t x0 __unused,u_register_t x1 __unused,u_register_t x2 __unused,u_register_t x3 __unused)73 void bl2_el3_early_platform_setup(u_register_t x0 __unused,
74 u_register_t x1 __unused,
75 u_register_t x2 __unused,
76 u_register_t x3 __unused)
77 {
78 static console_t console;
79 handoff reverse_handoff_ptr;
80 uint32_t reg_val;
81
82 /* Enable nonsecure access for peripherals and other misc components */
83 enable_nonsecure_access();
84
85 /* Bring all the required peripherals out of reset */
86 deassert_peripheral_reset();
87
88 /*
89 * Initialize the UART console early in BL2 EL3 boot flow to get
90 * the error/notice messages wherever required.
91 */
92 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
93 PLAT_BAUDRATE, &console);
94
95 /* Generic delay timer init */
96 generic_delay_timer_init();
97
98 socfpga_delay_timer_init();
99
100 /* Get the handoff data */
101 if ((socfpga_get_handoff(&reverse_handoff_ptr)) != 0) {
102 ERROR("SOCFPGA: Failed to get the correct handoff data\n");
103 panic();
104 }
105
106 /* Configure the pinmux */
107 config_pinmux(&reverse_handoff_ptr);
108
109 /* Configure OCRAM to NON SECURE ACCESS */
110 mmio_write_32(OCRAM_REGION_0_REG_BASE, OCRAM_NON_SECURE_ENABLE);
111 mmio_write_32(SOCFPGA_L4_PER_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
112 SOCFPGA_SDMMC_SECU_BIT_ENABLE);
113 mmio_write_32(SOCFPGA_L4_SYS_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
114 SOCFPGA_SDMMC_SECU_BIT_ENABLE);
115 mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE,
116 SOCFPGA_LWSOC2FPGA_ENABLE);
117
118 /* Configure the clock manager */
119 if ((config_clkmgr_handoff(&reverse_handoff_ptr)) != 0) {
120 ERROR("SOCFPGA: Failed to initialize the clock manager\n");
121 panic();
122 }
123
124 /* Configure power manager PSS SRAM power gate */
125 config_pwrmgr_handoff(&reverse_handoff_ptr);
126
127 /* Initialize the mailbox to enable communication between HPS and SDM */
128 mailbox_init();
129
130 /* Perform a handshake with certain peripherals before issuing a reset */
131 config_hps_hs_before_warm_reset();
132
133 /* TODO: watchdog init */
134 //watchdog_init(clkmgr_get_rate(CLKMGR_WDT_CLK_ID));
135
136 /* Initialize the CCU module for hardware cache coherency */
137 init_ncore_ccu();
138
139 socfpga_emac_init();
140
141 /* DDR and IOSSM driver init */
142 if ((agilex5_ddr_init(&reverse_handoff_ptr)) != 0) {
143 ERROR("SOCFPGA: Failed to initialize the ddr.\n");
144 panic();
145 }
146
147 /* TODO: DTB not available */
148 // if (socfpga_dt_open_and_check(SOCFPGA_DTB_BASE, DT_COMPATIBLE_STR) < 0) {
149 // ERROR("SOCFPGA: Failed to open device tree\n");
150 // panic();
151 // }
152
153 if (combo_phy_init(&reverse_handoff_ptr) != 0) {
154 ERROR("SOCFPGA: Combo Phy initialization failed\n");
155 }
156
157 /* Enable FPGA bridges as required */
158 if (!intel_mailbox_is_fpga_not_ready()) {
159 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
160 FPGA2SOC_MASK | F2SDRAM0_MASK);
161 }
162
163 /* Configure USB 3.1 in system manager */
164 reg_val = mmio_read_32(SOCFPGA_SYSMGR(USB3_MISC_CTRL_REG0));
165 reg_val |= SYSMGR_USB3_MISC0_PORT_OVR_CURR_PIPE_PWR; /* set pipe power present bit */
166 mmio_write_32(SOCFPGA_SYSMGR(USB3_MISC_CTRL_REG0), reg_val);
167 VERBOSE("USB3_MISC_CTRL_REG0 = 0x%X\n", mmio_read_32(SOCFPGA_SYSMGR(USB3_MISC_CTRL_REG0)));
168 }
169
bl2_el3_plat_arch_setup(void)170 void bl2_el3_plat_arch_setup(void)
171 {
172 unsigned long offset = 0;
173
174 struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc,
175 SDEMMC_SDCLK);
176
177 params.sdmclk = clkmgr_get_rate(CLKMGR_SDMMC_CLK_ID);
178 mmc_info.mmc_dev_type = MMC_DEVICE_TYPE;
179 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
180
181 INFO("SDMMC/NAND clock is %u\n", clkmgr_get_rate(CLKMGR_SDMMC_CLK_ID));
182
183 /* Request ownership and direct access to QSPI */
184 mailbox_hps_qspi_enable();
185
186 switch (boot_source) {
187 case BOOT_SOURCE_SDMMC:
188 NOTICE("SOCFPGA: SDMMC boot\n");
189 cdns_mmc_init(¶ms, &mmc_info);
190 socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
191 break;
192
193 case BOOT_SOURCE_QSPI:
194 NOTICE("SOCFPGA: QSPI boot\n");
195 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
196 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
197 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
198 if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) {
199 offset = PLAT_QSPI_DATA_BASE;
200 }
201 socfpga_io_setup(boot_source, offset);
202 break;
203
204 case BOOT_SOURCE_NAND:
205 NOTICE("SOCFPGA: NAND boot\n");
206 nand_init();
207 socfpga_io_setup(boot_source, PLAT_NAND_DATA_BASE);
208 break;
209
210 default:
211 ERROR("SOCFPGA: Unsupported boot source\n");
212 panic();
213 break;
214 }
215 }
216
get_spsr_for_bl33_entry(void)217 uint32_t get_spsr_for_bl33_entry(void)
218 {
219 unsigned long el_status;
220 unsigned int mode;
221 uint32_t spsr;
222
223 /* Figure out what mode we enter the non-secure world in */
224 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
225 el_status &= ID_AA64PFR0_ELX_MASK;
226
227 mode = (el_status) ? MODE_EL2 : MODE_EL1;
228
229 /*
230 * TODO: Consider the possibility of specifying the SPSR in
231 * the FIP ToC and allowing the platform to have a say as
232 * well.
233 */
234 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
235 return spsr;
236 }
237
bl2_plat_handle_post_image_load(unsigned int image_id)238 int bl2_plat_handle_post_image_load(unsigned int image_id)
239 {
240 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
241
242 assert(bl_mem_params);
243
244 #if SOCFPGA_SECURE_VAB_AUTH
245 /*
246 * VAB Authentication start here.
247 * If failed to authenticate, shall not proceed to process BL31 and hang.
248 */
249 int ret = 0;
250
251 ret = socfpga_vab_init(image_id);
252 if (ret < 0) {
253 ERROR("SOCFPGA: VAB Authentication failed\n");
254 wfi();
255 }
256 #endif
257
258 switch (image_id) {
259 case BL33_IMAGE_ID:
260 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
261 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
262 break;
263 default:
264 break;
265 }
266
267 return 0;
268 }
269
270 /*******************************************************************************
271 * Perform any BL3-1 platform setup code
272 ******************************************************************************/
bl2_platform_setup(void)273 void bl2_platform_setup(void)
274 {
275 }
276