1 /*
2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <platform_def.h>
8
9 #include <common/bl_common.h>
10 #include <common/interrupt_props.h>
11 #include <drivers/arm/gicv3.h>
12 #include <drivers/arm/arm_gicv3_common.h>
13 #include <lib/mmio.h>
14 #include <lib/utils.h>
15 #include <plat/common/platform.h>
16
17 #include <plat_imx8.h>
18
19 #ifdef SM_AP_SEMA_ADDR
20 extern void request_sm_ap_sema(void);
21 extern void release_sm_ap_sema(void);
22 #endif
23
24 /* the GICv3 driver only needs to be initialized in EL3 */
25 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
26
27 static const interrupt_prop_t g01s_interrupt_props[] = {
28 INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY,
29 INTR_GROUP0, GIC_INTR_CFG_LEVEL),
30 #if SDEI_SUPPORT
31 INTR_PROP_DESC(PLAT_SDEI_SGI_PRIVATE, PLAT_SDEI_NORMAL_PRI,
32 INTR_GROUP0, GIC_INTR_CFG_LEVEL),
33 #endif
34 };
35
plat_imx_mpidr_to_core_pos(unsigned long mpidr)36 static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr)
37 {
38 return (unsigned int)plat_core_pos_by_mpidr(mpidr);
39 }
40
41 const gicv3_driver_data_t arm_gic_data = {
42 .gicd_base = PLAT_GICD_BASE,
43 .gicr_base = PLAT_GICR_BASE,
44 .interrupt_props = g01s_interrupt_props,
45 .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
46 .rdistif_num = PLATFORM_CORE_COUNT,
47 .rdistif_base_addrs = rdistif_base_addrs,
48 .mpidr_to_core_pos = plat_imx_mpidr_to_core_pos,
49 };
50
plat_gic_driver_init(void)51 void plat_gic_driver_init(void)
52 {
53 /*
54 * the GICv3 driver is initialized in EL3 and does not need
55 * to be initialized again in S-EL1. This is because the S-EL1
56 * can use GIC system registers to manage interrupts and does
57 * not need GIC interface base addresses to be configured.
58 */
59 #if IMAGE_BL31
60 gicv3_driver_init(&arm_gic_data);
61 #endif
62 }
63
plat_gicr_exit_sleep(void)64 static __inline void plat_gicr_exit_sleep(void)
65 {
66 unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER);
67
68 /*
69 * ProcessorSleep bit can ONLY be set to zero when
70 * Quiescent bit and Sleep bit are both zero, so
71 * need to make sure Quiescent bit and Sleep bit
72 * are zero before clearing ProcessorSleep bit.
73 */
74 if (val & WAKER_QSC_BIT) {
75 mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT);
76 /* Wait till the WAKER_QSC_BIT changes to 0 */
77 while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U)
78 ;
79 }
80 }
81
plat_gic_init(void)82 void plat_gic_init(void)
83 {
84 plat_gicr_exit_sleep();
85 gicv3_distif_init();
86 gicv3_rdistif_init(plat_my_core_pos());
87 gicv3_cpuif_enable(plat_my_core_pos());
88 }
89
plat_gic_cpuif_enable(void)90 void plat_gic_cpuif_enable(void)
91 {
92 gicv3_cpuif_enable(plat_my_core_pos());
93 }
94
plat_gic_cpuif_disable(void)95 void plat_gic_cpuif_disable(void)
96 {
97 gicv3_cpuif_disable(plat_my_core_pos());
98 }
99
gic_cpuif_enable(unsigned int cpu_idx)100 void gic_cpuif_enable(unsigned int cpu_idx)
101 {
102 #ifdef SM_AP_SEMA_ADDR
103 request_sm_ap_sema();
104 #endif
105 gicv3_cpuif_enable(plat_my_core_pos());
106
107 #ifdef SM_AP_SEMA_ADDR
108 release_sm_ap_sema();
109 #endif
110 }
111
gic_cpuif_disable(unsigned int cpu_idx)112 void gic_cpuif_disable(unsigned int cpu_idx)
113 {
114 #ifdef SM_AP_SEMA_ADDR
115 request_sm_ap_sema();
116 #endif
117 gicv3_cpuif_disable(plat_my_core_pos());
118
119 #ifdef SM_AP_SEMA_ADDR
120 release_sm_ap_sema();
121 #endif
122 }
123
plat_gic_pcpu_init(void)124 void plat_gic_pcpu_init(void)
125 {
126 gicv3_rdistif_init(plat_my_core_pos());
127 }
128
plat_gic_save(unsigned int proc_num,struct plat_gic_ctx * ctx)129 void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx)
130 {
131 /* save the gic rdist/dist context */
132 for (int i = 0; i < PLATFORM_CORE_COUNT; i++)
133 gicv3_rdistif_save(i, &ctx->rdist_ctx[i]);
134 gicv3_distif_save(&ctx->dist_ctx);
135 }
136
plat_gic_restore(unsigned int proc_num,struct plat_gic_ctx * ctx)137 void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx)
138 {
139 /* restore the gic rdist/dist context */
140 gicv3_distif_init_restore(&ctx->dist_ctx);
141 for (int i = 0; i < PLATFORM_CORE_COUNT; i++)
142 gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]);
143 }
144