Merge "feat(corstone1000): add multicore support for fvp" into integration

Merge "refactor(dice): save parent context handle" into integration

feat(tc): add uart node in spmc manifest

The device memory described in the SP manifest has to be described in
the SPMC manifest as well. In this case, OP-TEE includes this UART
device in its SP man

feat(tc): add uart node in spmc manifest

The device memory described in the SP manifest has to be described in
the SPMC manifest as well. In this case, OP-TEE includes this UART
device in its SP manifest. Hence, this commit adds it in the SPMC
manifest.

Change-Id: I0f84d7b105c072dd021f0f2d215adf6bcdf5f98f
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "feat(versal2): add support for AMD Versal Gen 2 platform" into integration

Merge changes from topic "ip_smmu" into integration

* changes:
feat(tc): bind SMMU-600 with the DPU on TC3 FPGA
feat(tc): bind SMMU-700 with DPU on TC3
refactor(tc): append binding for SMMU-700

Merge "feat(versal-net): set lower cluster bus qos value" into integration

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the secondary cores.

Change-Id: Ie66b3dc43abadec88323999052357e2a9cdfd950
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

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refactor(st): move FWU support to common code

Move PLAT_PARTITION_MAX_ENTRIES and all other definitions linked to it
to common.mk.
Move drivers/fwu/fwu.mk inclusion there as well.

Signed-off-by: Ya

refactor(st): move FWU support to common code

Move PLAT_PARTITION_MAX_ENTRIES and all other definitions linked to it
to common.mk.
Move drivers/fwu/fwu.mk inclusion there as well.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I5dde65e41908d706328cb8929582f827ceeff841

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refactor(st): move FWU functions to common code

Move the platforms functions used for Firmware update in plat/st/common
directory. The function stm32mp1_fwu_set_boot_idx() is renamed
stm32_fwu_set_b

refactor(st): move FWU functions to common code

Move the platforms functions used for Firmware update in plat/st/common
directory. The function stm32mp1_fwu_set_boot_idx() is renamed
stm32_fwu_set_boot_idx() to align with other ones. A new function
stm32_get_bkpr_fwu_info_addr() is created to get the backup register
address where to store FWU info (counter and partition index).

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I64916c7992782ceeaaf990026756ca4134d93c88

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feat(versal-net): set lower cluster bus qos value

arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories i

feat(versal-net): set lower cluster bus qos value

arm clusterbusqos register has a default value of 0xeeeeeeee.
this may create bottleneck for other masters in system when
accessing other memories including ddr.
hence clusterbusqos is setup to lowest value 0.

Change-Id: I73d55066eb84e198c8c69593bb5700745f04f290
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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Merge "feat(fvp): add cpu power control" into integration

Merge changes from topic "st-nand-backup-fwu" into integration

* changes:
refactor(st): rename plat_set_image_source
feat(st): add FWU with boot from NAND
feat(st): manage backup partitions fo

Merge changes from topic "st-nand-backup-fwu" into integration

* changes:
refactor(st): rename plat_set_image_source
feat(st): add FWU with boot from NAND
feat(st): manage backup partitions for NAND devices
feat(bl): add plat handler for image loading
refactor(bl)!: remove unused plat_try_next_boot_source

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refactor(tc): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software componen

refactor(tc): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software components, and to
provide a more realistic breakdown of the expected components in the CCA
TCB.

This change replaces the static CCA platform token in the Total Compute
platform.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493

Change-Id: I792e693cc994fc1e856f713fd97bac4930b28e1e
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>

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Merge changes from topic "st_gpio_update" into integration

* changes:
fix(st-gpio): configure each GPIO mux as secure for STM32MP2
feat(st-gpio): add set GPIO config API
fix(stm32mp1): remove

Merge changes from topic "st_gpio_update" into integration

* changes:
fix(st-gpio): configure each GPIO mux as secure for STM32MP2
feat(st-gpio): add set GPIO config API
fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value
refactor(st): use GPIO banks definition from bindings
feat(dt-bindings): describe ST GPIO banks and config

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Merge "fix(tc): add SCP_BL2 to RSE measured boot" into integration

fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value

Remove assert for unexpected value of the define GPIO_BANK_A.

This check is not required as GPIO_BANK_A = 0, it can be limited to
have

fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value

Remove assert for unexpected value of the define GPIO_BANK_A.

This check is not required as GPIO_BANK_A = 0, it can be limited to
have bank <= GPIO_BANK_K as bank is unsigned int.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I0345d56f106fcacd6a6f93281c2d9279980cd152

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refactor(st): use GPIO banks definition from bindings

Use GPIO banks definition from bindings.

Change-Id: I4dcf321345e319af78285e940b72a1369569b996
Signed-off-by: Pascal Paillet <p.paillet@st.com>

fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 G

fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 GPT table. Add two pages to the L0 GPT reserve.
This could be optimized later by moving the bitlock somewhere else,
because it really only needs (1 << PPS.T) / (512M * 8) = 256 bytes for
the QEMU virt platform.

Fix two more comments in qemu_pas_def.h since we're here.

Change-Id: I2b0b8de38f4b5058735ed16f1cdc50e6b2d52ad9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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fix(rockchip): add parenthesis for BITS_SHIFT macro

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ideac271469f0753c5b7aaed7bb07a792b64ae01e

fix(rockchip): xlat: fix compatibility between v1 and v2

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I1194ef232947ba90fa374466773373762a5acdb5

feat(fvp): add cpu power control

Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from

feat(fvp): add cpu power control

Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from CPU Power control.

However there are certain older CPU's that don't have DSU and
don't support CPUPWRCTRL_EL1, so populate them as a list
and ignore setting core-off bit for those older CPU's as all newer
CPU's have them.

Note: unfortunately there is no mechanism to identify if a DSU is
present and CPUPWRCTRL_EL1 is supported through any CPU control
registers and CPUPWRCTRL_EL1 is supported only for ARM64 platforms
and not available in ARM32 platforms.

Change-Id: Iba6c3c8db60dbeb177cead7ebc65df8265860da7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables

build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables are boolean values determining
whether the build system has been configured to run silently or
verbosely respectively (i.e. with `--silent` or `V=1`).

These two modes cannot be used together - if `silent` is truthy then
`verbose` is always falsy. As such:

make --silent V=1

... results in a silent build.

In addition to these boolean variables, we also introduce two new
variables - `s` and `q` - for use in rule recipes to conditionally
suppress the output of commands.

When building silently, `s` expands to a value which disables the
command that follows, and `q` expands to a value which supppresses
echoing of the command:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed but not echoed'

When building verbosely, `s` expands to a value which disables the
command that follows, and `q` expands to nothing:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed and echoed'

In all other cases, both `s` and `q` expand to a value which suppresses
echoing of the command that follows:

$(s)echo 'This command is executed but not echoed'
$(q)echo 'This command is executed but not echoed'

The `s` variable is predominantly useful for `echo` commands, where you
always want to suppress echoing of the command itself, whilst `q` is
more useful for all other commands.

Change-Id: I8d8ff6ed714d3cb401946c52955887ed7dca602b
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build: add string casing facilities to utilities

This is a small modification to two existing functions in the build
system: `uppercase` and `lowercase`.

These functions have been moved to the comm

build: add string casing facilities to utilities

This is a small modification to two existing functions in the build
system: `uppercase` and `lowercase`.

These functions have been moved to the common utilities makefile, and
use the `tr` tool to simplify their implementation. Behaviour is, for
virtually all use-cases, identical.

Change-Id: I0e459d92e454087e4188b2fa5968244e5db89906
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "st_clk_update" into integration

* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct

Merge changes from topic "st_clk_update" into integration

* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct
feat(stm32mp1-fdts): remove RTC clock configuration
refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock
refactor(st-clock): driver size optimization
refactor(st-clock): remove BL32 support on STM32MP13
feat(st-clock): don't gate/ungate an oscillator if it is not wired
feat(dt-bindings): add missing SPIx bus clocks
feat(stm32mp1-fdts): remove PLL1 settings
feat(st-clock): update with new bindings
feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1
feat(dt-bindings): new RCC DT bindings
feat(stm32mp1): always boot at 650MHz
refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13
fix(st-clock): display proper PLL number for STM32MP13
fix(st-clock): do not reconfigure LSE
feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation
refactor(st-clock): remove unused clk function in API
refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config
feat(st-clock): add function to restore generic timer rate

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Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure acces

Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure access to pmu counters on TC3

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