1 /* 2 * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /* Extracts the CPU part number from MIDR for checking CPU match */ 28 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 29 30 /******************************************************************************* 31 * MPIDR macros 32 ******************************************************************************/ 33 #define MPIDR_MT_MASK (ULL(1) << 24) 34 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 35 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 36 #define MPIDR_AFFINITY_BITS U(8) 37 #define MPIDR_AFFLVL_MASK ULL(0xff) 38 #define MPIDR_AFF0_SHIFT U(0) 39 #define MPIDR_AFF1_SHIFT U(8) 40 #define MPIDR_AFF2_SHIFT U(16) 41 #define MPIDR_AFF3_SHIFT U(32) 42 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 44 #define MPIDR_AFFLVL_SHIFT U(3) 45 #define MPIDR_AFFLVL0 ULL(0x0) 46 #define MPIDR_AFFLVL1 ULL(0x1) 47 #define MPIDR_AFFLVL2 ULL(0x2) 48 #define MPIDR_AFFLVL3 ULL(0x3) 49 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 50 #define MPIDR_AFFLVL0_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL1_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 54 #define MPIDR_AFFLVL2_VAL(mpidr) \ 55 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 56 #define MPIDR_AFFLVL3_VAL(mpidr) \ 57 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 58 /* 59 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 60 * add one while using this macro to define array sizes. 61 * TODO: Support only the first 3 affinity levels for now. 62 */ 63 #define MPIDR_MAX_AFFLVL U(2) 64 65 #define MPID_MASK (MPIDR_MT_MASK | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 67 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 68 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 69 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 70 71 #define MPIDR_AFF_ID(mpid, n) \ 72 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 73 74 /* 75 * An invalid MPID. This value can be used by functions that return an MPID to 76 * indicate an error. 77 */ 78 #define INVALID_MPID U(0xFFFFFFFF) 79 80 /******************************************************************************* 81 * Definitions for Exception vector offsets 82 ******************************************************************************/ 83 #define CURRENT_EL_SP0 0x0 84 #define CURRENT_EL_SPX 0x200 85 #define LOWER_EL_AARCH64 0x400 86 #define LOWER_EL_AARCH32 0x600 87 88 #define SYNC_EXCEPTION 0x0 89 #define IRQ_EXCEPTION 0x80 90 #define FIQ_EXCEPTION 0x100 91 #define SERROR_EXCEPTION 0x180 92 93 /******************************************************************************* 94 * Encodings for GICv5 EL3 system registers 95 ******************************************************************************/ 96 #define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4 97 #define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5 98 #define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6 99 #define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7 100 101 #define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3) 102 #define ICC_PPI_DOMAINR_COUNT (32) 103 104 /******************************************************************************* 105 * Definitions for CPU system register interface to GICv3 106 ******************************************************************************/ 107 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 108 #define ICC_SGI1R S3_0_C12_C11_5 109 #define ICC_ASGI1R S3_0_C12_C11_6 110 #define ICC_SRE_EL1 S3_0_C12_C12_5 111 #define ICC_SRE_EL2 S3_4_C12_C9_5 112 #define ICC_SRE_EL3 S3_6_C12_C12_5 113 #define ICC_CTLR_EL1 S3_0_C12_C12_4 114 #define ICC_CTLR_EL3 S3_6_C12_C12_4 115 #define ICC_PMR_EL1 S3_0_C4_C6_0 116 #define ICC_RPR_EL1 S3_0_C12_C11_3 117 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 118 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 119 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 120 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 121 #define ICC_IAR0_EL1 S3_0_c12_c8_0 122 #define ICC_IAR1_EL1 S3_0_c12_c12_0 123 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 124 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 125 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 126 127 /******************************************************************************* 128 * Definitions for EL2 system registers for save/restore routine 129 ******************************************************************************/ 130 #define CNTPOFF_EL2 S3_4_C14_C0_6 131 #define HDFGRTR2_EL2 S3_4_C3_C1_0 132 #define HDFGWTR2_EL2 S3_4_C3_C1_1 133 #define HFGRTR2_EL2 S3_4_C3_C1_2 134 #define HFGWTR2_EL2 S3_4_C3_C1_3 135 #define HDFGRTR_EL2 S3_4_C3_C1_4 136 #define HDFGWTR_EL2 S3_4_C3_C1_5 137 #define HAFGRTR_EL2 S3_4_C3_C1_6 138 #define HFGITR2_EL2 S3_4_C3_C1_7 139 #define HFGITR_EL2 S3_4_C1_C1_6 140 #define HFGRTR_EL2 S3_4_C1_C1_4 141 #define HFGWTR_EL2 S3_4_C1_C1_5 142 #define ICH_HCR_EL2 S3_4_C12_C11_0 143 #define ICH_VMCR_EL2 S3_4_C12_C11_7 144 #define MPAMVPM0_EL2 S3_4_C10_C6_0 145 #define MPAMVPM1_EL2 S3_4_C10_C6_1 146 #define MPAMVPM2_EL2 S3_4_C10_C6_2 147 #define MPAMVPM3_EL2 S3_4_C10_C6_3 148 #define MPAMVPM4_EL2 S3_4_C10_C6_4 149 #define MPAMVPM5_EL2 S3_4_C10_C6_5 150 #define MPAMVPM6_EL2 S3_4_C10_C6_6 151 #define MPAMVPM7_EL2 S3_4_C10_C6_7 152 #define MPAMVPMV_EL2 S3_4_C10_C4_1 153 #define VNCR_EL2 S3_4_C2_C2_0 154 #define PMSCR_EL2 S3_4_C9_C9_0 155 #define TFSR_EL2 S3_4_C5_C6_0 156 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 157 #define TTBR1_EL2 S3_4_C2_C0_1 158 159 /******************************************************************************* 160 * Generic timer memory mapped registers & offsets 161 ******************************************************************************/ 162 #define CNTCR_OFF U(0x000) 163 #define CNTCV_OFF U(0x008) 164 #define CNTFID_OFF U(0x020) 165 166 #define CNTCR_EN (U(1) << 0) 167 #define CNTCR_HDBG (U(1) << 1) 168 #define CNTCR_FCREQ(x) ((x) << 8) 169 170 /******************************************************************************* 171 * System register bit definitions 172 ******************************************************************************/ 173 /* CLIDR definitions */ 174 #define LOUIS_SHIFT U(21) 175 #define LOC_SHIFT U(24) 176 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 177 #define CLIDR_FIELD_WIDTH U(3) 178 179 /* CSSELR definitions */ 180 #define LEVEL_SHIFT U(1) 181 182 /* Data cache set/way op type defines */ 183 #define DCISW U(0x0) 184 #define DCCISW U(0x1) 185 #if ERRATA_A53_827319 186 #define DCCSW DCCISW 187 #else 188 #define DCCSW U(0x2) 189 #endif 190 191 #define ID_REG_FIELD_MASK ULL(0xf) 192 193 /******************************************************************************* 194 * PFR0_EL1 - Definitions for AArch32 Processor Feature Register 0 195 ******************************************************************************/ 196 #define ID_PFR0_EL1 S3_0_C0_C1_0 197 198 /******************************************************************************* 199 * PFR2_EL1 - Definitions for AArch32 Processor Feature Register 2 200 ******************************************************************************/ 201 #define ID_PFR2_EL1 S3_0_C0_C3_4 202 203 /******************************************************************************* 204 * ID_ISAR6_EL1 - Definition for AArch32 Instruction Set Attribute Register 6 205 ******************************************************************************/ 206 #define ID_ISAR6_EL1 S3_0_C0_C2_7 207 208 /******************************************************************************* 209 * ID_DFR1_EL1 - Definition for AArch32 Debug Feature Register 1 210 ******************************************************************************/ 211 #define ID_DFR1_EL1 S3_0_C0_C3_5 212 213 /* ID_AA64PFR0_EL1 definitions */ 214 #define ID_AA64PFR0_EL0_SHIFT U(0) 215 #define ID_AA64PFR0_EL1_SHIFT U(4) 216 #define ID_AA64PFR0_EL2_SHIFT U(8) 217 #define ID_AA64PFR0_EL3_SHIFT U(12) 218 219 #define ID_AA64PFR0_AMU_SHIFT U(44) 220 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 221 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 222 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 223 224 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 225 #define ID_AA64PFR0_EL0_MASK ID_AA64PFR0_ELX_MASK 226 #define ID_AA64PFR0_EL1_MASK ID_AA64PFR0_ELX_MASK 227 #define ID_AA64PFR0_EL2_MASK ID_AA64PFR0_ELX_MASK 228 #define ID_AA64PFR0_EL3_MASK ID_AA64PFR0_ELX_MASK 229 230 #define ID_AA64PFR0_GIC_SHIFT U(24) 231 #define ID_AA64PFR0_GIC_WIDTH U(4) 232 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 233 234 #define ID_AA64PFR0_SVE_SHIFT U(32) 235 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 236 #define ID_AA64PFR0_SVE_LENGTH U(4) 237 #define SVE_IMPLEMENTED ULL(0x1) 238 239 #define ID_AA64PFR0_SEL2_SHIFT U(36) 240 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 241 242 #define ID_AA64PFR0_MPAM_SHIFT U(40) 243 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 244 245 #define ID_AA64PFR0_DIT_SHIFT U(48) 246 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 247 #define ID_AA64PFR0_DIT_LENGTH U(4) 248 #define DIT_IMPLEMENTED ULL(1) 249 250 #define ID_AA64PFR0_CSV2_SHIFT U(56) 251 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 252 #define ID_AA64PFR0_CSV2_LENGTH U(4) 253 #define CSV2_2_IMPLEMENTED ULL(0x2) 254 #define CSV2_3_IMPLEMENTED ULL(0x3) 255 256 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 257 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 258 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 259 #define RME_NOT_IMPLEMENTED ULL(0) 260 #define RME_GPC2_IMPLEMENTED ULL(0x2) 261 262 #define ID_AA64PFR0_RAS_SHIFT U(28) 263 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 264 #define ID_AA64PFR0_RAS_LENGTH U(4) 265 266 /* Exception level handling */ 267 #define EL_IMPL_NONE ULL(0) 268 #define EL_IMPL_A64ONLY ULL(1) 269 #define EL_IMPL_A64_A32 ULL(2) 270 271 /* ID_AA64DFR0_EL1.DebugVer definitions */ 272 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 273 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 274 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 275 276 /* ID_AA64DFR0_EL1.TraceVer definitions */ 277 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 278 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 279 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 280 281 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 282 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 283 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 284 #define TRACEFILT_IMPLEMENTED ULL(1) 285 286 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 287 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 288 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 289 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 290 #define ID_AA64DFR0_PMUVER_PMUV3P9 U(9) 291 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 292 293 /* ID_AA64DFR0_EL1.SEBEP definitions */ 294 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 295 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 296 #define SEBEP_IMPLEMENTED ULL(1) 297 298 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 299 #define ID_AA64DFR0_PMS_SHIFT U(32) 300 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 301 #define SPE_IMPLEMENTED ULL(0x1) 302 #define SPE_NOT_IMPLEMENTED ULL(0x0) 303 304 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 305 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 306 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 307 #define TRACEBUFFER_IMPLEMENTED ULL(1) 308 309 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 310 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 311 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 312 #define MTPMU_IMPLEMENTED ULL(1) 313 #define MTPMU_NOT_IMPLEMENTED ULL(15) 314 315 /* ID_AA64DFR0_EL1.BRBE definitions */ 316 #define ID_AA64DFR0_BRBE_SHIFT U(52) 317 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 318 #define BRBE_IMPLEMENTED ULL(1) 319 320 /* ID_AA64DFR1_EL1 definitions */ 321 #define ID_AA64DFR1_EBEP_SHIFT U(48) 322 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 323 #define EBEP_IMPLEMENTED ULL(1) 324 325 #define ID_AA64DFR1_BRP_SHIFT U(8) 326 #define ID_AA64DFR1_BRP_WIDTH U(8) 327 328 #define ID_AA64ZFR0_EL1 S3_0_C0_C4_4 329 #define ID_AA64FPFR0_EL1 S3_0_C0_C4_7 330 #define ID_AA64DFR2_EL1 S3_0_C0_C5_2 331 #define GMID_EL1 S3_1_C0_C0_4 332 333 /* ID_AA64ISAR0_EL1 definitions */ 334 #define ID_AA64ISAR0_ATOMIC_SHIFT U(20) 335 #define ID_AA64ISAR0_ATOMIC_MASK ULL(0xf) 336 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 337 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 338 339 #define ID_AA64ISAR0_AES_SHIFT U(0x4) 340 #define ID_AA64ISAR0_AES_MASK ULL(0xf) 341 #define ID_AA64ISAR0_SHA1_SHIFT U(0x8) 342 #define ID_AA64ISAR0_SHA1_MASK ULL(0xf) 343 #define ID_AA64ISAR0_SHA2_SHIFT U(0xc) 344 #define ID_AA64ISAR0_SHA2_MASK ULL(0xf) 345 346 /* ID_AA64ISAR1_EL1 definitions */ 347 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 348 349 #define ID_AA64ISAR1_LS64_SHIFT U(60) 350 #define ID_AA64ISAR1_LS64_MASK ULL(0xf) 351 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3) 352 #define LS64_V_IMPLEMENTED ULL(0x2) 353 #define LS64_IMPLEMENTED ULL(0x1) 354 #define LS64_NOT_IMPLEMENTED ULL(0x0) 355 356 #define ID_AA64ISAR1_SB_SHIFT U(36) 357 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 358 #define SB_IMPLEMENTED ULL(0x1) 359 #define SB_NOT_IMPLEMENTED ULL(0x0) 360 361 #define ID_AA64ISAR1_GPI_SHIFT U(28) 362 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 363 #define ID_AA64ISAR1_GPA_SHIFT U(24) 364 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 365 366 #define ID_AA64ISAR1_API_SHIFT U(8) 367 #define ID_AA64ISAR1_API_MASK ULL(0xf) 368 #define ID_AA64ISAR1_APA_SHIFT U(4) 369 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 370 371 /* ID_AA64ISAR2_EL1 definitions */ 372 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 373 #define ID_AA64ISAR2_EL1_MOPS_SHIFT U(16) 374 #define ID_AA64ISAR2_EL1_MOPS_MASK ULL(0xf) 375 376 #define MOPS_IMPLEMENTED ULL(0x1) 377 378 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 379 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 380 381 #define ID_AA64ISAR2_APA3_SHIFT U(12) 382 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 383 384 #define ID_AA64ISAR2_CLRBHB_SHIFT U(28) 385 #define ID_AA64ISAR2_CLRBHB_MASK ULL(0xf) 386 387 #define ID_AA64ISAR2_SYSREG128_SHIFT U(32) 388 #define ID_AA64ISAR2_SYSREG128_MASK ULL(0xf) 389 390 /* ID_AA64ISAR3_EL1 definitions */ 391 #define ID_AA64ISAR3_EL1 S3_0_C0_C6_3 392 #define ID_AA64ISAR3_EL1_CPA_SHIFT U(0) 393 #define ID_AA64ISAR3_EL1_CPA_MASK ULL(0xf) 394 395 #define CPA2_IMPLEMENTED ULL(0x2) 396 397 /* ID_AA64MMFR0_EL1 definitions */ 398 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 399 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 400 401 #define PARANGE_0000 U(32) 402 #define PARANGE_0001 U(36) 403 #define PARANGE_0010 U(40) 404 #define PARANGE_0011 U(42) 405 #define PARANGE_0100 U(44) 406 #define PARANGE_0101 U(48) 407 #define PARANGE_0110 U(52) 408 #define PARANGE_0111 U(56) 409 410 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 411 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 412 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 413 #define ECV_IMPLEMENTED ULL(0x1) 414 415 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 416 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 417 #define FGT2_IMPLEMENTED ULL(0x2) 418 #define FGT_IMPLEMENTED ULL(0x1) 419 #define FGT_NOT_IMPLEMENTED ULL(0x0) 420 421 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 422 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 423 424 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 425 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 426 427 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 428 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 429 #define TGRAN16_IMPLEMENTED ULL(0x1) 430 431 /* ID_AA64MMFR1_EL1 definitions */ 432 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 433 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 434 #define TWED_IMPLEMENTED ULL(0x1) 435 436 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 437 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 438 #define PAN_IMPLEMENTED ULL(0x1) 439 #define PAN2_IMPLEMENTED ULL(0x2) 440 #define PAN3_IMPLEMENTED ULL(0x3) 441 442 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 443 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 444 445 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 446 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 447 #define HCX_IMPLEMENTED ULL(0x1) 448 449 /* ID_AA64MMFR2_EL1 definitions */ 450 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 451 452 #define ID_AA64MMFR2_EL1_IDS_SHIFT U(36) 453 #define ID_AA64MMFR2_EL1_IDS_MASK ULL(0xf) 454 455 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 456 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 457 458 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 459 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 460 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 461 462 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 463 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 464 465 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 466 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 467 468 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 469 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 470 #define NV2_IMPLEMENTED ULL(0x2) 471 472 /* ID_AA64MMFR3_EL1 definitions */ 473 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 474 475 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32) 476 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf) 477 #define D128_IMPLEMENTED ULL(0x1) 478 479 #define ID_AA64MMFR3_EL1_MEC_SHIFT U(28) 480 #define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf) 481 482 #define ID_AA64MMFR3_EL1_AIE_SHIFT U(24) 483 #define ID_AA64MMFR3_EL1_AIE_MASK ULL(0xf) 484 485 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 486 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 487 488 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 489 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 490 491 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 492 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 493 494 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 495 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 496 497 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4) 498 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf) 499 #define SCTLR2_IMPLEMENTED ULL(1) 500 501 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 502 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 503 504 /* ID_AA64MMFR4_EL1 definitions */ 505 #define ID_AA64MMFR4_EL1 S3_0_C0_C7_4 506 507 #define ID_AA64MMFR4_EL1_FGWTE3_SHIFT U(16) 508 #define ID_AA64MMFR4_EL1_FGWTE3_MASK ULL(0xf) 509 #define FGWTE3_IMPLEMENTED ULL(0x1) 510 511 #define ID_AA64MMFR4_EL1_RME_GDI_SHIFT U(28) 512 #define ID_AA64MMFR4_EL1_RME_GDI_MASK ULL(0xf) 513 #define ID_AA64MMFR4_EL1_RME_GDI_LENGTH U(4) 514 #define RME_GDI_IMPLEMENTED ULL(0x1) 515 516 /* ID_AA64PFR1_EL1 definitions */ 517 518 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 519 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 520 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 521 522 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 523 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 524 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 525 526 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 527 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 528 529 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 530 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 531 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 532 533 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 534 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 535 #define NMI_IMPLEMENTED ULL(1) 536 537 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 538 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 539 #define GCS_IMPLEMENTED ULL(1) 540 541 #define ID_AA64PFR1_EL1_THE_SHIFT U(48) 542 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf) 543 #define THE_IMPLEMENTED ULL(1) 544 545 #define ID_AA64PFR1_EL1_PFAR_SHIFT U(60) 546 #define ID_AA64PFR1_EL1_PFAR_MASK ULL(0xf) 547 548 /* ID_AA64PFR1_EL1.CE field: Morello architecture presence (bits [23:20]) */ 549 #define ID_AA64PFR1_EL1_CE_SHIFT U(20) 550 #define ID_AA64PFR1_EL1_CE_MASK ULL(0xf) 551 /* 0b0000 means Morello arch is not present, 0b0001 means it is present */ 552 #define MORELLO_EXTENSION_IMPLEMENTED ULL(0x1) 553 #define CSCR_EL3_SETTAG ULL(0x1) 554 555 /* ID_AA64PFR2_EL1 definitions */ 556 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 557 558 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 559 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 560 561 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 562 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 563 564 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 565 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 566 567 #define ID_AA64PFR2_EL1_UINJ_SHIFT U(16) 568 #define ID_AA64PFR2_EL1_UINJ_MASK ULL(0xf) 569 #define UINJ_IMPLEMENTED ULL(0x1) 570 571 #define ID_AA64PFR2_EL1_FPMR_SHIFT U(32) 572 #define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf) 573 574 #define FPMR_IMPLEMENTED ULL(0x1) 575 576 #define VDISR_EL2 S3_4_C12_C1_1 577 #define VSESR_EL2 S3_4_C5_C2_3 578 579 /* Memory Tagging Extension is not implemented */ 580 #define MTE_UNIMPLEMENTED U(0) 581 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 582 #define MTE_IMPLEMENTED_EL0 U(1) 583 /* FEAT_MTE2: Full MTE is implemented */ 584 #define MTE_IMPLEMENTED_ELX U(2) 585 /* 586 * FEAT_MTE3: MTE is implemented with support for 587 * asymmetric Tag Check Fault handling 588 */ 589 #define MTE_IMPLEMENTED_ASY U(3) 590 591 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 592 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 593 594 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 595 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 596 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 597 #define SME_IMPLEMENTED ULL(0x1) 598 #define SME2_IMPLEMENTED ULL(0x2) 599 #define SME_NOT_IMPLEMENTED ULL(0x0) 600 601 /* ID_AA64PFR2_EL1 definitions */ 602 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 603 #define ID_AA64PFR2_EL1_GCIE_SHIFT 12 604 #define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf) 605 606 /* ID_PFR1_EL1 definitions */ 607 #define ID_PFR1_VIRTEXT_SHIFT U(12) 608 #define ID_PFR1_VIRTEXT_MASK U(0xf) 609 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 610 & ID_PFR1_VIRTEXT_MASK) 611 612 /* SCTLR definitions */ 613 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 614 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 615 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 616 617 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 618 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 619 620 #define SCTLR_AARCH32_EL1_RES1 \ 621 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 622 (U(1) << 4) | (U(1) << 3)) 623 624 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 625 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 626 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 627 628 #define SCTLR_M_BIT (ULL(1) << 0) 629 #define SCTLR_A_BIT (ULL(1) << 1) 630 #define SCTLR_C_BIT (ULL(1) << 2) 631 #define SCTLR_SA_BIT (ULL(1) << 3) 632 #define SCTLR_SA0_BIT (ULL(1) << 4) 633 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 634 #define SCTLR_nAA_BIT (ULL(1) << 6) 635 #define SCTLR_ITD_BIT (ULL(1) << 7) 636 #define SCTLR_SED_BIT (ULL(1) << 8) 637 #define SCTLR_UMA_BIT (ULL(1) << 9) 638 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 639 #define SCTLR_EOS_BIT (ULL(1) << 11) 640 #define SCTLR_I_BIT (ULL(1) << 12) 641 #define SCTLR_EnDB_BIT (ULL(1) << 13) 642 #define SCTLR_DZE_BIT (ULL(1) << 14) 643 #define SCTLR_UCT_BIT (ULL(1) << 15) 644 #define SCTLR_NTWI_BIT (ULL(1) << 16) 645 #define SCTLR_NTWE_BIT (ULL(1) << 18) 646 #define SCTLR_WXN_BIT (ULL(1) << 19) 647 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 648 #define SCTLR_IESB_BIT (ULL(1) << 21) 649 #define SCTLR_EIS_BIT (ULL(1) << 22) 650 #define SCTLR_SPAN_BIT (ULL(1) << 23) 651 #define SCTLR_E0E_BIT (ULL(1) << 24) 652 #define SCTLR_EE_BIT (ULL(1) << 25) 653 #define SCTLR_UCI_BIT (ULL(1) << 26) 654 #define SCTLR_EnDA_BIT (ULL(1) << 27) 655 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 656 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 657 #define SCTLR_EnIB_BIT (ULL(1) << 30) 658 #define SCTLR_EnIA_BIT (ULL(1) << 31) 659 #define SCTLR_BT0_BIT (ULL(1) << 35) 660 #define SCTLR_BT1_BIT (ULL(1) << 36) 661 #define SCTLR_BT_BIT (ULL(1) << 36) 662 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 663 #define SCTLR_TCF0_SHIFT U(38) 664 #define SCTLR_TCF0_MASK ULL(3) 665 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 666 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 667 668 /* Tag Check Faults in EL0 have no effect on the PE */ 669 #define SCTLR_TCF0_NO_EFFECT U(0) 670 /* Tag Check Faults in EL0 cause a synchronous exception */ 671 #define SCTLR_TCF0_SYNC U(1) 672 /* Tag Check Faults in EL0 are asynchronously accumulated */ 673 #define SCTLR_TCF0_ASYNC U(2) 674 /* 675 * Tag Check Faults in EL0 cause a synchronous exception on reads, 676 * and are asynchronously accumulated on writes 677 */ 678 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 679 680 #define SCTLR_TCF_SHIFT U(40) 681 #define SCTLR_TCF_MASK ULL(3) 682 683 /* Tag Check Faults in EL1 have no effect on the PE */ 684 #define SCTLR_TCF_NO_EFFECT U(0) 685 /* Tag Check Faults in EL1 cause a synchronous exception */ 686 #define SCTLR_TCF_SYNC U(1) 687 /* Tag Check Faults in EL1 are asynchronously accumulated */ 688 #define SCTLR_TCF_ASYNC U(2) 689 /* 690 * Tag Check Faults in EL1 cause a synchronous exception on reads, 691 * and are asynchronously accumulated on writes 692 */ 693 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 694 695 #define SCTLR_ATA0_BIT (ULL(1) << 42) 696 #define SCTLR_ATA_BIT (ULL(1) << 43) 697 #define SCTLR_DSSBS_SHIFT U(44) 698 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 699 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 700 #define SCTLR_TWEDEL_SHIFT U(46) 701 #define SCTLR_TWEDEL_MASK ULL(0xf) 702 #define SCTLR_EnASR_BIT (ULL(1) << 54) 703 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 704 #define SCTLR_EnALS_BIT (ULL(1) << 56) 705 #define SCTLR_EPAN_BIT (ULL(1) << 57) 706 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 707 708 #define SCTLR2_EnPACM_BIT (ULL(1) << 7) 709 #define SCTLR2_CPTA_BIT (ULL(1) << 9) 710 #define SCTLR2_CPTM_BIT (ULL(1) << 11) 711 712 /* SCTLR2 currently has no RES1 fields so reset to 0 */ 713 #define SCTLR2_RESET_VAL ULL(0) 714 715 /* CPACR_EL1 definitions */ 716 #define CPACR_EL1_FPEN(x) ((x) << 20) 717 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 718 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 719 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 720 #define CPACR_EL1_SMEN_SHIFT U(24) 721 #define CPACR_EL1_SMEN_MASK ULL(0x3) 722 723 /* SCR definitions */ 724 #if ENABLE_FEAT_GCIE 725 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT) 726 #else 727 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 728 #endif 729 #define SCR_NSE_SHIFT U(62) 730 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 731 #define SCR_FGTEN2_BIT (UL(1) << 59) 732 #define SCR_PFAREn_BIT (UL(1) << 53) 733 #define SCR_EnFPM_BIT (ULL(1) << 50) 734 #define SCR_MECEn_BIT (UL(1) << 49) 735 #define SCR_GPF_BIT (UL(1) << 48) 736 #define SCR_D128En_BIT (UL(1) << 47) 737 #define SCR_AIEn_BIT (UL(1) << 46) 738 #define SCR_TWEDEL_SHIFT U(30) 739 #define SCR_TWEDEL_MASK ULL(0xf) 740 #define SCR_PIEN_BIT (UL(1) << 45) 741 #define SCR_SCTLR2En_BIT (UL(1) << 44) 742 #define SCR_TCR2EN_BIT (UL(1) << 43) 743 #define SCR_RCWMASKEn_BIT (UL(1) << 42) 744 #define SCR_ENTP2_SHIFT U(41) 745 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 746 #define SCR_TRNDR_BIT (UL(1) << 40) 747 #define SCR_GCSEn_BIT (UL(1) << 39) 748 #define SCR_HXEn_BIT (UL(1) << 38) 749 #define SCR_ADEn_BIT (UL(1) << 37) 750 #define SCR_EnAS0_BIT (UL(1) << 36) 751 #define SCR_AMVOFFEN_SHIFT U(35) 752 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 753 #define SCR_TWEDEn_BIT (UL(1) << 29) 754 #define SCR_ECVEN_BIT (UL(1) << 28) 755 #define SCR_FGTEN_BIT (UL(1) << 27) 756 #define SCR_ATA_BIT (UL(1) << 26) 757 #define SCR_EnSCXT_BIT (UL(1) << 25) 758 #define SCR_TID5_BIT (UL(1) << 23) 759 #define SCR_TID3_BIT (UL(1) << 22) 760 #define SCR_FIEN_BIT (UL(1) << 21) 761 #define SCR_EEL2_SHIFT U(18) 762 #define SCR_EEL2_BIT (UL(1) << SCR_EEL2_SHIFT) 763 #define SCR_API_BIT (UL(1) << 17) 764 #define SCR_APK_BIT (UL(1) << 16) 765 #define SCR_TERR_BIT (UL(1) << 15) 766 #define SCR_TWE_BIT (UL(1) << 13) 767 #define SCR_TWI_BIT (UL(1) << 12) 768 #define SCR_ST_BIT (UL(1) << 11) 769 #define SCR_RW_BIT (UL(1) << 10) 770 #define SCR_SIF_BIT (UL(1) << 9) 771 #define SCR_HCE_BIT (UL(1) << 8) 772 #define SCR_SMD_BIT (UL(1) << 7) 773 #define SCR_EA_BIT (UL(1) << 3) 774 #define SCR_FIQ_BIT (UL(1) << 2) 775 #define SCR_IRQ_BIT (UL(1) << 1) 776 #define SCR_NS_BIT (UL(1) << 0) 777 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 778 #define SCR_RESET_VAL SCR_RES1_BITS 779 780 /* MDCR_EL3 definitions */ 781 #define MDCR_EBWE_BIT (ULL(1) << 43) 782 #define MDCR_EnPMS3_BIT (ULL(1) << 42) 783 #define MDCR_PMEE(x) ((x) << 40) 784 #define MDCR_PMEE_CTRL_EL2 ULL(0x1) 785 #define MDCR_E3BREC_BIT (ULL(1) << 38) 786 #define MDCR_E3BREW_BIT (ULL(1) << 37) 787 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 788 #define MDCR_MPMX_BIT (ULL(1) << 35) 789 #define MDCR_MCCD_BIT (ULL(1) << 34) 790 #define MDCR_SBRBE_SHIFT U(32) 791 #define MDCR_SBRBE(x) ((x) << MDCR_SBRBE_SHIFT) 792 #define MDCR_SBRBE_ALL ULL(0x3) 793 #define MDCR_SBRBE_NS ULL(0x1) 794 #define MDCR_NSTB_EN_BIT (ULL(1) << 24) 795 #define MDCR_NSTB_SS_BIT (ULL(1) << 25) 796 #define MDCR_NSTBE_BIT (ULL(1) << 26) 797 #define MDCR_MTPME_BIT (ULL(1) << 28) 798 #define MDCR_TDCC_BIT (ULL(1) << 27) 799 #define MDCR_SCCD_BIT (ULL(1) << 23) 800 #define MDCR_EPMAD_BIT (ULL(1) << 21) 801 #define MDCR_EDAD_BIT (ULL(1) << 20) 802 #define MDCR_TTRF_BIT (ULL(1) << 19) 803 #define MDCR_STE_BIT (ULL(1) << 18) 804 #define MDCR_SPME_BIT (ULL(1) << 17) 805 #define MDCR_SDD_BIT (ULL(1) << 16) 806 #define MDCR_SPD32(x) ((x) << 14) 807 #define MDCR_SPD32_LEGACY ULL(0x0) 808 #define MDCR_SPD32_DISABLE ULL(0x2) 809 #define MDCR_SPD32_ENABLE ULL(0x3) 810 #define MDCR_NSPB_SS_BIT (ULL(1) << 13) 811 #define MDCR_NSPB_EN_BIT (ULL(1) << 12) 812 #define MDCR_NSPBE_BIT (ULL(1) << 11) 813 #define MDCR_TDOSA_BIT (ULL(1) << 10) 814 #define MDCR_TDA_BIT (ULL(1) << 9) 815 #define MDCR_EnPM2_BIT (ULL(1) << 7) 816 #define MDCR_TPM_BIT (ULL(1) << 6) 817 #define MDCR_RLTE_BIT (ULL(1) << 0) 818 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 819 820 /* MDCR_EL2 definitions */ 821 #define MDCR_EL2_MTPME (ULL(1) << 28) 822 #define MDCR_EL2_HLP_BIT (ULL(1) << 26) 823 #define MDCR_EL2_E2TB(x) ULL((x) << 24) 824 #define MDCR_EL2_E2TB_EL1 ULL(0x3) 825 #define MDCR_EL2_HCCD_BIT (ULL(1) << 23) 826 #define MDCR_EL2_TTRF (ULL(1) << 19) 827 #define MDCR_EL2_HPMD_BIT (ULL(1) << 17) 828 #define MDCR_EL2_TPMS (ULL(1) << 14) 829 #define MDCR_EL2_E2PB(x) ULL((x) << 12) 830 #define MDCR_EL2_E2PB_EL1 ULL(0x3) 831 #define MDCR_EL2_TDRA_BIT (ULL(1) << 11) 832 #define MDCR_EL2_TDOSA_BIT (ULL(1) << 10) 833 #define MDCR_EL2_TDA_BIT (ULL(1) << 9) 834 #define MDCR_EL2_TDE_BIT (ULL(1) << 8) 835 #define MDCR_EL2_HPME_BIT (ULL(1) << 7) 836 #define MDCR_EL2_TPM_BIT (ULL(1) << 6) 837 #define MDCR_EL2_TPMCR_BIT (ULL(1) << 5) 838 #define MDCR_EL2_HPMN_MASK ULL(0x1f) 839 #define MDCR_EL2_RESET_VAL ULL(0x0) 840 841 /* HSTR_EL2 definitions */ 842 #define HSTR_EL2_RESET_VAL U(0x0) 843 #define HSTR_EL2_T_MASK U(0xff) 844 845 /* CNTHP_CTL_EL2 definitions */ 846 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 847 #define CNTHP_CTL_RESET_VAL U(0x0) 848 849 /* VTTBR_EL2 definitions */ 850 #define VTTBR_RESET_VAL ULL(0x0) 851 #define VTTBR_VMID_MASK ULL(0xff) 852 #define VTTBR_VMID_SHIFT U(48) 853 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 854 #define VTTBR_BADDR_SHIFT U(0) 855 856 /* HCR definitions */ 857 #define HCR_RESET_VAL ULL(0x0) 858 #define HCR_AMVOFFEN_SHIFT U(51) 859 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 860 #define HCR_TEA_BIT (ULL(1) << 47) 861 #define HCR_API_BIT (ULL(1) << 41) 862 #define HCR_APK_BIT (ULL(1) << 40) 863 #define HCR_E2H_BIT (ULL(1) << 34) 864 #define HCR_HCD_BIT (ULL(1) << 29) 865 #define HCR_TGE_BIT (ULL(1) << 27) 866 #define HCR_RW_SHIFT U(31) 867 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 868 #define HCR_TWE_BIT (ULL(1) << 14) 869 #define HCR_TWI_BIT (ULL(1) << 13) 870 #define HCR_AMO_BIT (ULL(1) << 5) 871 #define HCR_IMO_BIT (ULL(1) << 4) 872 #define HCR_FMO_BIT (ULL(1) << 3) 873 874 /* ISR definitions */ 875 #define ISR_A_SHIFT U(8) 876 #define ISR_I_SHIFT U(7) 877 #define ISR_F_SHIFT U(6) 878 879 /* CNTHCTL_EL2 definitions */ 880 #define CNTHCTL_RESET_VAL U(0x0) 881 #define EVNTEN_BIT (U(1) << 2) 882 #define EL1PCEN_BIT (U(1) << 1) 883 #define EL1PCTEN_BIT (U(1) << 0) 884 885 /* CNTKCTL_EL1 definitions */ 886 #define EL0PTEN_BIT (U(1) << 9) 887 #define EL0VTEN_BIT (U(1) << 8) 888 #define EL0PCTEN_BIT (U(1) << 0) 889 #define EL0VCTEN_BIT (U(1) << 1) 890 #define EVNTEN_BIT (U(1) << 2) 891 #define EVNTDIR_BIT (U(1) << 3) 892 #define EVNTI_SHIFT U(4) 893 #define EVNTI_MASK U(0xf) 894 895 /* CPTR_EL3 definitions */ 896 #define TCPAC_BIT (U(1) << 31) 897 #define TAM_SHIFT U(30) 898 #define TAM_BIT (U(1) << TAM_SHIFT) 899 #define TTA_BIT (U(1) << 20) 900 #define ESM_BIT (U(1) << 12) 901 #define TFP_BIT (U(1) << 10) 902 #define CPTR_EZ_BIT (U(1) << 8) 903 904 #if ENABLE_FEAT_MORELLO 905 #define EC_BIT (U(1) << 9) 906 /* 907 * Even though the morello spec doesnot have TAM_BIT defined it is included 908 * to keep the definition as close to other hardware as possible. Since bit 30 909 * is reserved in Morello it should not have any effect anyways. 910 */ 911 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT | EC_BIT) & \ 912 ~(CPTR_EZ_BIT | ESM_BIT | TCPAC_BIT)) 913 #else 914 /* TCPAC is always set by default as the register is always present */ 915 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT) & \ 916 ~(CPTR_EZ_BIT | ESM_BIT | TCPAC_BIT)) 917 #endif 918 919 /* CPTR_EL2 definitions */ 920 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 921 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 922 #define CPTR_EL2_TAM_SHIFT U(30) 923 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 924 #define CPTR_EL2_SMEN_MASK ULL(0x3) 925 #define CPTR_EL2_SMEN_SHIFT U(24) 926 #define CPTR_EL2_TTA_BIT (U(1) << 20) 927 #define CPTR_EL2_ZEN_MASK ULL(0x3) 928 #define CPTR_EL2_ZEN_SHIFT U(16) 929 #define CPTR_EL2_TSM_BIT (U(1) << 12) 930 #define CPTR_EL2_TFP_BIT (ULL(1) << 10) 931 #define CPTR_EL2_TZ_BIT (ULL(1) << 8) 932 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 933 934 /* VTCR_EL2 definitions */ 935 #define VTCR_RESET_VAL U(0x0) 936 #define VTCR_EL2_MSA (U(1) << 31) 937 938 /* CPSR/SPSR definitions */ 939 #define DAIF_FIQ_BIT (U(1) << 0) 940 #define DAIF_IRQ_BIT (U(1) << 1) 941 #define DAIF_ABT_BIT (U(1) << 2) 942 #define DAIF_DBG_BIT (U(1) << 3) 943 #define SPSR_V_BIT (U(1) << 28) 944 #define SPSR_C_BIT (U(1) << 29) 945 #define SPSR_Z_BIT (U(1) << 30) 946 #define SPSR_N_BIT (U(1) << 31) 947 #define SPSR_DAIF_SHIFT U(6) 948 #define SPSR_DAIF_MASK U(0xf) 949 950 #define SPSR_AIF_SHIFT U(6) 951 #define SPSR_AIF_MASK U(0x7) 952 953 #define SPSR_E_SHIFT U(9) 954 #define SPSR_E_MASK U(0x1) 955 #define SPSR_E_LITTLE U(0x0) 956 #define SPSR_E_BIG U(0x1) 957 958 #define SPSR_T_SHIFT U(5) 959 #define SPSR_T_MASK U(0x1) 960 #define SPSR_T_ARM U(0x0) 961 #define SPSR_T_THUMB U(0x1) 962 963 #define SPSR_M_SHIFT U(4) 964 #define SPSR_M_MASK U(0x1) 965 #define SPSR_M_WIDTH U(1) 966 #define SPSR_M_AARCH64 U(0x0) 967 #define SPSR_M_AARCH32 U(0x1) 968 #define SPSR_M_EL1H U(0x5) 969 #define SPSR_M_EL2H U(0x9) 970 971 #define SPSR_EL_SHIFT U(2) 972 #define SPSR_EL_WIDTH U(2) 973 974 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 975 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 976 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 977 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 978 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 979 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 980 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 981 #define SPSR_IL_BIT BIT_64(20) 982 #define SPSR_SS_BIT BIT_64(21) 983 #define SPSR_PAN_BIT BIT_64(22) 984 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 985 #define SPSR_DIT_BIT BIT(24) 986 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 987 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 988 #define SPSR_PPEND_BIT BIT(33) 989 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 990 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 991 #define SPSR_PACM_BIT_AARCH64 BIT_64(35) 992 #define SPSR_UINJ_BIT BIT_64(36) 993 994 /* 995 * SPSR_EL2 996 * M=0x9 (0b1001 EL2h) 997 * M[4]=0 998 * DAIF=0xF Exceptions masked on entry. 999 * BTYPE=0 BTI not yet supported. 1000 * SSBS=0 Not yet supported. 1001 * IL=0 Not an illegal exception return. 1002 * SS=0 Not single stepping. 1003 * PAN=1 RMM shouldn't access Unprivileged memory when running in VHE mode. 1004 * UAO=0 1005 * DIT=0 1006 * TCO=0 1007 * NZCV=0 1008 */ 1009 #define SPSR_EL2_REALM (SPSR_M_EL2H | (0xF << SPSR_DAIF_SHIFT) | \ 1010 SPSR_PAN_BIT) 1011 1012 #define DISABLE_ALL_EXCEPTIONS \ 1013 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 1014 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 1015 1016 /* 1017 * RMR_EL3 definitions 1018 */ 1019 #define RMR_EL3_RR_BIT (U(1) << 1) 1020 #define RMR_EL3_AA64_BIT (U(1) << 0) 1021 1022 /* 1023 * HI-VECTOR address for AArch32 state 1024 */ 1025 #define HI_VECTOR_BASE U(0xFFFF0000) 1026 1027 /* 1028 * TCR definitions 1029 */ 1030 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 1031 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 1032 #define TCR_EL1_IPS_SHIFT U(32) 1033 #define TCR_EL2_PS_SHIFT U(16) 1034 #define TCR_EL3_PS_SHIFT U(16) 1035 1036 #define TCR_TxSZ_MIN ULL(16) 1037 #define TCR_TxSZ_MAX ULL(39) 1038 #define TCR_TxSZ_MAX_TTST ULL(48) 1039 1040 #define TCR_T0SZ_SHIFT U(0) 1041 #define TCR_T1SZ_SHIFT U(16) 1042 1043 /* (internal) physical address size bits in EL3/EL1 */ 1044 #define TCR_PS_BITS_4GB ULL(0x0) 1045 #define TCR_PS_BITS_64GB ULL(0x1) 1046 #define TCR_PS_BITS_1TB ULL(0x2) 1047 #define TCR_PS_BITS_4TB ULL(0x3) 1048 #define TCR_PS_BITS_16TB ULL(0x4) 1049 #define TCR_PS_BITS_256TB ULL(0x5) 1050 1051 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 1052 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 1053 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 1054 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 1055 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 1056 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 1057 1058 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 1059 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 1060 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 1061 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 1062 1063 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 1064 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 1065 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 1066 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 1067 1068 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 1069 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 1070 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 1071 1072 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 1073 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 1074 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 1075 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 1076 1077 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 1078 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 1079 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 1080 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 1081 1082 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 1083 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 1084 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 1085 1086 #define TCR_TG0_SHIFT U(14) 1087 #define TCR_TG0_MASK ULL(3) 1088 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 1089 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 1090 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 1091 1092 #define TCR_HPD_BIT (ULL(1) << 24) 1093 #define TCR_HWU59_BIT (ULL(1) << 25) 1094 #define TCR_HWU60_BIT (ULL(1) << 26) 1095 #define TCR_HWU61_BIT (ULL(1) << 27) 1096 #define TCR_HWU62_BIT (ULL(1) << 28) 1097 1098 #define TCR_TG1_SHIFT U(30) 1099 #define TCR_TG1_MASK ULL(3) 1100 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 1101 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 1102 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 1103 1104 #define TCR_EPD0_BIT (ULL(1) << 7) 1105 #define TCR_EPD1_BIT (ULL(1) << 23) 1106 1107 #define MODE_SP_SHIFT U(0x0) 1108 #define MODE_SP_MASK U(0x1) 1109 #define MODE_SP_EL0 U(0x0) 1110 #define MODE_SP_ELX U(0x1) 1111 1112 #define MODE_RW_SHIFT U(0x4) 1113 #define MODE_RW_MASK U(0x1) 1114 #define MODE_RW_64 U(0x0) 1115 #define MODE_RW_32 U(0x1) 1116 1117 #define MODE_EL_SHIFT U(0x2) 1118 #define MODE_EL_MASK U(0x3) 1119 #define MODE_EL_WIDTH U(0x2) 1120 #define MODE_EL3 U(0x3) 1121 #define MODE_EL2 U(0x2) 1122 #define MODE_EL1 U(0x1) 1123 #define MODE_EL0 U(0x0) 1124 1125 #define MODE32_SHIFT U(0) 1126 #define MODE32_MASK U(0xf) 1127 #define MODE32_usr U(0x0) 1128 #define MODE32_fiq U(0x1) 1129 #define MODE32_irq U(0x2) 1130 #define MODE32_svc U(0x3) 1131 #define MODE32_mon U(0x6) 1132 #define MODE32_abt U(0x7) 1133 #define MODE32_hyp U(0xa) 1134 #define MODE32_und U(0xb) 1135 #define MODE32_sys U(0xf) 1136 1137 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 1138 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 1139 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 1140 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 1141 1142 #define SPSR_64(el, sp, daif) \ 1143 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 1144 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 1145 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 1146 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 1147 (~(SPSR_SSBS_BIT_AARCH64))) 1148 1149 #define SPSR_MODE32(mode, isa, endian, aif) \ 1150 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 1151 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 1152 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 1153 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 1154 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 1155 (~(SPSR_SSBS_BIT_AARCH32))) 1156 1157 /* 1158 * TTBR Definitions 1159 */ 1160 #define TTBR_CNP_BIT ULL(0x1) 1161 1162 /* 1163 * CTR_EL0 definitions 1164 */ 1165 #define CTR_CWG_SHIFT U(24) 1166 #define CTR_CWG_MASK U(0xf) 1167 #define CTR_ERG_SHIFT U(20) 1168 #define CTR_ERG_MASK U(0xf) 1169 #define CTR_DMINLINE_SHIFT U(16) 1170 #define CTR_DMINLINE_MASK U(0xf) 1171 #define CTR_L1IP_SHIFT U(14) 1172 #define CTR_L1IP_MASK U(0x3) 1173 #define CTR_IMINLINE_SHIFT U(0) 1174 #define CTR_IMINLINE_MASK U(0xf) 1175 1176 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 1177 1178 /* Physical timer control register bit fields shifts and masks */ 1179 #define CNTP_CTL_ENABLE_SHIFT U(0) 1180 #define CNTP_CTL_IMASK_SHIFT U(1) 1181 #define CNTP_CTL_ISTATUS_SHIFT U(2) 1182 1183 #define CNTP_CTL_ENABLE_MASK U(1) 1184 #define CNTP_CTL_IMASK_MASK U(1) 1185 #define CNTP_CTL_ISTATUS_MASK U(1) 1186 1187 /* Physical timer control macros */ 1188 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 1189 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 1190 1191 /* Exception Syndrome register bits and bobs */ 1192 #define ESR_EC_SHIFT U(26) 1193 #define ESR_EC_MASK U(0x3f) 1194 #define ESR_EC_LENGTH U(6) 1195 #define ESR_EC_WIDTH U(6) 1196 #define ESR_ISS_SHIFT U(0) 1197 #define ESR_ISS_LENGTH U(25) 1198 #define ESR_IL_BIT (U(1) << 25) 1199 #define EC_UNKNOWN U(0x0) 1200 #define EC_WFE_WFI U(0x1) 1201 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 1202 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 1203 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 1204 #define EC_AARCH32_CP14_LDC_STC U(0x6) 1205 #define EC_FP_SIMD U(0x7) 1206 #define EC_AARCH32_CP10_MRC U(0x8) 1207 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1208 #define EC_ILLEGAL U(0xe) 1209 #define EC_AARCH32_SVC U(0x11) 1210 #define EC_AARCH32_HVC U(0x12) 1211 #define EC_AARCH32_SMC U(0x13) 1212 #define EC_AARCH64_SVC U(0x15) 1213 #define EC_AARCH64_HVC U(0x16) 1214 #define EC_AARCH64_SMC U(0x17) 1215 #define EC_AARCH64_SYS U(0x18) 1216 #define EC_IMP_DEF_EL3 U(0x1f) 1217 #define EC_IABORT_LOWER_EL U(0x20) 1218 #define EC_IABORT_CUR_EL U(0x21) 1219 #define EC_PC_ALIGN U(0x22) 1220 #define EC_DABORT_LOWER_EL U(0x24) 1221 #define EC_DABORT_CUR_EL U(0x25) 1222 #define EC_SP_ALIGN U(0x26) 1223 #define EC_AARCH32_FP U(0x28) 1224 #define EC_AARCH64_FP U(0x2c) 1225 #define EC_SERROR U(0x2f) 1226 #define EC_BRK U(0x3c) 1227 1228 /* 1229 * External Abort bit in Instruction and Data Aborts synchronous exception 1230 * syndromes. 1231 */ 1232 #define ESR_ISS_EABORT_EA_BIT U(9) 1233 1234 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1235 1236 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1237 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1238 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1239 1240 /******************************************************************************* 1241 * Definitions of register offsets, fields and macros for CPU system 1242 * instructions. 1243 ******************************************************************************/ 1244 1245 #define TLBI_ADDR_SHIFT U(12) 1246 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1247 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1248 1249 /******************************************************************************* 1250 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1251 * system level implementation of the Generic Timer. 1252 ******************************************************************************/ 1253 #define CNTCTLBASE_CNTFRQ U(0x0) 1254 #define CNTNSAR U(0x4) 1255 #define CNTNSAR_NS_SHIFT(x) (x) 1256 1257 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1258 #define CNTACR_RPCT_SHIFT U(0x0) 1259 #define CNTACR_RVCT_SHIFT U(0x1) 1260 #define CNTACR_RFRQ_SHIFT U(0x2) 1261 #define CNTACR_RVOFF_SHIFT U(0x3) 1262 #define CNTACR_RWVT_SHIFT U(0x4) 1263 #define CNTACR_RWPT_SHIFT U(0x5) 1264 1265 /******************************************************************************* 1266 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1267 * system level implementation of the Generic Timer. 1268 ******************************************************************************/ 1269 /* Physical Count register. */ 1270 #define CNTPCT_LO U(0x0) 1271 /* Counter Frequency register. */ 1272 #define CNTBASEN_CNTFRQ U(0x10) 1273 /* Physical Timer CompareValue register. */ 1274 #define CNTP_CVAL_LO U(0x20) 1275 /* Physical Timer Control register. */ 1276 #define CNTP_CTL U(0x2c) 1277 1278 /* PMCR_EL0 definitions */ 1279 #define PMCR_EL0_RESET_VAL U(0x0) 1280 #define PMCR_EL0_N_SHIFT U(11) 1281 #define PMCR_EL0_N_MASK U(0x1f) 1282 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1283 #define PMCR_EL0_LP_BIT (U(1) << 7) 1284 #define PMCR_EL0_LC_BIT (U(1) << 6) 1285 #define PMCR_EL0_DP_BIT (U(1) << 5) 1286 #define PMCR_EL0_X_BIT (U(1) << 4) 1287 #define PMCR_EL0_D_BIT (U(1) << 3) 1288 #define PMCR_EL0_C_BIT (U(1) << 2) 1289 #define PMCR_EL0_P_BIT (U(1) << 1) 1290 #define PMCR_EL0_E_BIT (U(1) << 0) 1291 1292 /******************************************************************************* 1293 * Definitions for system register interface to SVE 1294 ******************************************************************************/ 1295 #define ZCR_EL3 S3_6_C1_C2_0 1296 #define ZCR_EL2 S3_4_C1_C2_0 1297 1298 /* ZCR_EL3 definitions */ 1299 #define ZCR_EL3_LEN_MASK U(0xf) 1300 1301 /* ZCR_EL2 definitions */ 1302 #define ZCR_EL2_LEN_MASK U(0xf) 1303 1304 /******************************************************************************* 1305 * Definitions for system register interface to SME as needed in EL3 1306 ******************************************************************************/ 1307 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1308 #define SMCR_EL3 S3_6_C1_C2_6 1309 #define SVCR S3_3_C4_C2_2 1310 1311 /* ID_AA64SMFR0_EL1 definitions */ 1312 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1313 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1314 #define SME_FA64_IMPLEMENTED U(0x1) 1315 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1316 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1317 #define SME_INST_IMPLEMENTED ULL(0x0) 1318 #define SME2_INST_IMPLEMENTED ULL(0x1) 1319 1320 /* SMCR_ELx definitions */ 1321 #define SMCR_ELX_LEN_SHIFT U(0) 1322 #define SMCR_ELX_LEN_MAX U(0x1ff) 1323 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1324 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1325 1326 /******************************************************************************* 1327 * Definitions of MAIR encodings for device and normal memory 1328 ******************************************************************************/ 1329 /* 1330 * MAIR encodings for device memory attributes. 1331 */ 1332 #define MAIR_DEV_nGnRnE ULL(0x0) 1333 #define MAIR_DEV_nGnRE ULL(0x4) 1334 #define MAIR_DEV_nGRE ULL(0x8) 1335 #define MAIR_DEV_GRE ULL(0xc) 1336 1337 /* 1338 * MAIR encodings for normal memory attributes. 1339 * 1340 * Cache Policy 1341 * WT: Write Through 1342 * WB: Write Back 1343 * NC: Non-Cacheable 1344 * 1345 * Transient Hint 1346 * NTR: Non-Transient 1347 * TR: Transient 1348 * 1349 * Allocation Policy 1350 * RA: Read Allocate 1351 * WA: Write Allocate 1352 * RWA: Read and Write Allocate 1353 * NA: No Allocation 1354 */ 1355 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1356 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1357 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1358 #define MAIR_NORM_NC ULL(0x4) 1359 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1360 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1361 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1362 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1363 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1364 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1365 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1366 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1367 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1368 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1369 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1370 1371 #define MAIR_NORM_OUTER_SHIFT U(4) 1372 1373 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1374 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1375 1376 /* PAR_EL1 fields */ 1377 #define PAR_F_SHIFT U(0) 1378 #define PAR_F_MASK ULL(0x1) 1379 1380 #define PAR_D128_ADDR_MASK GENMASK(55, 12) /* 44-bits-wide page address */ 1381 #define PAR_ADDR_MASK GENMASK(51, 12) /* 40-bits-wide page address */ 1382 1383 /******************************************************************************* 1384 * Definitions for system register interface to SPE 1385 ******************************************************************************/ 1386 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1387 1388 /******************************************************************************* 1389 * Definitions for system register interface, shifts and masks for MPAM 1390 ******************************************************************************/ 1391 #define MPAMIDR_EL1 S3_0_C10_C4_4 1392 #define MPAM2_EL2 S3_4_C10_C5_0 1393 #define MPAMHCR_EL2 S3_4_C10_C4_0 1394 #define MPAM3_EL3 S3_6_C10_C5_0 1395 1396 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1397 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1398 /******************************************************************************* 1399 * Definitions for system register interface to AMU for FEAT_AMUv1 1400 ******************************************************************************/ 1401 #define AMCR_EL0 S3_3_C13_C2_0 1402 #define AMCFGR_EL0 S3_3_C13_C2_1 1403 #define AMCGCR_EL0 S3_3_C13_C2_2 1404 #define AMUSERENR_EL0 S3_3_C13_C2_3 1405 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1406 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1407 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1408 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1409 1410 /* Activity Monitor Group 0 Event Counter Registers */ 1411 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1412 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1413 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1414 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1415 1416 /* Activity Monitor Group 0 Event Type Registers */ 1417 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1418 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1419 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1420 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1421 1422 /* Activity Monitor Group 1 Event Counter Registers */ 1423 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1424 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1425 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1426 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1427 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1428 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1429 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1430 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1431 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1432 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1433 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1434 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1435 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1436 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1437 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1438 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1439 1440 /* Activity Monitor Group 1 Event Type Registers */ 1441 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1442 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1443 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1444 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1445 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1446 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1447 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1448 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1449 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1450 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1451 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1452 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1453 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1454 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1455 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1456 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1457 1458 /* AMCNTENSET0_EL0 definitions */ 1459 #define AMCNTENSET0_EL0_Pn_ALWAYS_ON ULL(0x3) 1460 #define AMCNTENSET0_EL0_Pn_CONTEXTED ULL(0xc) 1461 #define AMCNTENSET0_EL0_Pn_ALL ULL(0xf) 1462 1463 /* AMCNTENSET1_EL0 definitions */ 1464 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1465 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1466 1467 /* AMCNTENCLR0_EL0 definitions */ 1468 #define AMCNTENCLR0_EL0_Pn_ALWAYS_ON ULL(0x3) 1469 #define AMCNTENCLR0_EL0_Pn_CONTEXTED ULL(0xc) 1470 #define AMCNTENCLR0_EL0_Pn_ALL ULL(0xf) 1471 1472 /* AMCNTENCLR1_EL0 definitions */ 1473 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1474 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1475 1476 /* AMCFGR_EL0 definitions */ 1477 #define AMCFGR_EL0_NCG_SHIFT U(28) 1478 #define AMCFGR_EL0_NCG_MASK U(0xf) 1479 #define AMCFGR_EL0_N_SHIFT U(0) 1480 #define AMCFGR_EL0_N_MASK U(0xff) 1481 1482 /* AMCGCR_EL0 definitions */ 1483 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1484 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1485 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1486 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1487 1488 /* MPAM register definitions */ 1489 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1490 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1491 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1492 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1493 1494 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1495 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1496 1497 #define MPAMIDR_HAS_BW_CTRL_BIT (ULL(1) << 56) 1498 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1499 1500 /* MPAM_PE_BW_CTRL register definitions */ 1501 #define MPAMBW2_EL2 S3_4_C10_C5_4 1502 #define MPAMBW2_EL2_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1503 #define MPAMBW2_EL2_ENABLED_BIT (ULL(1) << 62) 1504 #define MPAMBW2_EL2_HARDLIM_BIT (ULL(1) << 61) 1505 #define MPAMBW2_EL2_NTRAP_MPAMBWIDR_EL1_BIT (ULL(1) << 52) 1506 #define MPAMBW2_EL2_NTRAP_MPAMBW0_EL1_BIT (ULL(1) << 51) 1507 #define MPAMBW2_EL2_NTRAP_MPAMBW1_EL1_BIT (ULL(1) << 50) 1508 #define MPAMBW2_EL2_NTRAP_MPAMBWSM_EL1_BIT (ULL(1) << 49) 1509 1510 #define MPAMBW3_EL3 S3_6_C10_C5_4 1511 #define MPAMBW3_EL3_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1512 #define MPAMBW3_EL3_ENABLED_BIT (ULL(1) << 62) 1513 #define MPAMBW3_EL3_HARDLIM_BIT (ULL(1) << 61) 1514 #define MPAMBW3_EL3_NTRAPLOWER_BIT (ULL(1) << 49) 1515 1516 /******************************************************************************* 1517 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1518 ******************************************************************************/ 1519 1520 /* Definition for register defining which virtual offsets are implemented. */ 1521 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1522 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1523 #define AMCG1IDR_CTR_SHIFT U(0) 1524 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1525 #define AMCG1IDR_VOFF_SHIFT U(16) 1526 1527 /* New bit added to AMCR_EL0 */ 1528 #define AMCR_CG1RZ_SHIFT U(17) 1529 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1530 1531 /* 1532 * Definitions for virtual offset registers for architected activity monitor 1533 * event counters. 1534 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1535 */ 1536 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1537 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1538 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1539 1540 /* 1541 * Definitions for virtual offset registers for auxiliary activity monitor event 1542 * counters. 1543 */ 1544 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1545 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1546 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1547 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1548 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1549 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1550 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1551 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1552 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1553 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1554 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1555 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1556 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1557 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1558 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1559 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1560 1561 /******************************************************************************* 1562 * Realm management extension register definitions 1563 ******************************************************************************/ 1564 #define GPCCR_EL3 S3_6_C2_C1_6 1565 #define GPTBR_EL3 S3_6_C2_C1_4 1566 1567 #define SCXTNUM_EL2 S3_4_C13_C0_7 1568 #define SCXTNUM_EL1 S3_0_C13_C0_7 1569 #define SCXTNUM_EL0 S3_3_C13_C0_7 1570 1571 /******************************************************************************* 1572 * RAS system registers 1573 ******************************************************************************/ 1574 #define DISR_EL1 S3_0_C12_C1_1 1575 #define DISR_A_BIT U(31) 1576 1577 #define ERRIDR_EL1 S3_0_C5_C3_0 1578 #define ERRIDR_MASK U(0xffff) 1579 1580 #define ERRSELR_EL1 S3_0_C5_C3_1 1581 1582 /* System register access to Standard Error Record registers */ 1583 #define ERXFR_EL1 S3_0_C5_C4_0 1584 #define ERXCTLR_EL1 S3_0_C5_C4_1 1585 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1586 #define ERXADDR_EL1 S3_0_C5_C4_3 1587 #define ERXPFGF_EL1 S3_0_C5_C4_4 1588 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1589 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1590 #define ERXMISC0_EL1 S3_0_C5_C5_0 1591 #define ERXMISC1_EL1 S3_0_C5_C5_1 1592 1593 #define ERXCTLR_ED_SHIFT U(0) 1594 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1595 #define ERXCTLR_UE_BIT (U(1) << 4) 1596 1597 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1598 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1599 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1600 1601 /******************************************************************************* 1602 * Armv8.3 Pointer Authentication Registers 1603 ******************************************************************************/ 1604 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1605 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1606 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1607 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1608 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1609 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1610 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1611 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1612 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1613 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1614 1615 /******************************************************************************* 1616 * Armv8.4 Data Independent Timing Registers 1617 ******************************************************************************/ 1618 #define DIT S3_3_C4_C2_5 1619 #define DIT_BIT BIT(24) 1620 1621 /******************************************************************************* 1622 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1623 ******************************************************************************/ 1624 #define SSBS S3_3_C4_C2_6 1625 1626 /******************************************************************************* 1627 * Armv8.5 - Memory Tagging Extension Registers 1628 ******************************************************************************/ 1629 #define TFSRE0_EL1 S3_0_C5_C6_1 1630 #define TFSR_EL1 S3_0_C5_C6_0 1631 #define RGSR_EL1 S3_0_C1_C0_5 1632 #define GCR_EL1 S3_0_C1_C0_6 1633 1634 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1635 1636 /******************************************************************************* 1637 * Armv8.5 - Random Number Generator Registers 1638 ******************************************************************************/ 1639 #define RNDR S3_3_C2_C4_0 1640 #define RNDRRS S3_3_C2_C4_1 1641 1642 /******************************************************************************* 1643 * FEAT_HCX - Extended Hypervisor Configuration Register 1644 ******************************************************************************/ 1645 #define HCRX_EL2 S3_4_C1_C2_2 1646 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1647 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1648 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1649 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1650 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1651 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1652 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1653 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1654 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1655 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1656 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1657 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1658 #define HCRX_EL2_INIT_VAL ULL(0x0) 1659 1660 /******************************************************************************* 1661 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1662 ******************************************************************************/ 1663 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1664 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1665 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1666 1667 /******************************************************************************* 1668 * FEAT_TCR2 - Extended Translation Control Registers 1669 ******************************************************************************/ 1670 #define TCR2_EL1 S3_0_C2_C0_3 1671 #define TCR2_EL2 S3_4_C2_C0_3 1672 1673 /******************************************************************************* 1674 * Permission indirection and overlay Registers 1675 ******************************************************************************/ 1676 1677 #define PIRE0_EL1 S3_0_C10_C2_2 1678 #define PIRE0_EL2 S3_4_C10_C2_2 1679 #define PIR_EL1 S3_0_C10_C2_3 1680 #define PIR_EL2 S3_4_C10_C2_3 1681 #define POR_EL1 S3_0_C10_C2_4 1682 #define POR_EL2 S3_4_C10_C2_4 1683 #define S2PIR_EL2 S3_4_C10_C2_5 1684 #define S2POR_EL1 S3_0_C10_C2_5 1685 1686 /******************************************************************************* 1687 * FEAT_GCS - Guarded Control Stack Registers 1688 ******************************************************************************/ 1689 #define GCSCR_EL2 S3_4_C2_C5_0 1690 #define GCSPR_EL2 S3_4_C2_C5_1 1691 #define GCSCR_EL1 S3_0_C2_C5_0 1692 #define GCSCRE0_EL1 S3_0_C2_C5_2 1693 #define GCSPR_EL1 S3_0_C2_C5_1 1694 #define GCSPR_EL0 S3_3_C2_C5_1 1695 1696 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1697 1698 /******************************************************************************* 1699 * FEAT_TRF - Trace Filter Control Registers 1700 ******************************************************************************/ 1701 #define TRFCR_EL2 S3_4_C1_C2_1 1702 #define TRFCR_EL1 S3_0_C1_C2_1 1703 1704 /******************************************************************************* 1705 * FEAT_THE - Translation Hardening Extension Registers 1706 ******************************************************************************/ 1707 #define RCWMASK_EL1 S3_0_C13_C0_6 1708 #define RCWSMASK_EL1 S3_0_C13_C0_3 1709 1710 /******************************************************************************* 1711 * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers 1712 ******************************************************************************/ 1713 #define SCTLR2_EL3 S3_6_C1_C0_3 1714 #define SCTLR2_EL2 S3_4_C1_C0_3 1715 #define SCTLR2_EL1 S3_0_C1_C0_3 1716 1717 /******************************************************************************* 1718 * FEAT_BRBE - Branch Record Buffer Extension Registers 1719 ******************************************************************************/ 1720 #define BRBCR_EL2 S2_4_C9_C0_0 1721 1722 /******************************************************************************* 1723 * FEAT_LS64_ACCDATA - LoadStore64B with status data 1724 ******************************************************************************/ 1725 #define ACCDATA_EL1 S3_0_C13_C0_5 1726 1727 /******************************************************************************* 1728 * Definitions for DynamicIQ Shared Unit registers 1729 ******************************************************************************/ 1730 #define CLUSTERPWRDN_EL1 S3_0_C15_C3_6 1731 1732 /******************************************************************************* 1733 * FEAT_FPMR - Floating point Mode Register 1734 ******************************************************************************/ 1735 #define FPMR S3_3_C4_C4_2 1736 1737 /* CLUSTERPWRDN_EL1 register definitions */ 1738 #define DSU_CLUSTER_PWR_OFF 0 1739 #define DSU_CLUSTER_PWR_ON 1 1740 #define DSU_CLUSTER_PWR_MASK U(1) 1741 #define DSU_CLUSTER_MEM_RET BIT(1) 1742 1743 /* CLUSTERPMMDCR register definitions */ 1744 #define CLUSTERPMMDCR_SPME U(1) 1745 1746 /******************************************************************************* 1747 * Definitions for CPU Power/Performance Management registers 1748 ******************************************************************************/ 1749 1750 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1751 #define CPUPPMCR_EL3_MPMMPINCTL_BIT BIT(0) 1752 1753 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1754 #define CPUMPMMCR_EL3_MPMM_EN_BIT BIT(0) 1755 1756 /* alternative system register encoding for the "sb" speculation barrier */ 1757 #define SYSREG_SB S0_3_C3_C0_7 1758 1759 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1760 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1761 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1762 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1763 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1764 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1765 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1766 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1767 #define CLUSTERPMMDCR_EL3 S3_6_C15_C6_3 1768 1769 #define CLUSTERPMCR_E_BIT BIT(0) 1770 #define CLUSTERPMCR_N_SHIFT U(11) 1771 #define CLUSTERPMCR_N_MASK U(0x1f) 1772 1773 /******************************************************************************* 1774 * FEAT_MEC - Memory Encryption Contexts 1775 ******************************************************************************/ 1776 #define MECIDR_EL2 S3_4_C10_C8_7 1777 #define MECIDR_EL2_MECIDWidthm1_MASK U(0xf) 1778 #define MECIDR_EL2_MECIDWidthm1_SHIFT U(0) 1779 1780 /****************************************************************************** 1781 * FEAT_FGWTE3 - Fine Grained Write Trap 1782 ******************************************************************************/ 1783 #define FGWTE3_EL3 S3_6_C1_C1_5 1784 1785 /* FGWTE3_EL3 Defintions */ 1786 #define FGWTE3_EL3_VBAR_EL3_BIT (U(1) << 21) 1787 #define FGWTE3_EL3_TTBR0_EL3_BIT (U(1) << 20) 1788 #define FGWTE3_EL3_TPIDR_EL3_BIT (U(1) << 19) 1789 #define FGWTE3_EL3_TCR_EL3_BIT (U(1) << 18) 1790 #define FGWTE3_EL3_SPMROOTCR_EL3_BIT (U(1) << 17) 1791 #define FGWTE3_EL3_SCTLR2_EL3_BIT (U(1) << 16) 1792 #define FGWTE3_EL3_SCTLR_EL3_BIT (U(1) << 15) 1793 #define FGWTE3_EL3_PIR_EL3_BIT (U(1) << 14) 1794 #define FGWTE3_EL3_MECID_RL_A_EL3_BIT (U(1) << 12) 1795 #define FGWTE3_EL3_MAIR2_EL3_BIT (U(1) << 10) 1796 #define FGWTE3_EL3_MAIR_EL3_BIT (U(1) << 9) 1797 #define FGWTE3_EL3_GPTBR_EL3_BIT (U(1) << 8) 1798 #define FGWTE3_EL3_GPCCR_EL3_BIT (U(1) << 7) 1799 #define FGWTE3_EL3_GCSPR_EL3_BIT (U(1) << 6) 1800 #define FGWTE3_EL3_GCSCR_EL3_BIT (U(1) << 5) 1801 #define FGWTE3_EL3_AMAIR2_EL3_BIT (U(1) << 4) 1802 #define FGWTE3_EL3_AMAIR_EL3_BIT (U(1) << 3) 1803 #define FGWTE3_EL3_AFSR1_EL3_BIT (U(1) << 2) 1804 #define FGWTE3_EL3_AFSR0_EL3_BIT (U(1) << 1) 1805 #define FGWTE3_EL3_ACTLR_EL3_BIT (U(1) << 0) 1806 1807 #define FGWTE3_EL3_EARLY_INIT_VAL ( \ 1808 FGWTE3_EL3_VBAR_EL3_BIT | \ 1809 FGWTE3_EL3_TTBR0_EL3_BIT | \ 1810 FGWTE3_EL3_SPMROOTCR_EL3_BIT | \ 1811 FGWTE3_EL3_SCTLR2_EL3_BIT | \ 1812 FGWTE3_EL3_PIR_EL3_BIT | \ 1813 FGWTE3_EL3_MECID_RL_A_EL3_BIT | \ 1814 FGWTE3_EL3_MAIR2_EL3_BIT | \ 1815 FGWTE3_EL3_MAIR_EL3_BIT | \ 1816 FGWTE3_EL3_GPTBR_EL3_BIT | \ 1817 FGWTE3_EL3_GPCCR_EL3_BIT | \ 1818 FGWTE3_EL3_GCSPR_EL3_BIT | \ 1819 FGWTE3_EL3_GCSCR_EL3_BIT | \ 1820 FGWTE3_EL3_AMAIR2_EL3_BIT | \ 1821 FGWTE3_EL3_AMAIR_EL3_BIT | \ 1822 FGWTE3_EL3_AFSR1_EL3_BIT | \ 1823 FGWTE3_EL3_AFSR0_EL3_BIT) 1824 1825 #if HW_ASSISTED_COHERENCY 1826 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT FGWTE3_EL3_SCTLR_EL3_BIT | 1827 #else 1828 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT 1829 #endif 1830 1831 #if !(CRASH_REPORTING) 1832 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT FGWTE3_EL3_TPIDR_EL3_BIT | 1833 #else 1834 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT 1835 #endif 1836 1837 #define FGWTE3_EL3_LATE_INIT_VAL ( \ 1838 FGWTE3_EL3_EARLY_INIT_VAL | \ 1839 FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT \ 1840 FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT \ 1841 FGWTE3_EL3_TCR_EL3_BIT | \ 1842 FGWTE3_EL3_ACTLR_EL3_BIT) 1843 1844 #endif /* ARCH_H */ 1845