1 #ifndef __ODY_CSRS_DSS_H__ 2 #define __ODY_CSRS_DSS_H__ 3 /* This file is auto-generated. Do not edit */ 4 5 /***********************license start*********************************** 6 * Copyright (C) 2021-2026 Marvell. 7 * SPDX-License-Identifier: BSD-3-Clause 8 * https://spdx.org/licenses 9 ***********************license end**************************************/ 10 11 12 /** 13 * @file 14 * 15 * Configuration and status register (CSR) address and type definitions for 16 * DSS. 17 * 18 * This file is auto generated. Do not edit. 19 * 20 */ 21 22 /** 23 * Enumeration dss_bar_e 24 * 25 * DSS Base Address Register Enumeration 26 * Enumerates the base address registers. 27 */ 28 #define ODY_DSS_BAR_E_DSSX_PF_BAR0(a) (0x87e1b0000000ll + 0x1000000ll * (a)) 29 #define ODY_DSS_BAR_E_DSSX_PF_BAR0_SIZE 0x400000ull 30 #define ODY_DSS_BAR_E_DSSX_PF_BAR2(a) (0x87e1b0800000ll + 0x1000000ll * (a)) 31 #define ODY_DSS_BAR_E_DSSX_PF_BAR2_SIZE 0x800000ull 32 #define ODY_DSS_BAR_E_DSSX_PF_BAR4(a) (0x87e1b0700000ll + 0x1000000ll * (a)) 33 #define ODY_DSS_BAR_E_DSSX_PF_BAR4_SIZE 0x100000ull 34 35 /** 36 * Enumeration dss_chb_mpamf_err_e 37 * 38 * MPAM Error Code Enumeration 39 * Error codes to be reported in MPAMF_ESR (if DSS_DDRCTL_REGB_CHB_MPAM_NS/S_MPAMF_IDR_32[HAS_ESR]==1) 40 */ 41 #define ODY_DSS_CHB_MPAMF_ERR_E_MONITOR_RANGE (5) 42 #define ODY_DSS_CHB_MPAMF_ERR_E_MSMONCFG_ID_RANGE (3) 43 #define ODY_DSS_CHB_MPAMF_ERR_E_NO_ERROR (0) 44 #define ODY_DSS_CHB_MPAMF_ERR_E_PARTID_SEL_RANGE (1) 45 #define ODY_DSS_CHB_MPAMF_ERR_E_REQ_PARTID_RANGE (2) 46 #define ODY_DSS_CHB_MPAMF_ERR_E_REQ_PMG_RANGE (4) 47 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_10 (0xa) 48 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_11 (0xb) 49 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_12 (0xc) 50 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_13 (0xd) 51 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_14 (0xe) 52 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_15 (0xf) 53 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_6 (6) 54 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_7 (7) 55 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_8 (8) 56 #define ODY_DSS_CHB_MPAMF_ERR_E_RESERVED_ERRCODE_9 (9) 57 58 /** 59 * Enumeration dss_int_vec_e 60 * 61 * DSS MSI-X Vector Enumeration 62 * Enumerates the MSI-X interrupt vectors. 63 */ 64 #define ODY_DSS_INT_VEC_E_DSS_INT (0) 65 #define ODY_DSS_INT_VEC_E_DSS_MCT_INT (1) 66 #define ODY_DSS_INT_VEC_E_DSS_MPAM_NS_INT (4) 67 #define ODY_DSS_INT_VEC_E_DSS_MPAM_S_INT (3) 68 #define ODY_DSS_INT_VEC_E_DSS_PERF_CNT_INT (2) 69 70 /** 71 * Register (RSL) dss#_cbusy_cnt_clr# 72 * 73 * CBUSY Counter Clear Register 74 * CBUSY Counter clear register. 75 */ 76 union ody_dssx_cbusy_cnt_clrx { 77 uint64_t u; 78 struct ody_dssx_cbusy_cnt_clrx_s { 79 uint64_t cbusy_cnt_clr : 1; 80 uint64_t reserved_1_63 : 63; 81 } s; 82 /* struct ody_dssx_cbusy_cnt_clrx_s cn; */ 83 }; 84 typedef union ody_dssx_cbusy_cnt_clrx ody_dssx_cbusy_cnt_clrx_t; 85 86 static inline uint64_t ODY_DSSX_CBUSY_CNT_CLRX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 87 static inline uint64_t ODY_DSSX_CBUSY_CNT_CLRX(uint64_t a, uint64_t b) 88 { 89 if ((a <= 19) && (b <= 3)) 90 return 0x87e1b0020320ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 91 __ody_csr_fatal("DSSX_CBUSY_CNT_CLRX", 2, a, b, 0, 0, 0, 0); 92 } 93 94 #define typedef_ODY_DSSX_CBUSY_CNT_CLRX(a, b) ody_dssx_cbusy_cnt_clrx_t 95 #define bustype_ODY_DSSX_CBUSY_CNT_CLRX(a, b) CSR_TYPE_RSL 96 #define basename_ODY_DSSX_CBUSY_CNT_CLRX(a, b) "DSSX_CBUSY_CNT_CLRX" 97 #define device_bar_ODY_DSSX_CBUSY_CNT_CLRX(a, b) 0x0 /* PF_BAR0 */ 98 #define busnum_ODY_DSSX_CBUSY_CNT_CLRX(a, b) (a) 99 #define arguments_ODY_DSSX_CBUSY_CNT_CLRX(a, b) (a), (b), -1, -1 100 101 /** 102 * Register (RSL) dss#_cbusy_cnt_ctrl# 103 * 104 * CBUSY Counter Control Register 105 * CBUSY Counter control register. 106 */ 107 union ody_dssx_cbusy_cnt_ctrlx { 108 uint64_t u; 109 struct ody_dssx_cbusy_cnt_ctrlx_s { 110 uint64_t cbusy_cnt_en : 1; 111 uint64_t cbusy_cnt_interrupt_en : 1; 112 uint64_t cbusy_cnt_wrap_value : 1; 113 uint64_t reserved_3_9 : 7; 114 uint64_t count_cbusy_value_0 : 1; 115 uint64_t count_cbusy_value_1 : 1; 116 uint64_t count_cbusy_value_2 : 1; 117 uint64_t count_cbusy_value_3 : 1; 118 uint64_t count_cbusy_from_dat_flit : 1; 119 uint64_t count_cbusy_from_rsp_flit : 1; 120 uint64_t reserved_16_63 : 48; 121 } s; 122 /* struct ody_dssx_cbusy_cnt_ctrlx_s cn; */ 123 }; 124 typedef union ody_dssx_cbusy_cnt_ctrlx ody_dssx_cbusy_cnt_ctrlx_t; 125 126 static inline uint64_t ODY_DSSX_CBUSY_CNT_CTRLX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 127 static inline uint64_t ODY_DSSX_CBUSY_CNT_CTRLX(uint64_t a, uint64_t b) 128 { 129 if ((a <= 19) && (b <= 3)) 130 return 0x87e1b0020300ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 131 __ody_csr_fatal("DSSX_CBUSY_CNT_CTRLX", 2, a, b, 0, 0, 0, 0); 132 } 133 134 #define typedef_ODY_DSSX_CBUSY_CNT_CTRLX(a, b) ody_dssx_cbusy_cnt_ctrlx_t 135 #define bustype_ODY_DSSX_CBUSY_CNT_CTRLX(a, b) CSR_TYPE_RSL 136 #define basename_ODY_DSSX_CBUSY_CNT_CTRLX(a, b) "DSSX_CBUSY_CNT_CTRLX" 137 #define device_bar_ODY_DSSX_CBUSY_CNT_CTRLX(a, b) 0x0 /* PF_BAR0 */ 138 #define busnum_ODY_DSSX_CBUSY_CNT_CTRLX(a, b) (a) 139 #define arguments_ODY_DSSX_CBUSY_CNT_CTRLX(a, b) (a), (b), -1, -1 140 141 /** 142 * Register (RSL) dss#_cbusy_cnt_val# 143 * 144 * CBUSY Counter Value Register 145 * Counter value of chosen CBUSY events. 146 */ 147 union ody_dssx_cbusy_cnt_valx { 148 uint64_t u; 149 struct ody_dssx_cbusy_cnt_valx_s { 150 uint64_t cbusy_counter_value : 63; 151 uint64_t cbusy_cnt_overflow : 1; 152 } s; 153 /* struct ody_dssx_cbusy_cnt_valx_s cn; */ 154 }; 155 typedef union ody_dssx_cbusy_cnt_valx ody_dssx_cbusy_cnt_valx_t; 156 157 static inline uint64_t ODY_DSSX_CBUSY_CNT_VALX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 158 static inline uint64_t ODY_DSSX_CBUSY_CNT_VALX(uint64_t a, uint64_t b) 159 { 160 if ((a <= 19) && (b <= 3)) 161 return 0x87e1b0020340ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 162 __ody_csr_fatal("DSSX_CBUSY_CNT_VALX", 2, a, b, 0, 0, 0, 0); 163 } 164 165 #define typedef_ODY_DSSX_CBUSY_CNT_VALX(a, b) ody_dssx_cbusy_cnt_valx_t 166 #define bustype_ODY_DSSX_CBUSY_CNT_VALX(a, b) CSR_TYPE_RSL 167 #define basename_ODY_DSSX_CBUSY_CNT_VALX(a, b) "DSSX_CBUSY_CNT_VALX" 168 #define device_bar_ODY_DSSX_CBUSY_CNT_VALX(a, b) 0x0 /* PF_BAR0 */ 169 #define busnum_ODY_DSSX_CBUSY_CNT_VALX(a, b) (a) 170 #define arguments_ODY_DSSX_CBUSY_CNT_VALX(a, b) (a), (b), -1, -1 171 172 /** 173 * Register (RSL) dss#_clk_en 174 * 175 * DSS Clock Enable Register 176 * Control of DSS domain's clock enables. 177 */ 178 union ody_dssx_clk_en { 179 uint64_t u; 180 struct ody_dssx_clk_en_s { 181 uint64_t s_mc_core_clk_en : 1; 182 uint64_t s_phy_ref_clk_en : 1; 183 uint64_t s_rclk_en : 1; 184 uint64_t s_apb_clk_en : 1; 185 uint64_t s_mct_clk_en : 1; 186 uint64_t reserved_5_63 : 59; 187 } s; 188 /* struct ody_dssx_clk_en_s cn; */ 189 }; 190 typedef union ody_dssx_clk_en ody_dssx_clk_en_t; 191 192 static inline uint64_t ODY_DSSX_CLK_EN(uint64_t a) __attribute__ ((pure, always_inline)); 193 static inline uint64_t ODY_DSSX_CLK_EN(uint64_t a) 194 { 195 if (a <= 19) 196 return 0x87e1b0000020ll + 0x1000000ll * ((a) & 0x1f); 197 __ody_csr_fatal("DSSX_CLK_EN", 1, a, 0, 0, 0, 0, 0); 198 } 199 200 #define typedef_ODY_DSSX_CLK_EN(a) ody_dssx_clk_en_t 201 #define bustype_ODY_DSSX_CLK_EN(a) CSR_TYPE_RSL 202 #define basename_ODY_DSSX_CLK_EN(a) "DSSX_CLK_EN" 203 #define device_bar_ODY_DSSX_CLK_EN(a) 0x0 /* PF_BAR0 */ 204 #define busnum_ODY_DSSX_CLK_EN(a) (a) 205 #define arguments_ODY_DSSX_CLK_EN(a) (a), -1, -1, -1 206 207 /** 208 * Register (RSL) dss#_ctrl 209 * 210 * DSS Control Register 211 * General control register. 212 */ 213 union ody_dssx_ctrl { 214 uint64_t u; 215 struct ody_dssx_ctrl_s { 216 uint64_t reserved_0_2 : 3; 217 uint64_t s_force_kbd_0_chi_read_buf_ram : 1; 218 uint64_t ecc_dispsn : 1; 219 uint64_t ecc_discor : 1; 220 uint64_t dmc_mdc_dis : 1; 221 uint64_t reserved_7_63 : 57; 222 } s; 223 /* struct ody_dssx_ctrl_s cn; */ 224 }; 225 typedef union ody_dssx_ctrl ody_dssx_ctrl_t; 226 227 static inline uint64_t ODY_DSSX_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 228 static inline uint64_t ODY_DSSX_CTRL(uint64_t a) 229 { 230 if (a <= 19) 231 return 0x87e1b0000030ll + 0x1000000ll * ((a) & 0x1f); 232 __ody_csr_fatal("DSSX_CTRL", 1, a, 0, 0, 0, 0, 0); 233 } 234 235 #define typedef_ODY_DSSX_CTRL(a) ody_dssx_ctrl_t 236 #define bustype_ODY_DSSX_CTRL(a) CSR_TYPE_RSL 237 #define basename_ODY_DSSX_CTRL(a) "DSSX_CTRL" 238 #define device_bar_ODY_DSSX_CTRL(a) 0x0 /* PF_BAR0 */ 239 #define busnum_ODY_DSSX_CTRL(a) (a) 240 #define arguments_ODY_DSSX_CTRL(a) (a), -1, -1, -1 241 242 /** 243 * Register (RSL) dss#_dbg_status_0 244 * 245 * Debug status 0 bits Register 246 * Reserved. 247 */ 248 union ody_dssx_dbg_status_0 { 249 uint64_t u; 250 struct ody_dssx_dbg_status_0_s { 251 uint64_t dbg_rd_retry_rank : 1; 252 uint64_t reserved_1_63 : 63; 253 } s; 254 /* struct ody_dssx_dbg_status_0_s cn; */ 255 }; 256 typedef union ody_dssx_dbg_status_0 ody_dssx_dbg_status_0_t; 257 258 static inline uint64_t ODY_DSSX_DBG_STATUS_0(uint64_t a) __attribute__ ((pure, always_inline)); 259 static inline uint64_t ODY_DSSX_DBG_STATUS_0(uint64_t a) 260 { 261 if (a <= 19) 262 return 0x87e1b0000120ll + 0x1000000ll * ((a) & 0x1f); 263 __ody_csr_fatal("DSSX_DBG_STATUS_0", 1, a, 0, 0, 0, 0, 0); 264 } 265 266 #define typedef_ODY_DSSX_DBG_STATUS_0(a) ody_dssx_dbg_status_0_t 267 #define bustype_ODY_DSSX_DBG_STATUS_0(a) CSR_TYPE_RSL 268 #define basename_ODY_DSSX_DBG_STATUS_0(a) "DSSX_DBG_STATUS_0" 269 #define device_bar_ODY_DSSX_DBG_STATUS_0(a) 0x0 /* PF_BAR0 */ 270 #define busnum_ODY_DSSX_DBG_STATUS_0(a) (a) 271 #define arguments_ODY_DSSX_DBG_STATUS_0(a) (a), -1, -1, -1 272 273 /** 274 * Register (RSL) dss#_dbg_status_1 275 * 276 * Debug status 1 bits Register 277 * Reserved. 278 */ 279 union ody_dssx_dbg_status_1 { 280 uint64_t u; 281 struct ody_dssx_dbg_status_1_s { 282 uint64_t dbg_prank_pre_pd : 2; 283 uint64_t dbg_prank_act_pd : 2; 284 uint64_t reserved_4_63 : 60; 285 } s; 286 /* struct ody_dssx_dbg_status_1_s cn; */ 287 }; 288 typedef union ody_dssx_dbg_status_1 ody_dssx_dbg_status_1_t; 289 290 static inline uint64_t ODY_DSSX_DBG_STATUS_1(uint64_t a) __attribute__ ((pure, always_inline)); 291 static inline uint64_t ODY_DSSX_DBG_STATUS_1(uint64_t a) 292 { 293 if (a <= 19) 294 return 0x87e1b0000128ll + 0x1000000ll * ((a) & 0x1f); 295 __ody_csr_fatal("DSSX_DBG_STATUS_1", 1, a, 0, 0, 0, 0, 0); 296 } 297 298 #define typedef_ODY_DSSX_DBG_STATUS_1(a) ody_dssx_dbg_status_1_t 299 #define bustype_ODY_DSSX_DBG_STATUS_1(a) CSR_TYPE_RSL 300 #define basename_ODY_DSSX_DBG_STATUS_1(a) "DSSX_DBG_STATUS_1" 301 #define device_bar_ODY_DSSX_DBG_STATUS_1(a) 0x0 /* PF_BAR0 */ 302 #define busnum_ODY_DSSX_DBG_STATUS_1(a) (a) 303 #define arguments_ODY_DSSX_DBG_STATUS_1(a) (a), -1, -1, -1 304 305 /** 306 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap1 307 * 308 * DSS Ddrctl Regb Addr Map0 Addrmap1 Register 309 * Address Map Register 1 310 */ 311 union ody_dssx_ddrctl_regb_addr_map0_addrmap1 { 312 uint32_t u; 313 struct ody_dssx_ddrctl_regb_addr_map0_addrmap1_s { 314 uint32_t addrmap_cs_bit0 : 6; 315 uint32_t reserved_6_31 : 26; 316 } s; 317 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap1_s cn; */ 318 }; 319 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap1 ody_dssx_ddrctl_regb_addr_map0_addrmap1_t; 320 321 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1(uint64_t a) __attribute__ ((pure, always_inline)); 322 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1(uint64_t a) 323 { 324 if (a <= 19) 325 return 0x87e1b0230004ll + 0x1000000ll * ((a) & 0x1f); 326 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1", 1, a, 0, 0, 0, 0, 0); 327 } 328 329 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1(a) ody_dssx_ddrctl_regb_addr_map0_addrmap1_t 330 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1(a) CSR_TYPE_RSL32b 331 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1" 332 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1(a) 0x0 /* PF_BAR0 */ 333 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1(a) (a) 334 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP1(a) (a), -1, -1, -1 335 336 /** 337 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap10 338 * 339 * DSS Ddrctl Regb Addr Map0 Addrmap10 Register 340 * Address Map Register 10 341 */ 342 union ody_dssx_ddrctl_regb_addr_map0_addrmap10 { 343 uint32_t u; 344 struct ody_dssx_ddrctl_regb_addr_map0_addrmap10_s { 345 uint32_t addrmap_row_b2 : 5; 346 uint32_t reserved_5_7 : 3; 347 uint32_t addrmap_row_b3 : 5; 348 uint32_t reserved_13_15 : 3; 349 uint32_t addrmap_row_b4 : 5; 350 uint32_t reserved_21_23 : 3; 351 uint32_t addrmap_row_b5 : 5; 352 uint32_t reserved_29_31 : 3; 353 } s; 354 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap10_s cn; */ 355 }; 356 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap10 ody_dssx_ddrctl_regb_addr_map0_addrmap10_t; 357 358 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10(uint64_t a) __attribute__ ((pure, always_inline)); 359 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10(uint64_t a) 360 { 361 if (a <= 19) 362 return 0x87e1b0230028ll + 0x1000000ll * ((a) & 0x1f); 363 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10", 1, a, 0, 0, 0, 0, 0); 364 } 365 366 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10(a) ody_dssx_ddrctl_regb_addr_map0_addrmap10_t 367 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10(a) CSR_TYPE_RSL32b 368 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10" 369 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10(a) 0x0 /* PF_BAR0 */ 370 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10(a) (a) 371 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP10(a) (a), -1, -1, -1 372 373 /** 374 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap11 375 * 376 * DSS Ddrctl Regb Addr Map0 Addrmap11 Register 377 * Address Map Register 11 378 */ 379 union ody_dssx_ddrctl_regb_addr_map0_addrmap11 { 380 uint32_t u; 381 struct ody_dssx_ddrctl_regb_addr_map0_addrmap11_s { 382 uint32_t addrmap_row_b0 : 5; 383 uint32_t reserved_5_7 : 3; 384 uint32_t addrmap_row_b1 : 5; 385 uint32_t reserved_13_31 : 19; 386 } s; 387 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap11_s cn; */ 388 }; 389 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap11 ody_dssx_ddrctl_regb_addr_map0_addrmap11_t; 390 391 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11(uint64_t a) __attribute__ ((pure, always_inline)); 392 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11(uint64_t a) 393 { 394 if (a <= 19) 395 return 0x87e1b023002cll + 0x1000000ll * ((a) & 0x1f); 396 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11", 1, a, 0, 0, 0, 0, 0); 397 } 398 399 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11(a) ody_dssx_ddrctl_regb_addr_map0_addrmap11_t 400 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11(a) CSR_TYPE_RSL32b 401 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11" 402 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11(a) 0x0 /* PF_BAR0 */ 403 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11(a) (a) 404 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP11(a) (a), -1, -1, -1 405 406 /** 407 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap12 408 * 409 * DSS Ddrctl Regb Addr Map0 Addrmap12 Register 410 * Address Map Register 12 411 */ 412 union ody_dssx_ddrctl_regb_addr_map0_addrmap12 { 413 uint32_t u; 414 struct ody_dssx_ddrctl_regb_addr_map0_addrmap12_s { 415 uint32_t nonbinary_device_density : 3; 416 uint32_t reserved_3_31 : 29; 417 } s; 418 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap12_s cn; */ 419 }; 420 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap12 ody_dssx_ddrctl_regb_addr_map0_addrmap12_t; 421 422 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12(uint64_t a) __attribute__ ((pure, always_inline)); 423 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12(uint64_t a) 424 { 425 if (a <= 19) 426 return 0x87e1b0230030ll + 0x1000000ll * ((a) & 0x1f); 427 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12", 1, a, 0, 0, 0, 0, 0); 428 } 429 430 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12(a) ody_dssx_ddrctl_regb_addr_map0_addrmap12_t 431 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12(a) CSR_TYPE_RSL32b 432 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12" 433 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12(a) 0x0 /* PF_BAR0 */ 434 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12(a) (a) 435 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP12(a) (a), -1, -1, -1 436 437 /** 438 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap3 439 * 440 * DSS Ddrctl Regb Addr Map0 Addrmap3 Register 441 * Address Map Register 3 442 */ 443 union ody_dssx_ddrctl_regb_addr_map0_addrmap3 { 444 uint32_t u; 445 struct ody_dssx_ddrctl_regb_addr_map0_addrmap3_s { 446 uint32_t addrmap_bank_b0 : 6; 447 uint32_t reserved_6_7 : 2; 448 uint32_t addrmap_bank_b1 : 6; 449 uint32_t reserved_14_31 : 18; 450 } s; 451 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap3_s cn; */ 452 }; 453 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap3 ody_dssx_ddrctl_regb_addr_map0_addrmap3_t; 454 455 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3(uint64_t a) __attribute__ ((pure, always_inline)); 456 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3(uint64_t a) 457 { 458 if (a <= 19) 459 return 0x87e1b023000cll + 0x1000000ll * ((a) & 0x1f); 460 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3", 1, a, 0, 0, 0, 0, 0); 461 } 462 463 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3(a) ody_dssx_ddrctl_regb_addr_map0_addrmap3_t 464 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3(a) CSR_TYPE_RSL32b 465 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3" 466 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3(a) 0x0 /* PF_BAR0 */ 467 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3(a) (a) 468 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP3(a) (a), -1, -1, -1 469 470 /** 471 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap4 472 * 473 * DSS Ddrctl Regb Addr Map0 Addrmap4 Register 474 * Address Map Register 4 475 */ 476 union ody_dssx_ddrctl_regb_addr_map0_addrmap4 { 477 uint32_t u; 478 struct ody_dssx_ddrctl_regb_addr_map0_addrmap4_s { 479 uint32_t addrmap_bg_b0 : 6; 480 uint32_t reserved_6_7 : 2; 481 uint32_t addrmap_bg_b1 : 6; 482 uint32_t reserved_14_15 : 2; 483 uint32_t addrmap_bg_b2 : 6; 484 uint32_t reserved_22_31 : 10; 485 } s; 486 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap4_s cn; */ 487 }; 488 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap4 ody_dssx_ddrctl_regb_addr_map0_addrmap4_t; 489 490 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4(uint64_t a) __attribute__ ((pure, always_inline)); 491 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4(uint64_t a) 492 { 493 if (a <= 19) 494 return 0x87e1b0230010ll + 0x1000000ll * ((a) & 0x1f); 495 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4", 1, a, 0, 0, 0, 0, 0); 496 } 497 498 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4(a) ody_dssx_ddrctl_regb_addr_map0_addrmap4_t 499 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4(a) CSR_TYPE_RSL32b 500 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4" 501 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4(a) 0x0 /* PF_BAR0 */ 502 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4(a) (a) 503 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP4(a) (a), -1, -1, -1 504 505 /** 506 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap5 507 * 508 * DSS Ddrctl Regb Addr Map0 Addrmap5 Register 509 * Address Map Register 5 510 */ 511 union ody_dssx_ddrctl_regb_addr_map0_addrmap5 { 512 uint32_t u; 513 struct ody_dssx_ddrctl_regb_addr_map0_addrmap5_s { 514 uint32_t addrmap_col_b7 : 5; 515 uint32_t reserved_5_7 : 3; 516 uint32_t addrmap_col_b8 : 5; 517 uint32_t reserved_13_15 : 3; 518 uint32_t addrmap_col_b9 : 5; 519 uint32_t reserved_21_23 : 3; 520 uint32_t addrmap_col_b10 : 5; 521 uint32_t reserved_29_31 : 3; 522 } s; 523 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap5_s cn; */ 524 }; 525 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap5 ody_dssx_ddrctl_regb_addr_map0_addrmap5_t; 526 527 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5(uint64_t a) __attribute__ ((pure, always_inline)); 528 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5(uint64_t a) 529 { 530 if (a <= 19) 531 return 0x87e1b0230014ll + 0x1000000ll * ((a) & 0x1f); 532 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5", 1, a, 0, 0, 0, 0, 0); 533 } 534 535 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5(a) ody_dssx_ddrctl_regb_addr_map0_addrmap5_t 536 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5(a) CSR_TYPE_RSL32b 537 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5" 538 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5(a) 0x0 /* PF_BAR0 */ 539 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5(a) (a) 540 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP5(a) (a), -1, -1, -1 541 542 /** 543 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap6 544 * 545 * DSS Ddrctl Regb Addr Map0 Addrmap6 Register 546 * Address Map Register 6 547 */ 548 union ody_dssx_ddrctl_regb_addr_map0_addrmap6 { 549 uint32_t u; 550 struct ody_dssx_ddrctl_regb_addr_map0_addrmap6_s { 551 uint32_t addrmap_col_b3 : 4; 552 uint32_t reserved_4_7 : 4; 553 uint32_t addrmap_col_b4 : 4; 554 uint32_t reserved_12_15 : 4; 555 uint32_t addrmap_col_b5 : 4; 556 uint32_t reserved_20_23 : 4; 557 uint32_t addrmap_col_b6 : 4; 558 uint32_t reserved_28_31 : 4; 559 } s; 560 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap6_s cn; */ 561 }; 562 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap6 ody_dssx_ddrctl_regb_addr_map0_addrmap6_t; 563 564 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6(uint64_t a) __attribute__ ((pure, always_inline)); 565 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6(uint64_t a) 566 { 567 if (a <= 19) 568 return 0x87e1b0230018ll + 0x1000000ll * ((a) & 0x1f); 569 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6", 1, a, 0, 0, 0, 0, 0); 570 } 571 572 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6(a) ody_dssx_ddrctl_regb_addr_map0_addrmap6_t 573 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6(a) CSR_TYPE_RSL32b 574 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6" 575 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6(a) 0x0 /* PF_BAR0 */ 576 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6(a) (a) 577 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP6(a) (a), -1, -1, -1 578 579 /** 580 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap7 581 * 582 * DSS Ddrctl Regb Addr Map0 Addrmap7 Register 583 * Address Map Register 7 584 */ 585 union ody_dssx_ddrctl_regb_addr_map0_addrmap7 { 586 uint32_t u; 587 struct ody_dssx_ddrctl_regb_addr_map0_addrmap7_s { 588 uint32_t addrmap_row_b14 : 5; 589 uint32_t reserved_5_7 : 3; 590 uint32_t addrmap_row_b15 : 5; 591 uint32_t reserved_13_15 : 3; 592 uint32_t addrmap_row_b16 : 5; 593 uint32_t reserved_21_23 : 3; 594 uint32_t addrmap_row_b17 : 5; 595 uint32_t reserved_29_31 : 3; 596 } s; 597 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap7_s cn; */ 598 }; 599 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap7 ody_dssx_ddrctl_regb_addr_map0_addrmap7_t; 600 601 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7(uint64_t a) __attribute__ ((pure, always_inline)); 602 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7(uint64_t a) 603 { 604 if (a <= 19) 605 return 0x87e1b023001cll + 0x1000000ll * ((a) & 0x1f); 606 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7", 1, a, 0, 0, 0, 0, 0); 607 } 608 609 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7(a) ody_dssx_ddrctl_regb_addr_map0_addrmap7_t 610 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7(a) CSR_TYPE_RSL32b 611 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7" 612 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7(a) 0x0 /* PF_BAR0 */ 613 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7(a) (a) 614 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP7(a) (a), -1, -1, -1 615 616 /** 617 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap8 618 * 619 * DSS Ddrctl Regb Addr Map0 Addrmap8 Register 620 * Address Map Register 8 621 */ 622 union ody_dssx_ddrctl_regb_addr_map0_addrmap8 { 623 uint32_t u; 624 struct ody_dssx_ddrctl_regb_addr_map0_addrmap8_s { 625 uint32_t addrmap_row_b10 : 5; 626 uint32_t reserved_5_7 : 3; 627 uint32_t addrmap_row_b11 : 5; 628 uint32_t reserved_13_15 : 3; 629 uint32_t addrmap_row_b12 : 5; 630 uint32_t reserved_21_23 : 3; 631 uint32_t addrmap_row_b13 : 5; 632 uint32_t reserved_29_31 : 3; 633 } s; 634 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap8_s cn; */ 635 }; 636 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap8 ody_dssx_ddrctl_regb_addr_map0_addrmap8_t; 637 638 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8(uint64_t a) __attribute__ ((pure, always_inline)); 639 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8(uint64_t a) 640 { 641 if (a <= 19) 642 return 0x87e1b0230020ll + 0x1000000ll * ((a) & 0x1f); 643 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8", 1, a, 0, 0, 0, 0, 0); 644 } 645 646 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8(a) ody_dssx_ddrctl_regb_addr_map0_addrmap8_t 647 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8(a) CSR_TYPE_RSL32b 648 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8" 649 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8(a) 0x0 /* PF_BAR0 */ 650 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8(a) (a) 651 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP8(a) (a), -1, -1, -1 652 653 /** 654 * Register (RSL32b) dss#_ddrctl_regb_addr_map0_addrmap9 655 * 656 * DSS Ddrctl Regb Addr Map0 Addrmap9 Register 657 * Address Map Register 9 658 */ 659 union ody_dssx_ddrctl_regb_addr_map0_addrmap9 { 660 uint32_t u; 661 struct ody_dssx_ddrctl_regb_addr_map0_addrmap9_s { 662 uint32_t addrmap_row_b6 : 5; 663 uint32_t reserved_5_7 : 3; 664 uint32_t addrmap_row_b7 : 5; 665 uint32_t reserved_13_15 : 3; 666 uint32_t addrmap_row_b8 : 5; 667 uint32_t reserved_21_23 : 3; 668 uint32_t addrmap_row_b9 : 5; 669 uint32_t reserved_29_31 : 3; 670 } s; 671 /* struct ody_dssx_ddrctl_regb_addr_map0_addrmap9_s cn; */ 672 }; 673 typedef union ody_dssx_ddrctl_regb_addr_map0_addrmap9 ody_dssx_ddrctl_regb_addr_map0_addrmap9_t; 674 675 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9(uint64_t a) __attribute__ ((pure, always_inline)); 676 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9(uint64_t a) 677 { 678 if (a <= 19) 679 return 0x87e1b0230024ll + 0x1000000ll * ((a) & 0x1f); 680 __ody_csr_fatal("DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9", 1, a, 0, 0, 0, 0, 0); 681 } 682 683 #define typedef_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9(a) ody_dssx_ddrctl_regb_addr_map0_addrmap9_t 684 #define bustype_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9(a) CSR_TYPE_RSL32b 685 #define basename_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9(a) "DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9" 686 #define device_bar_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9(a) 0x0 /* PF_BAR0 */ 687 #define busnum_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9(a) (a) 688 #define arguments_ODY_DSSX_DDRCTL_REGB_ADDR_MAP0_ADDRMAP9(a) (a), -1, -1, -1 689 690 /** 691 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pcfgqos0 692 * 693 * DSS Ddrctl Regb Arb Port0 Pcfgqos0 Register 694 * Reserved. 695 */ 696 union ody_dssx_ddrctl_regb_arb_port0_pcfgqos0 { 697 uint32_t u; 698 struct ody_dssx_ddrctl_regb_arb_port0_pcfgqos0_s { 699 uint32_t rqos_map_level1 : 4; 700 uint32_t reserved_4_15 : 12; 701 uint32_t rqos_map_region0 : 2; 702 uint32_t reserved_18_19 : 2; 703 uint32_t rqos_map_region1 : 2; 704 uint32_t reserved_22_31 : 10; 705 } s; 706 /* struct ody_dssx_ddrctl_regb_arb_port0_pcfgqos0_s cn; */ 707 }; 708 typedef union ody_dssx_ddrctl_regb_arb_port0_pcfgqos0 ody_dssx_ddrctl_regb_arb_port0_pcfgqos0_t; 709 710 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0(uint64_t a) __attribute__ ((pure, always_inline)); 711 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0(uint64_t a) 712 { 713 if (a <= 19) 714 return 0x87e1b0220094ll + 0x1000000ll * ((a) & 0x1f); 715 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0", 1, a, 0, 0, 0, 0, 0); 716 } 717 718 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0(a) ody_dssx_ddrctl_regb_arb_port0_pcfgqos0_t 719 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0(a) CSR_TYPE_RSL32b 720 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0" 721 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0(a) 0x0 /* PF_BAR0 */ 722 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0(a) (a) 723 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS0(a) (a), -1, -1, -1 724 725 /** 726 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pcfgqos1 727 * 728 * DSS Ddrctl Regb Arb Port0 Pcfgqos1 Register 729 * Reserved. 730 */ 731 union ody_dssx_ddrctl_regb_arb_port0_pcfgqos1 { 732 uint32_t u; 733 struct ody_dssx_ddrctl_regb_arb_port0_pcfgqos1_s { 734 uint32_t rqos_map_timeoutb : 11; 735 uint32_t reserved_11_15 : 5; 736 uint32_t rqos_map_timeoutr : 11; 737 uint32_t reserved_27_31 : 5; 738 } s; 739 /* struct ody_dssx_ddrctl_regb_arb_port0_pcfgqos1_s cn; */ 740 }; 741 typedef union ody_dssx_ddrctl_regb_arb_port0_pcfgqos1 ody_dssx_ddrctl_regb_arb_port0_pcfgqos1_t; 742 743 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1(uint64_t a) __attribute__ ((pure, always_inline)); 744 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1(uint64_t a) 745 { 746 if (a <= 19) 747 return 0x87e1b0220098ll + 0x1000000ll * ((a) & 0x1f); 748 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1", 1, a, 0, 0, 0, 0, 0); 749 } 750 751 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1(a) ody_dssx_ddrctl_regb_arb_port0_pcfgqos1_t 752 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1(a) CSR_TYPE_RSL32b 753 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1" 754 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1(a) 0x0 /* PF_BAR0 */ 755 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1(a) (a) 756 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGQOS1(a) (a), -1, -1, -1 757 758 /** 759 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pcfgwqos0 760 * 761 * DSS Ddrctl Regb Arb Port0 Pcfgwqos0 Register 762 * Port n Write QoS Configuration Register 0 763 */ 764 union ody_dssx_ddrctl_regb_arb_port0_pcfgwqos0 { 765 uint32_t u; 766 struct ody_dssx_ddrctl_regb_arb_port0_pcfgwqos0_s { 767 uint32_t wqos_map_level1 : 4; 768 uint32_t reserved_4_7 : 4; 769 uint32_t wqos_map_level2 : 4; 770 uint32_t reserved_12_15 : 4; 771 uint32_t wqos_map_region0 : 2; 772 uint32_t reserved_18_19 : 2; 773 uint32_t wqos_map_region1 : 2; 774 uint32_t reserved_22_23 : 2; 775 uint32_t wqos_map_region2 : 2; 776 uint32_t reserved_26_31 : 6; 777 } s; 778 /* struct ody_dssx_ddrctl_regb_arb_port0_pcfgwqos0_s cn; */ 779 }; 780 typedef union ody_dssx_ddrctl_regb_arb_port0_pcfgwqos0 ody_dssx_ddrctl_regb_arb_port0_pcfgwqos0_t; 781 782 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0(uint64_t a) __attribute__ ((pure, always_inline)); 783 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0(uint64_t a) 784 { 785 if (a <= 19) 786 return 0x87e1b022009cll + 0x1000000ll * ((a) & 0x1f); 787 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0", 1, a, 0, 0, 0, 0, 0); 788 } 789 790 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0(a) ody_dssx_ddrctl_regb_arb_port0_pcfgwqos0_t 791 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0(a) CSR_TYPE_RSL32b 792 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0" 793 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0(a) 0x0 /* PF_BAR0 */ 794 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0(a) (a) 795 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS0(a) (a), -1, -1, -1 796 797 /** 798 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pcfgwqos1 799 * 800 * DSS Ddrctl Regb Arb Port0 Pcfgwqos1 Register 801 * Port n Write QoS Configuration Register 1 802 */ 803 union ody_dssx_ddrctl_regb_arb_port0_pcfgwqos1 { 804 uint32_t u; 805 struct ody_dssx_ddrctl_regb_arb_port0_pcfgwqos1_s { 806 uint32_t wqos_map_timeout1 : 11; 807 uint32_t reserved_11_15 : 5; 808 uint32_t wqos_map_timeout2 : 11; 809 uint32_t reserved_27_31 : 5; 810 } s; 811 /* struct ody_dssx_ddrctl_regb_arb_port0_pcfgwqos1_s cn; */ 812 }; 813 typedef union ody_dssx_ddrctl_regb_arb_port0_pcfgwqos1 ody_dssx_ddrctl_regb_arb_port0_pcfgwqos1_t; 814 815 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1(uint64_t a) __attribute__ ((pure, always_inline)); 816 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1(uint64_t a) 817 { 818 if (a <= 19) 819 return 0x87e1b02200a0ll + 0x1000000ll * ((a) & 0x1f); 820 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1", 1, a, 0, 0, 0, 0, 0); 821 } 822 823 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1(a) ody_dssx_ddrctl_regb_arb_port0_pcfgwqos1_t 824 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1(a) CSR_TYPE_RSL32b 825 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1" 826 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1(a) 0x0 /* PF_BAR0 */ 827 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1(a) (a) 828 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCFGWQOS1(a) (a), -1, -1, -1 829 830 /** 831 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbcbusyh 832 * 833 * DSS Ddrctl Regb Arb Port0 Pchbcbusyh Register 834 * CHB Port CBUSY CAM HPR Threshold register 835 */ 836 union ody_dssx_ddrctl_regb_arb_port0_pchbcbusyh { 837 uint32_t u; 838 struct ody_dssx_ddrctl_regb_arb_port0_pchbcbusyh_s { 839 uint32_t cam_busy_threshold_hpr : 7; 840 uint32_t reserved_7_9 : 3; 841 uint32_t cam_free_threshold_hpr : 7; 842 uint32_t reserved_17_19 : 3; 843 uint32_t cam_middle_threshold_hpr : 7; 844 uint32_t reserved_27_31 : 5; 845 } s; 846 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbcbusyh_s cn; */ 847 }; 848 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbcbusyh ody_dssx_ddrctl_regb_arb_port0_pchbcbusyh_t; 849 850 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH(uint64_t a) __attribute__ ((pure, always_inline)); 851 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH(uint64_t a) 852 { 853 if (a <= 19) 854 return 0x87e1b0220920ll + 0x1000000ll * ((a) & 0x1f); 855 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH", 1, a, 0, 0, 0, 0, 0); 856 } 857 858 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH(a) ody_dssx_ddrctl_regb_arb_port0_pchbcbusyh_t 859 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH(a) CSR_TYPE_RSL32b 860 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH" 861 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH(a) 0x0 /* PF_BAR0 */ 862 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH(a) (a) 863 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYH(a) (a), -1, -1, -1 864 865 /** 866 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbcbusyl 867 * 868 * DSS Ddrctl Regb Arb Port0 Pchbcbusyl Register 869 * CHB Port CBUSY CAM LPR Threshold register 870 */ 871 union ody_dssx_ddrctl_regb_arb_port0_pchbcbusyl { 872 uint32_t u; 873 struct ody_dssx_ddrctl_regb_arb_port0_pchbcbusyl_s { 874 uint32_t cam_busy_threshold_lpr : 7; 875 uint32_t reserved_7_9 : 3; 876 uint32_t cam_free_threshold_lpr : 7; 877 uint32_t reserved_17_19 : 3; 878 uint32_t cam_middle_threshold_lpr : 7; 879 uint32_t reserved_27_31 : 5; 880 } s; 881 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbcbusyl_s cn; */ 882 }; 883 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbcbusyl ody_dssx_ddrctl_regb_arb_port0_pchbcbusyl_t; 884 885 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL(uint64_t a) __attribute__ ((pure, always_inline)); 886 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL(uint64_t a) 887 { 888 if (a <= 19) 889 return 0x87e1b0220924ll + 0x1000000ll * ((a) & 0x1f); 890 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL", 1, a, 0, 0, 0, 0, 0); 891 } 892 893 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL(a) ody_dssx_ddrctl_regb_arb_port0_pchbcbusyl_t 894 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL(a) CSR_TYPE_RSL32b 895 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL" 896 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL(a) 0x0 /* PF_BAR0 */ 897 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL(a) (a) 898 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYL(a) (a), -1, -1, -1 899 900 /** 901 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbcbusyw 902 * 903 * DSS Ddrctl Regb Arb Port0 Pchbcbusyw Register 904 * CHB Port CBUSY CAM WR Threshold register 905 */ 906 union ody_dssx_ddrctl_regb_arb_port0_pchbcbusyw { 907 uint32_t u; 908 struct ody_dssx_ddrctl_regb_arb_port0_pchbcbusyw_s { 909 uint32_t cam_busy_threshold_wr : 7; 910 uint32_t reserved_7_9 : 3; 911 uint32_t cam_free_threshold_wr : 7; 912 uint32_t reserved_17_19 : 3; 913 uint32_t cam_middle_threshold_wr : 7; 914 uint32_t reserved_27_31 : 5; 915 } s; 916 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbcbusyw_s cn; */ 917 }; 918 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbcbusyw ody_dssx_ddrctl_regb_arb_port0_pchbcbusyw_t; 919 920 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW(uint64_t a) __attribute__ ((pure, always_inline)); 921 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW(uint64_t a) 922 { 923 if (a <= 19) 924 return 0x87e1b0220928ll + 0x1000000ll * ((a) & 0x1f); 925 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW", 1, a, 0, 0, 0, 0, 0); 926 } 927 928 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW(a) ody_dssx_ddrctl_regb_arb_port0_pchbcbusyw_t 929 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW(a) CSR_TYPE_RSL32b 930 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW" 931 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW(a) 0x0 /* PF_BAR0 */ 932 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW(a) (a) 933 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBCBUSYW(a) (a), -1, -1, -1 934 935 /** 936 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchblctrl 937 * 938 * DSS Ddrctl Regb Arb Port0 Pchblctrl Register 939 * CHB Port Link Control register 940 */ 941 union ody_dssx_ddrctl_regb_arb_port0_pchblctrl { 942 uint32_t u; 943 struct ody_dssx_ddrctl_regb_arb_port0_pchblctrl_s { 944 uint32_t txsactive_en : 1; 945 uint32_t reserved_1_31 : 31; 946 } s; 947 /* struct ody_dssx_ddrctl_regb_arb_port0_pchblctrl_s cn; */ 948 }; 949 typedef union ody_dssx_ddrctl_regb_arb_port0_pchblctrl ody_dssx_ddrctl_regb_arb_port0_pchblctrl_t; 950 951 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL(uint64_t a) __attribute__ ((pure, always_inline)); 952 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL(uint64_t a) 953 { 954 if (a <= 19) 955 return 0x87e1b0220900ll + 0x1000000ll * ((a) & 0x1f); 956 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL", 1, a, 0, 0, 0, 0, 0); 957 } 958 959 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL(a) ody_dssx_ddrctl_regb_arb_port0_pchblctrl_t 960 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL(a) CSR_TYPE_RSL32b 961 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL" 962 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL(a) 0x0 /* PF_BAR0 */ 963 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL(a) (a) 964 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLCTRL(a) (a), -1, -1, -1 965 966 /** 967 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchblstat0 968 * 969 * DSS Ddrctl Regb Arb Port0 Pchblstat0 Register 970 * CHB Port Link status register 0 971 */ 972 union ody_dssx_ddrctl_regb_arb_port0_pchblstat0 { 973 uint32_t u; 974 struct ody_dssx_ddrctl_regb_arb_port0_pchblstat0_s { 975 uint32_t txsactive_status : 1; 976 uint32_t rxsactive_status : 1; 977 uint32_t tx_req : 1; 978 uint32_t tx_ack : 1; 979 uint32_t rx_req : 1; 980 uint32_t rx_ack : 1; 981 uint32_t reserved_6_31 : 26; 982 } s; 983 /* struct ody_dssx_ddrctl_regb_arb_port0_pchblstat0_s cn; */ 984 }; 985 typedef union ody_dssx_ddrctl_regb_arb_port0_pchblstat0 ody_dssx_ddrctl_regb_arb_port0_pchblstat0_t; 986 987 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0(uint64_t a) __attribute__ ((pure, always_inline)); 988 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0(uint64_t a) 989 { 990 if (a <= 19) 991 return 0x87e1b0220980ll + 0x1000000ll * ((a) & 0x1f); 992 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0", 1, a, 0, 0, 0, 0, 0); 993 } 994 995 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0(a) ody_dssx_ddrctl_regb_arb_port0_pchblstat0_t 996 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0(a) CSR_TYPE_RSL32b 997 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0" 998 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0(a) 0x0 /* PF_BAR0 */ 999 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0(a) (a) 1000 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBLSTAT0(a) (a), -1, -1, -1 1001 1002 /** 1003 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbprctmr 1004 * 1005 * DSS Ddrctl Regb Arb Port0 Pchbprctmr Register 1006 * CHB Port Prefetch cache eviction Timer register 1007 */ 1008 union ody_dssx_ddrctl_regb_arb_port0_pchbprctmr { 1009 uint32_t u; 1010 struct ody_dssx_ddrctl_regb_arb_port0_pchbprctmr_s { 1011 uint32_t prc_exp_cnt : 10; 1012 uint32_t reserved_10_15 : 6; 1013 uint32_t exp_cnt_div : 2; 1014 uint32_t reserved_18_31 : 14; 1015 } s; 1016 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbprctmr_s cn; */ 1017 }; 1018 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbprctmr ody_dssx_ddrctl_regb_arb_port0_pchbprctmr_t; 1019 1020 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR(uint64_t a) __attribute__ ((pure, always_inline)); 1021 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR(uint64_t a) 1022 { 1023 if (a <= 19) 1024 return 0x87e1b0220908ll + 0x1000000ll * ((a) & 0x1f); 1025 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR", 1, a, 0, 0, 0, 0, 0); 1026 } 1027 1028 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR(a) ody_dssx_ddrctl_regb_arb_port0_pchbprctmr_t 1029 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR(a) CSR_TYPE_RSL32b 1030 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR" 1031 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR(a) 0x0 /* PF_BAR0 */ 1032 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR(a) (a) 1033 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPRCTMR(a) (a), -1, -1, -1 1034 1035 /** 1036 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbprotqctl 1037 * 1038 * DSS Ddrctl Regb Arb Port0 Pchbprotqctl Register 1039 * CHB Port Protocol Queue control register 1040 */ 1041 union ody_dssx_ddrctl_regb_arb_port0_pchbprotqctl { 1042 uint32_t u; 1043 struct ody_dssx_ddrctl_regb_arb_port0_pchbprotqctl_s { 1044 uint32_t rpq_lpr_min : 7; 1045 uint32_t reserved_7 : 1; 1046 uint32_t rpq_hpr_min : 7; 1047 uint32_t reserved_15_31 : 17; 1048 } s; 1049 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbprotqctl_s cn; */ 1050 }; 1051 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbprotqctl ody_dssx_ddrctl_regb_arb_port0_pchbprotqctl_t; 1052 1053 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL(uint64_t a) __attribute__ ((pure, always_inline)); 1054 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL(uint64_t a) 1055 { 1056 if (a <= 19) 1057 return 0x87e1b022090cll + 0x1000000ll * ((a) & 0x1f); 1058 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL", 1, a, 0, 0, 0, 0, 0); 1059 } 1060 1061 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL(a) ody_dssx_ddrctl_regb_arb_port0_pchbprotqctl_t 1062 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL(a) CSR_TYPE_RSL32b 1063 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL" 1064 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL(a) 0x0 /* PF_BAR0 */ 1065 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL(a) (a) 1066 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBPROTQCTL(a) (a), -1, -1, -1 1067 1068 /** 1069 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbrlstat 1070 * 1071 * DSS Ddrctl Regb Arb Port0 Pchbrlstat Register 1072 * CHB Port Retry List status register 1073 */ 1074 union ody_dssx_ddrctl_regb_arb_port0_pchbrlstat { 1075 uint32_t u; 1076 struct ody_dssx_ddrctl_regb_arb_port0_pchbrlstat_s { 1077 uint32_t retry_list_empty : 1; 1078 uint32_t retry_list_full : 1; 1079 uint32_t pend_qos_type : 5; 1080 uint32_t reserved_7_31 : 25; 1081 } s; 1082 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbrlstat_s cn; */ 1083 }; 1084 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbrlstat ody_dssx_ddrctl_regb_arb_port0_pchbrlstat_t; 1085 1086 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 1087 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT(uint64_t a) 1088 { 1089 if (a <= 19) 1090 return 0x87e1b0220990ll + 0x1000000ll * ((a) & 0x1f); 1091 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT", 1, a, 0, 0, 0, 0, 0); 1092 } 1093 1094 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT(a) ody_dssx_ddrctl_regb_arb_port0_pchbrlstat_t 1095 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT(a) CSR_TYPE_RSL32b 1096 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT" 1097 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT(a) 0x0 /* PF_BAR0 */ 1098 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT(a) (a) 1099 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRLSTAT(a) (a), -1, -1, -1 1100 1101 /** 1102 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbrqos0 1103 * 1104 * DSS Ddrctl Regb Arb Port0 Pchbrqos0 Register 1105 * CHB Port n Read QoS Configuration Register 0 1106 */ 1107 union ody_dssx_ddrctl_regb_arb_port0_pchbrqos0 { 1108 uint32_t u; 1109 struct ody_dssx_ddrctl_regb_arb_port0_pchbrqos0_s { 1110 uint32_t chb_rqos_map_level1 : 4; 1111 uint32_t reserved_4_7 : 4; 1112 uint32_t chb_rqos_map_level2 : 4; 1113 uint32_t reserved_12_15 : 4; 1114 uint32_t chb_rqos_map_region0 : 2; 1115 uint32_t reserved_18_19 : 2; 1116 uint32_t chb_rqos_map_region1 : 2; 1117 uint32_t reserved_22_23 : 2; 1118 uint32_t chb_rqos_map_region2 : 2; 1119 uint32_t reserved_26_31 : 6; 1120 } s; 1121 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbrqos0_s cn; */ 1122 }; 1123 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbrqos0 ody_dssx_ddrctl_regb_arb_port0_pchbrqos0_t; 1124 1125 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0(uint64_t a) __attribute__ ((pure, always_inline)); 1126 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0(uint64_t a) 1127 { 1128 if (a <= 19) 1129 return 0x87e1b0220910ll + 0x1000000ll * ((a) & 0x1f); 1130 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0", 1, a, 0, 0, 0, 0, 0); 1131 } 1132 1133 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0(a) ody_dssx_ddrctl_regb_arb_port0_pchbrqos0_t 1134 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0(a) CSR_TYPE_RSL32b 1135 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0" 1136 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0(a) 0x0 /* PF_BAR0 */ 1137 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0(a) (a) 1138 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS0(a) (a), -1, -1, -1 1139 1140 /** 1141 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbrqos1 1142 * 1143 * DSS Ddrctl Regb Arb Port0 Pchbrqos1 Register 1144 * CHB Port n Read QoS Configuration Register 1 1145 */ 1146 union ody_dssx_ddrctl_regb_arb_port0_pchbrqos1 { 1147 uint32_t u; 1148 struct ody_dssx_ddrctl_regb_arb_port0_pchbrqos1_s { 1149 uint32_t vpr_uncrd_timeout : 11; 1150 uint32_t reserved_11_15 : 5; 1151 uint32_t vpr_crd_timeout : 11; 1152 uint32_t reserved_27_31 : 5; 1153 } s; 1154 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbrqos1_s cn; */ 1155 }; 1156 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbrqos1 ody_dssx_ddrctl_regb_arb_port0_pchbrqos1_t; 1157 1158 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1(uint64_t a) __attribute__ ((pure, always_inline)); 1159 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1(uint64_t a) 1160 { 1161 if (a <= 19) 1162 return 0x87e1b0220914ll + 0x1000000ll * ((a) & 0x1f); 1163 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1", 1, a, 0, 0, 0, 0, 0); 1164 } 1165 1166 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1(a) ody_dssx_ddrctl_regb_arb_port0_pchbrqos1_t 1167 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1(a) CSR_TYPE_RSL32b 1168 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1" 1169 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1(a) 0x0 /* PF_BAR0 */ 1170 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1(a) (a) 1171 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBRQOS1(a) (a), -1, -1, -1 1172 1173 /** 1174 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbtctrl 1175 * 1176 * DSS Ddrctl Regb Arb Port0 Pchbtctrl Register 1177 * CHB Port Transaction Control register 1178 */ 1179 union ody_dssx_ddrctl_regb_arb_port0_pchbtctrl { 1180 uint32_t u; 1181 struct ody_dssx_ddrctl_regb_arb_port0_pchbtctrl_s { 1182 uint32_t dis_prefetch : 1; 1183 uint32_t crc_ue_rsp_sel : 2; 1184 uint32_t reserved_3 : 1; 1185 uint32_t dbg_force_pcrd_steal_mode : 1; 1186 uint32_t reserved_5_31 : 27; 1187 } s; 1188 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbtctrl_s cn; */ 1189 }; 1190 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbtctrl ody_dssx_ddrctl_regb_arb_port0_pchbtctrl_t; 1191 1192 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL(uint64_t a) __attribute__ ((pure, always_inline)); 1193 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL(uint64_t a) 1194 { 1195 if (a <= 19) 1196 return 0x87e1b0220904ll + 0x1000000ll * ((a) & 0x1f); 1197 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL", 1, a, 0, 0, 0, 0, 0); 1198 } 1199 1200 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL(a) ody_dssx_ddrctl_regb_arb_port0_pchbtctrl_t 1201 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL(a) CSR_TYPE_RSL32b 1202 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL" 1203 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL(a) 0x0 /* PF_BAR0 */ 1204 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL(a) (a) 1205 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBTCTRL(a) (a), -1, -1, -1 1206 1207 /** 1208 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbwqos0 1209 * 1210 * DSS Ddrctl Regb Arb Port0 Pchbwqos0 Register 1211 * CHB Port n Write QoS Configuration Register 0 1212 */ 1213 union ody_dssx_ddrctl_regb_arb_port0_pchbwqos0 { 1214 uint32_t u; 1215 struct ody_dssx_ddrctl_regb_arb_port0_pchbwqos0_s { 1216 uint32_t chb_wqos_map_level1 : 4; 1217 uint32_t reserved_4_7 : 4; 1218 uint32_t chb_wqos_map_level2 : 4; 1219 uint32_t reserved_12_15 : 4; 1220 uint32_t chb_wqos_map_region0 : 2; 1221 uint32_t reserved_18_19 : 2; 1222 uint32_t chb_wqos_map_region1 : 2; 1223 uint32_t reserved_22_23 : 2; 1224 uint32_t chb_wqos_map_region2 : 2; 1225 uint32_t reserved_26_31 : 6; 1226 } s; 1227 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbwqos0_s cn; */ 1228 }; 1229 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbwqos0 ody_dssx_ddrctl_regb_arb_port0_pchbwqos0_t; 1230 1231 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0(uint64_t a) __attribute__ ((pure, always_inline)); 1232 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0(uint64_t a) 1233 { 1234 if (a <= 19) 1235 return 0x87e1b0220918ll + 0x1000000ll * ((a) & 0x1f); 1236 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0", 1, a, 0, 0, 0, 0, 0); 1237 } 1238 1239 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0(a) ody_dssx_ddrctl_regb_arb_port0_pchbwqos0_t 1240 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0(a) CSR_TYPE_RSL32b 1241 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0" 1242 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0(a) 0x0 /* PF_BAR0 */ 1243 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0(a) (a) 1244 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS0(a) (a), -1, -1, -1 1245 1246 /** 1247 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pchbwqos1 1248 * 1249 * DSS Ddrctl Regb Arb Port0 Pchbwqos1 Register 1250 * CHB Port n Write QoS Configuration Register 1 1251 */ 1252 union ody_dssx_ddrctl_regb_arb_port0_pchbwqos1 { 1253 uint32_t u; 1254 struct ody_dssx_ddrctl_regb_arb_port0_pchbwqos1_s { 1255 uint32_t vpw_uncrd_timeout : 11; 1256 uint32_t reserved_11_15 : 5; 1257 uint32_t vpw_crd_timeout : 11; 1258 uint32_t reserved_27_31 : 5; 1259 } s; 1260 /* struct ody_dssx_ddrctl_regb_arb_port0_pchbwqos1_s cn; */ 1261 }; 1262 typedef union ody_dssx_ddrctl_regb_arb_port0_pchbwqos1 ody_dssx_ddrctl_regb_arb_port0_pchbwqos1_t; 1263 1264 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1(uint64_t a) __attribute__ ((pure, always_inline)); 1265 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1(uint64_t a) 1266 { 1267 if (a <= 19) 1268 return 0x87e1b022091cll + 0x1000000ll * ((a) & 0x1f); 1269 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1", 1, a, 0, 0, 0, 0, 0); 1270 } 1271 1272 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1(a) ody_dssx_ddrctl_regb_arb_port0_pchbwqos1_t 1273 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1(a) CSR_TYPE_RSL32b 1274 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1" 1275 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1(a) 0x0 /* PF_BAR0 */ 1276 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1(a) (a) 1277 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCHBWQOS1(a) (a), -1, -1, -1 1278 1279 /** 1280 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pctrl 1281 * 1282 * DSS Ddrctl Regb Arb Port0 Pctrl Register 1283 * Port Control Register 1284 */ 1285 union ody_dssx_ddrctl_regb_arb_port0_pctrl { 1286 uint32_t u; 1287 struct ody_dssx_ddrctl_regb_arb_port0_pctrl_s { 1288 uint32_t port_en : 1; 1289 uint32_t reserved_1_31 : 31; 1290 } s; 1291 /* struct ody_dssx_ddrctl_regb_arb_port0_pctrl_s cn; */ 1292 }; 1293 typedef union ody_dssx_ddrctl_regb_arb_port0_pctrl ody_dssx_ddrctl_regb_arb_port0_pctrl_t; 1294 1295 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL(uint64_t a) __attribute__ ((pure, always_inline)); 1296 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL(uint64_t a) 1297 { 1298 if (a <= 19) 1299 return 0x87e1b0220090ll + 0x1000000ll * ((a) & 0x1f); 1300 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL", 1, a, 0, 0, 0, 0, 0); 1301 } 1302 1303 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL(a) ody_dssx_ddrctl_regb_arb_port0_pctrl_t 1304 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL(a) CSR_TYPE_RSL32b 1305 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL" 1306 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL(a) 0x0 /* PF_BAR0 */ 1307 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL(a) (a) 1308 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PCTRL(a) (a), -1, -1, -1 1309 1310 /** 1311 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_pstat 1312 * 1313 * DSS Ddrctl Regb Arb Port0 Pstat Register 1314 * Port Status Register 1315 */ 1316 union ody_dssx_ddrctl_regb_arb_port0_pstat { 1317 uint32_t u; 1318 struct ody_dssx_ddrctl_regb_arb_port0_pstat_s { 1319 uint32_t rd_port_busy_0 : 1; 1320 uint32_t reserved_1_15 : 15; 1321 uint32_t wr_port_busy_0 : 1; 1322 uint32_t reserved_17_31 : 15; 1323 } s; 1324 /* struct ody_dssx_ddrctl_regb_arb_port0_pstat_s cn; */ 1325 }; 1326 typedef union ody_dssx_ddrctl_regb_arb_port0_pstat ody_dssx_ddrctl_regb_arb_port0_pstat_t; 1327 1328 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 1329 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT(uint64_t a) 1330 { 1331 if (a <= 19) 1332 return 0x87e1b0220114ll + 0x1000000ll * ((a) & 0x1f); 1333 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT", 1, a, 0, 0, 0, 0, 0); 1334 } 1335 1336 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT(a) ody_dssx_ddrctl_regb_arb_port0_pstat_t 1337 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT(a) CSR_TYPE_RSL32b 1338 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT(a) "DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT" 1339 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT(a) 0x0 /* PF_BAR0 */ 1340 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT(a) (a) 1341 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_PSTAT(a) (a), -1, -1, -1 1342 1343 /** 1344 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbraddrlog0 1345 * 1346 * DSS Ddrctl Regb Arb Port0 Sbraddrlog0 Register 1347 * Lower 32 bits of last generated scrubber address 1348 */ 1349 union ody_dssx_ddrctl_regb_arb_port0_sbraddrlog0 { 1350 uint32_t u; 1351 struct ody_dssx_ddrctl_regb_arb_port0_sbraddrlog0_s { 1352 uint32_t scrub_addr_log0 : 32; 1353 } s; 1354 /* struct ody_dssx_ddrctl_regb_arb_port0_sbraddrlog0_s cn; */ 1355 }; 1356 typedef union ody_dssx_ddrctl_regb_arb_port0_sbraddrlog0 ody_dssx_ddrctl_regb_arb_port0_sbraddrlog0_t; 1357 1358 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0(uint64_t a) __attribute__ ((pure, always_inline)); 1359 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0(uint64_t a) 1360 { 1361 if (a <= 19) 1362 return 0x87e1b022011cll + 0x1000000ll * ((a) & 0x1f); 1363 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0", 1, a, 0, 0, 0, 0, 0); 1364 } 1365 1366 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0(a) ody_dssx_ddrctl_regb_arb_port0_sbraddrlog0_t 1367 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0(a) CSR_TYPE_RSL32b 1368 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0" 1369 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0(a) 0x0 /* PF_BAR0 */ 1370 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0(a) (a) 1371 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG0(a) (a), -1, -1, -1 1372 1373 /** 1374 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbraddrlog1 1375 * 1376 * DSS Ddrctl Regb Arb Port0 Sbraddrlog1 Register 1377 * Higher MEMC_HIF_ADDR_WIDTH-32 bits of last generated scrubber address 1378 */ 1379 union ody_dssx_ddrctl_regb_arb_port0_sbraddrlog1 { 1380 uint32_t u; 1381 struct ody_dssx_ddrctl_regb_arb_port0_sbraddrlog1_s { 1382 uint32_t scrub_addr_log1 : 3; 1383 uint32_t reserved_3_31 : 29; 1384 } s; 1385 /* struct ody_dssx_ddrctl_regb_arb_port0_sbraddrlog1_s cn; */ 1386 }; 1387 typedef union ody_dssx_ddrctl_regb_arb_port0_sbraddrlog1 ody_dssx_ddrctl_regb_arb_port0_sbraddrlog1_t; 1388 1389 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1(uint64_t a) __attribute__ ((pure, always_inline)); 1390 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1(uint64_t a) 1391 { 1392 if (a <= 19) 1393 return 0x87e1b0220120ll + 0x1000000ll * ((a) & 0x1f); 1394 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1", 1, a, 0, 0, 0, 0, 0); 1395 } 1396 1397 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1(a) ody_dssx_ddrctl_regb_arb_port0_sbraddrlog1_t 1398 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1(a) CSR_TYPE_RSL32b 1399 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1" 1400 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1(a) 0x0 /* PF_BAR0 */ 1401 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1(a) (a) 1402 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRLOG1(a) (a), -1, -1, -1 1403 1404 /** 1405 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbraddrrestore0 1406 * 1407 * DSS Ddrctl Regb Arb Port0 Sbraddrrestore0 Register 1408 * Lower 32 bits of address to be loaded to the scrubber 1409 */ 1410 union ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore0 { 1411 uint32_t u; 1412 struct ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore0_s { 1413 uint32_t scrub_restore_address0 : 32; 1414 } s; 1415 /* struct ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore0_s cn; */ 1416 }; 1417 typedef union ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore0 ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore0_t; 1418 1419 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0(uint64_t a) __attribute__ ((pure, always_inline)); 1420 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0(uint64_t a) 1421 { 1422 if (a <= 19) 1423 return 0x87e1b0220124ll + 0x1000000ll * ((a) & 0x1f); 1424 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0", 1, a, 0, 0, 0, 0, 0); 1425 } 1426 1427 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0(a) ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore0_t 1428 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0(a) CSR_TYPE_RSL32b 1429 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0" 1430 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0(a) 0x0 /* PF_BAR0 */ 1431 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0(a) (a) 1432 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE0(a) (a), -1, -1, -1 1433 1434 /** 1435 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbraddrrestore1 1436 * 1437 * DSS Ddrctl Regb Arb Port0 Sbraddrrestore1 Register 1438 * Higher MEMC_HIF_ADDR_WIDTH-32 bits of address to be loaded to the scrubber 1439 */ 1440 union ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore1 { 1441 uint32_t u; 1442 struct ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore1_s { 1443 uint32_t scrub_restore_address1 : 3; 1444 uint32_t reserved_3_31 : 29; 1445 } s; 1446 /* struct ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore1_s cn; */ 1447 }; 1448 typedef union ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore1 ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore1_t; 1449 1450 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1(uint64_t a) __attribute__ ((pure, always_inline)); 1451 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1(uint64_t a) 1452 { 1453 if (a <= 19) 1454 return 0x87e1b0220128ll + 0x1000000ll * ((a) & 0x1f); 1455 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1", 1, a, 0, 0, 0, 0, 0); 1456 } 1457 1458 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1(a) ody_dssx_ddrctl_regb_arb_port0_sbraddrrestore1_t 1459 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1(a) CSR_TYPE_RSL32b 1460 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1" 1461 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1(a) 0x0 /* PF_BAR0 */ 1462 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1(a) (a) 1463 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRADDRRESTORE1(a) (a), -1, -1, -1 1464 1465 /** 1466 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbrctl 1467 * 1468 * DSS Ddrctl Regb Arb Port0 Sbrctl Register 1469 * Scrubber Control Register 1470 */ 1471 union ody_dssx_ddrctl_regb_arb_port0_sbrctl { 1472 uint32_t u; 1473 struct ody_dssx_ddrctl_regb_arb_port0_sbrctl_s { 1474 uint32_t scrub_en : 1; 1475 uint32_t scrub_during_lowpower : 1; 1476 uint32_t reserved_2_3 : 2; 1477 uint32_t scrub_burst_length_nm : 3; 1478 uint32_t reserved_7 : 1; 1479 uint32_t scrub_interval : 13; 1480 uint32_t reserved_21_23 : 3; 1481 uint32_t scrub_cmd_type : 2; 1482 uint32_t sbr_correction_mode : 2; 1483 uint32_t scrub_burst_length_lp : 3; 1484 uint32_t scrub_ue : 1; 1485 } s; 1486 /* struct ody_dssx_ddrctl_regb_arb_port0_sbrctl_s cn; */ 1487 }; 1488 typedef union ody_dssx_ddrctl_regb_arb_port0_sbrctl ody_dssx_ddrctl_regb_arb_port0_sbrctl_t; 1489 1490 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL(uint64_t a) __attribute__ ((pure, always_inline)); 1491 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL(uint64_t a) 1492 { 1493 if (a <= 19) 1494 return 0x87e1b02200e0ll + 0x1000000ll * ((a) & 0x1f); 1495 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL", 1, a, 0, 0, 0, 0, 0); 1496 } 1497 1498 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL(a) ody_dssx_ddrctl_regb_arb_port0_sbrctl_t 1499 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL(a) CSR_TYPE_RSL32b 1500 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL" 1501 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL(a) 0x0 /* PF_BAR0 */ 1502 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL(a) (a) 1503 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRCTL(a) (a), -1, -1, -1 1504 1505 /** 1506 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbrlpctl 1507 * 1508 * DSS Ddrctl Regb Arb Port0 Sbrlpctl Register 1509 * Scrubber DDR5 low power modes control register 1510 */ 1511 union ody_dssx_ddrctl_regb_arb_port0_sbrlpctl { 1512 uint32_t u; 1513 struct ody_dssx_ddrctl_regb_arb_port0_sbrlpctl_s { 1514 uint32_t perrank_dis_scrub : 2; 1515 uint32_t reserved_2_3 : 2; 1516 uint32_t scrub_restore : 1; 1517 uint32_t reserved_5_31 : 27; 1518 } s; 1519 /* struct ody_dssx_ddrctl_regb_arb_port0_sbrlpctl_s cn; */ 1520 }; 1521 typedef union ody_dssx_ddrctl_regb_arb_port0_sbrlpctl ody_dssx_ddrctl_regb_arb_port0_sbrlpctl_t; 1522 1523 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL(uint64_t a) __attribute__ ((pure, always_inline)); 1524 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL(uint64_t a) 1525 { 1526 if (a <= 19) 1527 return 0x87e1b0220118ll + 0x1000000ll * ((a) & 0x1f); 1528 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL", 1, a, 0, 0, 0, 0, 0); 1529 } 1530 1531 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL(a) ody_dssx_ddrctl_regb_arb_port0_sbrlpctl_t 1532 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL(a) CSR_TYPE_RSL32b 1533 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL" 1534 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL(a) 0x0 /* PF_BAR0 */ 1535 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL(a) (a) 1536 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRLPCTL(a) (a), -1, -1, -1 1537 1538 /** 1539 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbrrange0 1540 * 1541 * DSS Ddrctl Regb Arb Port0 Sbrrange0 Register 1542 * Scrubber Address Range Mask Register 0 1543 */ 1544 union ody_dssx_ddrctl_regb_arb_port0_sbrrange0 { 1545 uint32_t u; 1546 struct ody_dssx_ddrctl_regb_arb_port0_sbrrange0_s { 1547 uint32_t sbr_address_range_mask_0 : 32; 1548 } s; 1549 /* struct ody_dssx_ddrctl_regb_arb_port0_sbrrange0_s cn; */ 1550 }; 1551 typedef union ody_dssx_ddrctl_regb_arb_port0_sbrrange0 ody_dssx_ddrctl_regb_arb_port0_sbrrange0_t; 1552 1553 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0(uint64_t a) __attribute__ ((pure, always_inline)); 1554 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0(uint64_t a) 1555 { 1556 if (a <= 19) 1557 return 0x87e1b02200f8ll + 0x1000000ll * ((a) & 0x1f); 1558 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0", 1, a, 0, 0, 0, 0, 0); 1559 } 1560 1561 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0(a) ody_dssx_ddrctl_regb_arb_port0_sbrrange0_t 1562 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0(a) CSR_TYPE_RSL32b 1563 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0" 1564 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0(a) 0x0 /* PF_BAR0 */ 1565 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0(a) (a) 1566 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE0(a) (a), -1, -1, -1 1567 1568 /** 1569 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbrrange1 1570 * 1571 * DSS Ddrctl Regb Arb Port0 Sbrrange1 Register 1572 * Scrubber Address Range Mask Register 1 1573 */ 1574 union ody_dssx_ddrctl_regb_arb_port0_sbrrange1 { 1575 uint32_t u; 1576 struct ody_dssx_ddrctl_regb_arb_port0_sbrrange1_s { 1577 uint32_t sbr_address_range_mask_1 : 8; 1578 uint32_t reserved_8_31 : 24; 1579 } s; 1580 /* struct ody_dssx_ddrctl_regb_arb_port0_sbrrange1_s cn; */ 1581 }; 1582 typedef union ody_dssx_ddrctl_regb_arb_port0_sbrrange1 ody_dssx_ddrctl_regb_arb_port0_sbrrange1_t; 1583 1584 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1(uint64_t a) __attribute__ ((pure, always_inline)); 1585 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1(uint64_t a) 1586 { 1587 if (a <= 19) 1588 return 0x87e1b02200fcll + 0x1000000ll * ((a) & 0x1f); 1589 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1", 1, a, 0, 0, 0, 0, 0); 1590 } 1591 1592 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1(a) ody_dssx_ddrctl_regb_arb_port0_sbrrange1_t 1593 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1(a) CSR_TYPE_RSL32b 1594 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1" 1595 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1(a) 0x0 /* PF_BAR0 */ 1596 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1(a) (a) 1597 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRRANGE1(a) (a), -1, -1, -1 1598 1599 /** 1600 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbrstart0 1601 * 1602 * DSS Ddrctl Regb Arb Port0 Sbrstart0 Register 1603 * Scrubber Start Address Mask Register 0 1604 */ 1605 union ody_dssx_ddrctl_regb_arb_port0_sbrstart0 { 1606 uint32_t u; 1607 struct ody_dssx_ddrctl_regb_arb_port0_sbrstart0_s { 1608 uint32_t sbr_address_start_mask_0 : 32; 1609 } s; 1610 /* struct ody_dssx_ddrctl_regb_arb_port0_sbrstart0_s cn; */ 1611 }; 1612 typedef union ody_dssx_ddrctl_regb_arb_port0_sbrstart0 ody_dssx_ddrctl_regb_arb_port0_sbrstart0_t; 1613 1614 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0(uint64_t a) __attribute__ ((pure, always_inline)); 1615 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0(uint64_t a) 1616 { 1617 if (a <= 19) 1618 return 0x87e1b02200f0ll + 0x1000000ll * ((a) & 0x1f); 1619 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0", 1, a, 0, 0, 0, 0, 0); 1620 } 1621 1622 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0(a) ody_dssx_ddrctl_regb_arb_port0_sbrstart0_t 1623 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0(a) CSR_TYPE_RSL32b 1624 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0" 1625 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0(a) 0x0 /* PF_BAR0 */ 1626 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0(a) (a) 1627 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART0(a) (a), -1, -1, -1 1628 1629 /** 1630 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbrstart1 1631 * 1632 * DSS Ddrctl Regb Arb Port0 Sbrstart1 Register 1633 * Scrubber Start Address Mask Register 1 1634 */ 1635 union ody_dssx_ddrctl_regb_arb_port0_sbrstart1 { 1636 uint32_t u; 1637 struct ody_dssx_ddrctl_regb_arb_port0_sbrstart1_s { 1638 uint32_t sbr_address_start_mask_1 : 8; 1639 uint32_t reserved_8_31 : 24; 1640 } s; 1641 /* struct ody_dssx_ddrctl_regb_arb_port0_sbrstart1_s cn; */ 1642 }; 1643 typedef union ody_dssx_ddrctl_regb_arb_port0_sbrstart1 ody_dssx_ddrctl_regb_arb_port0_sbrstart1_t; 1644 1645 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1(uint64_t a) __attribute__ ((pure, always_inline)); 1646 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1(uint64_t a) 1647 { 1648 if (a <= 19) 1649 return 0x87e1b02200f4ll + 0x1000000ll * ((a) & 0x1f); 1650 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1", 1, a, 0, 0, 0, 0, 0); 1651 } 1652 1653 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1(a) ody_dssx_ddrctl_regb_arb_port0_sbrstart1_t 1654 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1(a) CSR_TYPE_RSL32b 1655 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1" 1656 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1(a) 0x0 /* PF_BAR0 */ 1657 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1(a) (a) 1658 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTART1(a) (a), -1, -1, -1 1659 1660 /** 1661 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbrstat 1662 * 1663 * DSS Ddrctl Regb Arb Port0 Sbrstat Register 1664 * Scrubber Status Register 1665 */ 1666 union ody_dssx_ddrctl_regb_arb_port0_sbrstat { 1667 uint32_t u; 1668 struct ody_dssx_ddrctl_regb_arb_port0_sbrstat_s { 1669 uint32_t scrub_busy : 1; 1670 uint32_t scrub_done : 1; 1671 uint32_t reserved_2_3 : 2; 1672 uint32_t scrub_drop_cnt : 5; 1673 uint32_t reserved_9_31 : 23; 1674 } s; 1675 /* struct ody_dssx_ddrctl_regb_arb_port0_sbrstat_s cn; */ 1676 }; 1677 typedef union ody_dssx_ddrctl_regb_arb_port0_sbrstat ody_dssx_ddrctl_regb_arb_port0_sbrstat_t; 1678 1679 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 1680 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT(uint64_t a) 1681 { 1682 if (a <= 19) 1683 return 0x87e1b02200e4ll + 0x1000000ll * ((a) & 0x1f); 1684 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT", 1, a, 0, 0, 0, 0, 0); 1685 } 1686 1687 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT(a) ody_dssx_ddrctl_regb_arb_port0_sbrstat_t 1688 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT(a) CSR_TYPE_RSL32b 1689 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT" 1690 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT(a) 0x0 /* PF_BAR0 */ 1691 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT(a) (a) 1692 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRSTAT(a) (a), -1, -1, -1 1693 1694 /** 1695 * Register (RSL32b) dss#_ddrctl_regb_arb_port0_sbrwdata0 1696 * 1697 * DSS Ddrctl Regb Arb Port0 Sbrwdata0 Register 1698 * Scrubber Write Data Pattern0 1699 */ 1700 union ody_dssx_ddrctl_regb_arb_port0_sbrwdata0 { 1701 uint32_t u; 1702 struct ody_dssx_ddrctl_regb_arb_port0_sbrwdata0_s { 1703 uint32_t scrub_pattern0 : 32; 1704 } s; 1705 /* struct ody_dssx_ddrctl_regb_arb_port0_sbrwdata0_s cn; */ 1706 }; 1707 typedef union ody_dssx_ddrctl_regb_arb_port0_sbrwdata0 ody_dssx_ddrctl_regb_arb_port0_sbrwdata0_t; 1708 1709 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0(uint64_t a) __attribute__ ((pure, always_inline)); 1710 static inline uint64_t ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0(uint64_t a) 1711 { 1712 if (a <= 19) 1713 return 0x87e1b02200e8ll + 0x1000000ll * ((a) & 0x1f); 1714 __ody_csr_fatal("DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0", 1, a, 0, 0, 0, 0, 0); 1715 } 1716 1717 #define typedef_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0(a) ody_dssx_ddrctl_regb_arb_port0_sbrwdata0_t 1718 #define bustype_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0(a) CSR_TYPE_RSL32b 1719 #define basename_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0(a) "DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0" 1720 #define device_bar_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0(a) 0x0 /* PF_BAR0 */ 1721 #define busnum_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0(a) (a) 1722 #define arguments_ODY_DSSX_DDRCTL_REGB_ARB_PORT0_SBRWDATA0(a) (a), -1, -1, -1 1723 1724 /** 1725 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_max 1726 * 1727 * DSS Ddrctl Regb Chb Mpam Ns Mpamcfg Mbw Max Register 1728 * MPAM memory maximum bandwidth partitioning partition configuration register. 1729 */ 1730 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_max { 1731 uint32_t u; 1732 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_max_s { 1733 uint32_t unimpl : 8; 1734 uint32_t max : 8; 1735 uint32_t reserved_16_31 : 16; 1736 } s; 1737 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_max_s cn; */ 1738 }; 1739 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_max ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_max_t; 1740 1741 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX(uint64_t a) __attribute__ ((pure, always_inline)); 1742 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX(uint64_t a) 1743 { 1744 if (a <= 19) 1745 return 0x87e1b0240208ll + 0x1000000ll * ((a) & 0x1f); 1746 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX", 1, a, 0, 0, 0, 0, 0); 1747 } 1748 1749 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_max_t 1750 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX(a) CSR_TYPE_RSL32b 1751 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX" 1752 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX(a) 0x0 /* PF_BAR0 */ 1753 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX(a) (a) 1754 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MAX(a) (a), -1, -1, -1 1755 1756 /** 1757 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_min 1758 * 1759 * DSS Ddrctl Regb Chb Mpam Ns Mpamcfg Mbw Min Register 1760 * MPAM memory minimum bandwidth partitioning partition configuration register. 1761 */ 1762 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_min { 1763 uint32_t u; 1764 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_min_s { 1765 uint32_t unimpl : 8; 1766 uint32_t min : 8; 1767 uint32_t reserved_16_31 : 16; 1768 } s; 1769 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_min_s cn; */ 1770 }; 1771 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_min ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_min_t; 1772 1773 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN(uint64_t a) __attribute__ ((pure, always_inline)); 1774 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN(uint64_t a) 1775 { 1776 if (a <= 19) 1777 return 0x87e1b0240200ll + 0x1000000ll * ((a) & 0x1f); 1778 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN", 1, a, 0, 0, 0, 0, 0); 1779 } 1780 1781 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_min_t 1782 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN(a) CSR_TYPE_RSL32b 1783 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN" 1784 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN(a) 0x0 /* PF_BAR0 */ 1785 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN(a) (a) 1786 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_MIN(a) (a), -1, -1, -1 1787 1788 /** 1789 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_winwd 1790 * 1791 * DSS Ddrctl Regb Chb Mpam Ns Mpamcfg Mbw Winwd Register 1792 * MPAM memory bandwidth partitioning window width register. 1793 * 1794 * Note: This IP uses a custom implementation to set BW accounting widow. 1795 * MPAMCFG_MBW_WINWD hence is not compliant to the MPAM spec. SW should not use 1796 * MPAMCFG_MBW_WINWD and instead rely on MPAMF_CUST_WINDW register 1797 */ 1798 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_winwd { 1799 uint32_t u; 1800 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_winwd_s { 1801 uint32_t us_frac : 8; 1802 uint32_t us_int : 16; 1803 uint32_t reserved_24_31 : 8; 1804 } s; 1805 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_winwd_s cn; */ 1806 }; 1807 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_winwd ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_winwd_t; 1808 1809 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD(uint64_t a) __attribute__ ((pure, always_inline)); 1810 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD(uint64_t a) 1811 { 1812 if (a <= 19) 1813 return 0x87e1b0240220ll + 0x1000000ll * ((a) & 0x1f); 1814 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD", 1, a, 0, 0, 0, 0, 0); 1815 } 1816 1817 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_mbw_winwd_t 1818 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD(a) CSR_TYPE_RSL32b 1819 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD" 1820 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD(a) 0x0 /* PF_BAR0 */ 1821 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD(a) (a) 1822 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_MBW_WINWD(a) (a), -1, -1, -1 1823 1824 /** 1825 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamcfg_part_sel 1826 * 1827 * DSS Ddrctl Regb Chb Mpam Ns Mpamcfg Part Sel Register 1828 * MPAM partition configuration selection register 1829 */ 1830 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_part_sel { 1831 uint32_t u; 1832 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_part_sel_s { 1833 uint32_t partid_sel : 16; 1834 uint32_t internal : 1; 1835 uint32_t reserved_17_31 : 15; 1836 } s; 1837 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_part_sel_s cn; */ 1838 }; 1839 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_part_sel ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_part_sel_t; 1840 1841 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL(uint64_t a) __attribute__ ((pure, always_inline)); 1842 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL(uint64_t a) 1843 { 1844 if (a <= 19) 1845 return 0x87e1b0240100ll + 0x1000000ll * ((a) & 0x1f); 1846 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL", 1, a, 0, 0, 0, 0, 0); 1847 } 1848 1849 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamcfg_part_sel_t 1850 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL(a) CSR_TYPE_RSL32b 1851 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL" 1852 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL(a) 0x0 /* PF_BAR0 */ 1853 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL(a) (a) 1854 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMCFG_PART_SEL(a) (a), -1, -1, -1 1855 1856 /** 1857 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_aidr 1858 * 1859 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Aidr Register 1860 * MPAM architecture ID register. 1861 */ 1862 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_aidr { 1863 uint32_t u; 1864 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_aidr_s { 1865 uint32_t archminorrev : 4; 1866 uint32_t archmajorrev : 4; 1867 uint32_t reserved_8_31 : 24; 1868 } s; 1869 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_aidr_s cn; */ 1870 }; 1871 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_aidr ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_aidr_t; 1872 1873 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR(uint64_t a) __attribute__ ((pure, always_inline)); 1874 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR(uint64_t a) 1875 { 1876 if (a <= 19) 1877 return 0x87e1b0240020ll + 0x1000000ll * ((a) & 0x1f); 1878 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR", 1, a, 0, 0, 0, 0, 0); 1879 } 1880 1881 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_aidr_t 1882 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR(a) CSR_TYPE_RSL32b 1883 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR" 1884 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR(a) 0x0 /* PF_BAR0 */ 1885 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR(a) (a) 1886 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_AIDR(a) (a), -1, -1, -1 1887 1888 /** 1889 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_cust_cfg 1890 * 1891 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Cust Cfg Register 1892 * MPAM Custom Register - MPAM Disable 1893 */ 1894 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_cfg { 1895 uint32_t u; 1896 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_cfg_s { 1897 uint32_t dis_mpam : 1; 1898 uint32_t reserved_1_31 : 31; 1899 } s; 1900 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_cfg_s cn; */ 1901 }; 1902 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_cfg ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_cfg_t; 1903 1904 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG(uint64_t a) __attribute__ ((pure, always_inline)); 1905 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG(uint64_t a) 1906 { 1907 if (a <= 19) 1908 return 0x87e1b0240a10ll + 0x1000000ll * ((a) & 0x1f); 1909 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG", 1, a, 0, 0, 0, 0, 0); 1910 } 1911 1912 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_cfg_t 1913 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG(a) CSR_TYPE_RSL32b 1914 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG" 1915 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG(a) 0x0 /* PF_BAR0 */ 1916 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG(a) (a) 1917 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_CFG(a) (a), -1, -1, -1 1918 1919 /** 1920 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_cust_mbwc 1921 * 1922 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Cust Mbwc Register 1923 * MPAM Custom Register - Memory Bandwitdh Counter 1924 */ 1925 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_mbwc { 1926 uint32_t u; 1927 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_mbwc_s { 1928 uint32_t mbwc : 24; 1929 uint32_t reserved_24_31 : 8; 1930 } s; 1931 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_mbwc_s cn; */ 1932 }; 1933 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_mbwc ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_mbwc_t; 1934 1935 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC(uint64_t a) __attribute__ ((pure, always_inline)); 1936 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC(uint64_t a) 1937 { 1938 if (a <= 19) 1939 return 0x87e1b0240a08ll + 0x1000000ll * ((a) & 0x1f); 1940 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC", 1, a, 0, 0, 0, 0, 0); 1941 } 1942 1943 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_mbwc_t 1944 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC(a) CSR_TYPE_RSL32b 1945 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC" 1946 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC(a) 0x0 /* PF_BAR0 */ 1947 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC(a) (a) 1948 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_MBWC(a) (a), -1, -1, -1 1949 1950 /** 1951 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_cust_windw 1952 * 1953 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Cust Windw Register 1954 * MPAM Custom Register containing the current bandwidth accounting window period 1955 */ 1956 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_windw { 1957 uint32_t u; 1958 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_windw_s { 1959 uint32_t wind_cyc_count : 24; 1960 uint32_t reserved_24_31 : 8; 1961 } s; 1962 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_windw_s cn; */ 1963 }; 1964 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_windw ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_windw_t; 1965 1966 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW(uint64_t a) __attribute__ ((pure, always_inline)); 1967 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW(uint64_t a) 1968 { 1969 if (a <= 19) 1970 return 0x87e1b0240a0cll + 0x1000000ll * ((a) & 0x1f); 1971 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW", 1, a, 0, 0, 0, 0, 0); 1972 } 1973 1974 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_cust_windw_t 1975 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW(a) CSR_TYPE_RSL32b 1976 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW" 1977 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW(a) 0x0 /* PF_BAR0 */ 1978 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW(a) (a) 1979 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_CUST_WINDW(a) (a), -1, -1, -1 1980 1981 /** 1982 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_ecr 1983 * 1984 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Ecr Register 1985 * MPAM Error Control Register 1986 */ 1987 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_ecr { 1988 uint32_t u; 1989 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_ecr_s { 1990 uint32_t inten : 1; 1991 uint32_t reserved_1_31 : 31; 1992 } s; 1993 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_ecr_s cn; */ 1994 }; 1995 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_ecr ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_ecr_t; 1996 1997 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR(uint64_t a) __attribute__ ((pure, always_inline)); 1998 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR(uint64_t a) 1999 { 2000 if (a <= 19) 2001 return 0x87e1b02400f0ll + 0x1000000ll * ((a) & 0x1f); 2002 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR", 1, a, 0, 0, 0, 0, 0); 2003 } 2004 2005 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_ecr_t 2006 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR(a) CSR_TYPE_RSL32b 2007 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR" 2008 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR(a) 0x0 /* PF_BAR0 */ 2009 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR(a) (a) 2010 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ECR(a) (a), -1, -1, -1 2011 2012 /** 2013 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_esr 2014 * 2015 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Esr Register 2016 * MPAM Error Status Register 2017 */ 2018 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_esr { 2019 uint32_t u; 2020 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_esr_s { 2021 uint32_t partidmon : 16; 2022 uint32_t mpamf_esr_pmg : 8; 2023 uint32_t errcode : 4; 2024 uint32_t reserved_28_30 : 3; 2025 uint32_t ovrwr : 1; 2026 } s; 2027 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_esr_s cn; */ 2028 }; 2029 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_esr ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_esr_t; 2030 2031 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR(uint64_t a) __attribute__ ((pure, always_inline)); 2032 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR(uint64_t a) 2033 { 2034 if (a <= 19) 2035 return 0x87e1b02400f8ll + 0x1000000ll * ((a) & 0x1f); 2036 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR", 1, a, 0, 0, 0, 0, 0); 2037 } 2038 2039 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_esr_t 2040 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR(a) CSR_TYPE_RSL32b 2041 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR" 2042 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR(a) 0x0 /* PF_BAR0 */ 2043 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR(a) (a) 2044 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_ESR(a) (a), -1, -1, -1 2045 2046 /** 2047 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_idr 2048 * 2049 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Idr Register 2050 * MPAM features ID register for a memory system component. 2051 */ 2052 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr { 2053 uint32_t u; 2054 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_s { 2055 uint32_t partid_max : 16; 2056 uint32_t pmg_max : 8; 2057 uint32_t has_ccap_part : 1; 2058 uint32_t has_cport_part : 1; 2059 uint32_t has_mbw_part : 1; 2060 uint32_t has_pri_part : 1; 2061 uint32_t ext : 1; 2062 uint32_t has_impl_part : 1; 2063 uint32_t has_msmon : 1; 2064 uint32_t has_partid_nrw : 1; 2065 } s; 2066 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_s cn; */ 2067 }; 2068 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_t; 2069 2070 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 2071 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR(uint64_t a) 2072 { 2073 if (a <= 19) 2074 return 0x87e1b0240000ll + 0x1000000ll * ((a) & 0x1f); 2075 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR", 1, a, 0, 0, 0, 0, 0); 2076 } 2077 2078 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_t 2079 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR(a) CSR_TYPE_RSL32b 2080 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR" 2081 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR(a) 0x0 /* PF_BAR0 */ 2082 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR(a) (a) 2083 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR(a) (a), -1, -1, -1 2084 2085 /** 2086 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_idr_32 2087 * 2088 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Idr 32 Register 2089 * Extended MPAM features ID register for a memory system component present only when 2090 * MPAM V1.1 Version is enabled. At this offset MPAMF_IDR[63:32] can be accessed 2091 */ 2092 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_32 { 2093 uint32_t u; 2094 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_32_s { 2095 uint32_t has_ris : 1; 2096 uint32_t reserved_1_3 : 3; 2097 uint32_t has_no_impl_part : 1; 2098 uint32_t has_no_impl_msmon : 1; 2099 uint32_t has_extd_esr : 1; 2100 uint32_t has_esr : 1; 2101 uint32_t has_err_msi : 1; 2102 uint32_t reserved_9_31 : 23; 2103 } s; 2104 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_32_s cn; */ 2105 }; 2106 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_32 ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_32_t; 2107 2108 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32(uint64_t a) __attribute__ ((pure, always_inline)); 2109 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32(uint64_t a) 2110 { 2111 if (a <= 19) 2112 return 0x87e1b0240004ll + 0x1000000ll * ((a) & 0x1f); 2113 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32", 1, a, 0, 0, 0, 0, 0); 2114 } 2115 2116 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_idr_32_t 2117 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32(a) CSR_TYPE_RSL32b 2118 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32" 2119 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32(a) 0x0 /* PF_BAR0 */ 2120 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32(a) (a) 2121 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IDR_32(a) (a), -1, -1, -1 2122 2123 /** 2124 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_iidr 2125 * 2126 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Iidr Register 2127 * MPAM implementation ID register. 2128 */ 2129 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_iidr { 2130 uint32_t u; 2131 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_iidr_s { 2132 uint32_t implementer : 12; 2133 uint32_t revision : 4; 2134 uint32_t variant : 4; 2135 uint32_t productid : 12; 2136 } s; 2137 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_iidr_s cn; */ 2138 }; 2139 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_iidr ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_iidr_t; 2140 2141 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR(uint64_t a) __attribute__ ((pure, always_inline)); 2142 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR(uint64_t a) 2143 { 2144 if (a <= 19) 2145 return 0x87e1b0240018ll + 0x1000000ll * ((a) & 0x1f); 2146 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR", 1, a, 0, 0, 0, 0, 0); 2147 } 2148 2149 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_iidr_t 2150 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR(a) CSR_TYPE_RSL32b 2151 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR" 2152 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR(a) 0x0 /* PF_BAR0 */ 2153 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR(a) (a) 2154 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IIDR(a) (a), -1, -1, -1 2155 2156 /** 2157 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_impl_idr 2158 * 2159 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Impl Idr Register 2160 * MPAMF implementation-specific partitioning feature ID register for a memory system component. 2161 */ 2162 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_impl_idr { 2163 uint32_t u; 2164 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_impl_idr_s { 2165 uint32_t mpam_cust_offset : 32; 2166 } s; 2167 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_impl_idr_s cn; */ 2168 }; 2169 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_impl_idr ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_impl_idr_t; 2170 2171 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 2172 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR(uint64_t a) 2173 { 2174 if (a <= 19) 2175 return 0x87e1b0240028ll + 0x1000000ll * ((a) & 0x1f); 2176 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR", 1, a, 0, 0, 0, 0, 0); 2177 } 2178 2179 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_impl_idr_t 2180 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR(a) CSR_TYPE_RSL32b 2181 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR" 2182 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR(a) 0x0 /* PF_BAR0 */ 2183 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR(a) (a) 2184 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_IMPL_IDR(a) (a), -1, -1, -1 2185 2186 /** 2187 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_mbw_idr 2188 * 2189 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Mbw Idr Register 2190 * MPAM features memory bandwidth partitioning ID register 2191 */ 2192 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbw_idr { 2193 uint32_t u; 2194 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbw_idr_s { 2195 uint32_t bwa_wd : 6; 2196 uint32_t reserved_6_9 : 4; 2197 uint32_t has_min : 1; 2198 uint32_t has_max : 1; 2199 uint32_t has_pbm : 1; 2200 uint32_t has_prop : 1; 2201 uint32_t windwr : 1; 2202 uint32_t reserved_15 : 1; 2203 uint32_t bwpbm_wd : 13; 2204 uint32_t reserved_29_31 : 3; 2205 } s; 2206 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbw_idr_s cn; */ 2207 }; 2208 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbw_idr ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbw_idr_t; 2209 2210 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 2211 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR(uint64_t a) 2212 { 2213 if (a <= 19) 2214 return 0x87e1b0240040ll + 0x1000000ll * ((a) & 0x1f); 2215 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR", 1, a, 0, 0, 0, 0, 0); 2216 } 2217 2218 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbw_idr_t 2219 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR(a) CSR_TYPE_RSL32b 2220 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR" 2221 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR(a) 0x0 /* PF_BAR0 */ 2222 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR(a) (a) 2223 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBW_IDR(a) (a), -1, -1, -1 2224 2225 /** 2226 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_mbwumon_idr 2227 * 2228 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Mbwumon Idr Register 2229 * MPAM Memory BandWidth Monitor ID register. 2230 */ 2231 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbwumon_idr { 2232 uint32_t u; 2233 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbwumon_idr_s { 2234 uint32_t num_mon : 16; 2235 uint32_t reserved_16_25 : 10; 2236 uint32_t has_ofsr : 1; 2237 uint32_t reserved_27 : 1; 2238 uint32_t has_rwbw : 1; 2239 uint32_t lwd : 1; 2240 uint32_t has_long : 1; 2241 uint32_t has_capture : 1; 2242 } s; 2243 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbwumon_idr_s cn; */ 2244 }; 2245 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbwumon_idr ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbwumon_idr_t; 2246 2247 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 2248 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR(uint64_t a) 2249 { 2250 if (a <= 19) 2251 return 0x87e1b0240090ll + 0x1000000ll * ((a) & 0x1f); 2252 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR", 1, a, 0, 0, 0, 0, 0); 2253 } 2254 2255 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_mbwumon_idr_t 2256 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR(a) CSR_TYPE_RSL32b 2257 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR" 2258 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR(a) 0x0 /* PF_BAR0 */ 2259 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR(a) (a) 2260 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MBWUMON_IDR(a) (a), -1, -1, -1 2261 2262 /** 2263 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_mpamf_msmon_idr 2264 * 2265 * DSS Ddrctl Regb Chb Mpam Ns Mpamf Msmon Idr Register 2266 * MPAM Memory System Monitor ID register. 2267 */ 2268 union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_msmon_idr { 2269 uint32_t u; 2270 struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_msmon_idr_s { 2271 uint32_t reserved_0_15 : 16; 2272 uint32_t msmon_csu : 1; 2273 uint32_t msmon_mbwu : 1; 2274 uint32_t reserved_18_27 : 10; 2275 uint32_t has_oflow_sr : 1; 2276 uint32_t has_oflow_msi : 1; 2277 uint32_t no_hw_oflw_intr : 1; 2278 uint32_t has_local_capt_evnt : 1; 2279 } s; 2280 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_msmon_idr_s cn; */ 2281 }; 2282 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_msmon_idr ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_msmon_idr_t; 2283 2284 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 2285 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR(uint64_t a) 2286 { 2287 if (a <= 19) 2288 return 0x87e1b0240080ll + 0x1000000ll * ((a) & 0x1f); 2289 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR", 1, a, 0, 0, 0, 0, 0); 2290 } 2291 2292 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_mpamf_msmon_idr_t 2293 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR(a) CSR_TYPE_RSL32b 2294 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR" 2295 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR(a) 0x0 /* PF_BAR0 */ 2296 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR(a) (a) 2297 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MPAMF_MSMON_IDR(a) (a), -1, -1, -1 2298 2299 /** 2300 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_capt_evnt 2301 * 2302 * DSS Ddrctl Regb Chb Mpam Ns Msmon Capt Evnt Register 2303 * MPAM Monitor Capture Event register 2304 */ 2305 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_capt_evnt { 2306 uint32_t u; 2307 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_capt_evnt_s { 2308 uint32_t now : 1; 2309 uint32_t all : 1; 2310 uint32_t reserved_2_31 : 30; 2311 } s; 2312 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_capt_evnt_s cn; */ 2313 }; 2314 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_capt_evnt ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_capt_evnt_t; 2315 2316 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT(uint64_t a) __attribute__ ((pure, always_inline)); 2317 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT(uint64_t a) 2318 { 2319 if (a <= 19) 2320 return 0x87e1b0240808ll + 0x1000000ll * ((a) & 0x1f); 2321 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT", 1, a, 0, 0, 0, 0, 0); 2322 } 2323 2324 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_capt_evnt_t 2325 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT(a) CSR_TYPE_RSL32b 2326 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT" 2327 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT(a) 0x0 /* PF_BAR0 */ 2328 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT(a) (a) 2329 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CAPT_EVNT(a) (a), -1, -1, -1 2330 2331 /** 2332 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_ctl 2333 * 2334 * DSS Ddrctl Regb Chb Mpam Ns Msmon Cfg Mbwu Ctl Register 2335 * MPAM MBWU Configuration Control register 2336 */ 2337 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_ctl { 2338 uint32_t u; 2339 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_ctl_s { 2340 uint32_t mon_type : 8; 2341 uint32_t reserved_8_13 : 6; 2342 uint32_t oflow_intr_l : 1; 2343 uint32_t oflow_status_l : 1; 2344 uint32_t match_partid : 1; 2345 uint32_t match_pmg : 1; 2346 uint32_t reserved_18_23 : 6; 2347 uint32_t oflow_frz : 1; 2348 uint32_t reserved_25_26 : 2; 2349 uint32_t capt_reset : 1; 2350 uint32_t capt_evnt : 3; 2351 uint32_t en : 1; 2352 } s; 2353 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_ctl_s cn; */ 2354 }; 2355 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_ctl ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_ctl_t; 2356 2357 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL(uint64_t a) __attribute__ ((pure, always_inline)); 2358 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL(uint64_t a) 2359 { 2360 if (a <= 19) 2361 return 0x87e1b0240828ll + 0x1000000ll * ((a) & 0x1f); 2362 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL", 1, a, 0, 0, 0, 0, 0); 2363 } 2364 2365 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_ctl_t 2366 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL(a) CSR_TYPE_RSL32b 2367 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL" 2368 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL(a) 0x0 /* PF_BAR0 */ 2369 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL(a) (a) 2370 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_CTL(a) (a), -1, -1, -1 2371 2372 /** 2373 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_flt 2374 * 2375 * DSS Ddrctl Regb Chb Mpam Ns Msmon Cfg Mbwu Flt Register 2376 * MPAM MBWU Configuration Filter register 2377 */ 2378 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_flt { 2379 uint32_t u; 2380 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_flt_s { 2381 uint32_t partid : 16; 2382 uint32_t pmg : 8; 2383 uint32_t reserved_24_29 : 6; 2384 uint32_t rwbw : 2; 2385 } s; 2386 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_flt_s cn; */ 2387 }; 2388 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_flt ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_flt_t; 2389 2390 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT(uint64_t a) __attribute__ ((pure, always_inline)); 2391 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT(uint64_t a) 2392 { 2393 if (a <= 19) 2394 return 0x87e1b0240820ll + 0x1000000ll * ((a) & 0x1f); 2395 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT", 1, a, 0, 0, 0, 0, 0); 2396 } 2397 2398 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mbwu_flt_t 2399 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT(a) CSR_TYPE_RSL32b 2400 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT" 2401 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT(a) 0x0 /* PF_BAR0 */ 2402 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT(a) (a) 2403 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MBWU_FLT(a) (a), -1, -1, -1 2404 2405 /** 2406 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_cfg_mon_sel 2407 * 2408 * DSS Ddrctl Regb Chb Mpam Ns Msmon Cfg Mon Sel Register 2409 * MPAM Monitor configuration selection register 2410 */ 2411 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mon_sel { 2412 uint32_t u; 2413 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mon_sel_s { 2414 uint32_t mon_sel : 16; 2415 uint32_t reserved_16_31 : 16; 2416 } s; 2417 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mon_sel_s cn; */ 2418 }; 2419 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mon_sel ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mon_sel_t; 2420 2421 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL(uint64_t a) __attribute__ ((pure, always_inline)); 2422 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL(uint64_t a) 2423 { 2424 if (a <= 19) 2425 return 0x87e1b0240800ll + 0x1000000ll * ((a) & 0x1f); 2426 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL", 1, a, 0, 0, 0, 0, 0); 2427 } 2428 2429 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_cfg_mon_sel_t 2430 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL(a) CSR_TYPE_RSL32b 2431 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL" 2432 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL(a) 0x0 /* PF_BAR0 */ 2433 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL(a) (a) 2434 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_CFG_MON_SEL(a) (a), -1, -1, -1 2435 2436 /** 2437 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l 2438 * 2439 * DSS Ddrctl Regb Chb Mpam Ns Msmon Mbwu L Register 2440 * MPAM MBWU Long register 2441 */ 2442 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l { 2443 uint32_t u; 2444 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_s { 2445 uint32_t value : 32; 2446 } s; 2447 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_s cn; */ 2448 }; 2449 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_t; 2450 2451 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L(uint64_t a) __attribute__ ((pure, always_inline)); 2452 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L(uint64_t a) 2453 { 2454 if (a <= 19) 2455 return 0x87e1b0240880ll + 0x1000000ll * ((a) & 0x1f); 2456 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L", 1, a, 0, 0, 0, 0, 0); 2457 } 2458 2459 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_t 2460 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L(a) CSR_TYPE_RSL32b 2461 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L" 2462 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L(a) 0x0 /* PF_BAR0 */ 2463 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L(a) (a) 2464 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L(a) (a), -1, -1, -1 2465 2466 /** 2467 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_32 2468 * 2469 * DSS Ddrctl Regb Chb Mpam Ns Msmon Mbwu L 32 Register 2470 * MPAM MBWU Long MSB 32bits register 2471 */ 2472 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_32 { 2473 uint32_t u; 2474 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_32_s { 2475 uint32_t value : 31; 2476 uint32_t nrdy : 1; 2477 } s; 2478 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_32_s cn; */ 2479 }; 2480 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_32 ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_32_t; 2481 2482 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32(uint64_t a) __attribute__ ((pure, always_inline)); 2483 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32(uint64_t a) 2484 { 2485 if (a <= 19) 2486 return 0x87e1b0240884ll + 0x1000000ll * ((a) & 0x1f); 2487 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32", 1, a, 0, 0, 0, 0, 0); 2488 } 2489 2490 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_32_t 2491 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32(a) CSR_TYPE_RSL32b 2492 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32" 2493 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32(a) 0x0 /* PF_BAR0 */ 2494 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32(a) (a) 2495 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_32(a) (a), -1, -1, -1 2496 2497 /** 2498 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture 2499 * 2500 * DSS Ddrctl Regb Chb Mpam Ns Msmon Mbwu L Capture Register 2501 * MPAM MBWU Long Capture register 2502 */ 2503 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture { 2504 uint32_t u; 2505 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_s { 2506 uint32_t value : 32; 2507 } s; 2508 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_s cn; */ 2509 }; 2510 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_t; 2511 2512 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE(uint64_t a) __attribute__ ((pure, always_inline)); 2513 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE(uint64_t a) 2514 { 2515 if (a <= 19) 2516 return 0x87e1b0240890ll + 0x1000000ll * ((a) & 0x1f); 2517 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE", 1, a, 0, 0, 0, 0, 0); 2518 } 2519 2520 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_t 2521 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE(a) CSR_TYPE_RSL32b 2522 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE" 2523 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE(a) 0x0 /* PF_BAR0 */ 2524 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE(a) (a) 2525 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE(a) (a), -1, -1, -1 2526 2527 /** 2528 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_32 2529 * 2530 * DSS Ddrctl Regb Chb Mpam Ns Msmon Mbwu L Capture 32 Register 2531 * MPAM MBWU Long Capture MSB 32bits register 2532 */ 2533 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_32 { 2534 uint32_t u; 2535 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_32_s { 2536 uint32_t value : 31; 2537 uint32_t nrdy : 1; 2538 } s; 2539 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_32_s cn; */ 2540 }; 2541 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_32 ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_32_t; 2542 2543 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32(uint64_t a) __attribute__ ((pure, always_inline)); 2544 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32(uint64_t a) 2545 { 2546 if (a <= 19) 2547 return 0x87e1b0240894ll + 0x1000000ll * ((a) & 0x1f); 2548 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32", 1, a, 0, 0, 0, 0, 0); 2549 } 2550 2551 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_l_capture_32_t 2552 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32(a) CSR_TYPE_RSL32b 2553 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32" 2554 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32(a) 0x0 /* PF_BAR0 */ 2555 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32(a) (a) 2556 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_L_CAPTURE_32(a) (a), -1, -1, -1 2557 2558 /** 2559 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_mbwu_ofsr 2560 * 2561 * DSS Ddrctl Regb Chb Mpam Ns Msmon Mbwu Ofsr Register 2562 * MPAM MBWU OFSR register 2563 */ 2564 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_ofsr { 2565 uint32_t u; 2566 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_ofsr_s { 2567 uint32_t ofpnd : 32; 2568 } s; 2569 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_ofsr_s cn; */ 2570 }; 2571 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_ofsr ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_ofsr_t; 2572 2573 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR(uint64_t a) __attribute__ ((pure, always_inline)); 2574 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR(uint64_t a) 2575 { 2576 if (a <= 19) 2577 return 0x87e1b0240898ll + 0x1000000ll * ((a) & 0x1f); 2578 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR", 1, a, 0, 0, 0, 0, 0); 2579 } 2580 2581 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_mbwu_ofsr_t 2582 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR(a) CSR_TYPE_RSL32b 2583 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR" 2584 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR(a) 0x0 /* PF_BAR0 */ 2585 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR(a) (a) 2586 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_MBWU_OFSR(a) (a), -1, -1, -1 2587 2588 /** 2589 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_ns_msmon_oflow_sr 2590 * 2591 * DSS Ddrctl Regb Chb Mpam Ns Msmon Oflow Sr Register 2592 * MPAM MSMON OFLOW SR register 2593 */ 2594 union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_oflow_sr { 2595 uint32_t u; 2596 struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_oflow_sr_s { 2597 uint32_t reserved_0_29 : 30; 2598 uint32_t mbwu_oflow_pnd : 1; 2599 uint32_t reserved_31 : 1; 2600 } s; 2601 /* struct ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_oflow_sr_s cn; */ 2602 }; 2603 typedef union ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_oflow_sr ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_oflow_sr_t; 2604 2605 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR(uint64_t a) __attribute__ ((pure, always_inline)); 2606 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR(uint64_t a) 2607 { 2608 if (a <= 19) 2609 return 0x87e1b02408f0ll + 0x1000000ll * ((a) & 0x1f); 2610 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR", 1, a, 0, 0, 0, 0, 0); 2611 } 2612 2613 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR(a) ody_dssx_ddrctl_regb_chb_mpam_ns_msmon_oflow_sr_t 2614 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR(a) CSR_TYPE_RSL32b 2615 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR" 2616 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR(a) 0x0 /* PF_BAR0 */ 2617 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR(a) (a) 2618 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_NS_MSMON_OFLOW_SR(a) (a), -1, -1, -1 2619 2620 /** 2621 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_max 2622 * 2623 * DSS Ddrctl Regb Chb Mpam S Mpamcfg Mbw Max Register 2624 * MPAM memory maximum bandwidth partitioning partition configuration register. 2625 */ 2626 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_max { 2627 uint32_t u; 2628 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_max_s { 2629 uint32_t unimpl : 8; 2630 uint32_t max : 8; 2631 uint32_t reserved_16_31 : 16; 2632 } s; 2633 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_max_s cn; */ 2634 }; 2635 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_max ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_max_t; 2636 2637 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX(uint64_t a) __attribute__ ((pure, always_inline)); 2638 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX(uint64_t a) 2639 { 2640 if (a <= 19) 2641 return 0x87e1b0250208ll + 0x1000000ll * ((a) & 0x1f); 2642 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX", 1, a, 0, 0, 0, 0, 0); 2643 } 2644 2645 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_max_t 2646 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX(a) CSR_TYPE_RSL32b 2647 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX" 2648 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX(a) 0x0 /* PF_BAR0 */ 2649 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX(a) (a) 2650 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MAX(a) (a), -1, -1, -1 2651 2652 /** 2653 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_min 2654 * 2655 * DSS Ddrctl Regb Chb Mpam S Mpamcfg Mbw Min Register 2656 * MPAM memory minimum bandwidth partitioning partition configuration register. 2657 */ 2658 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_min { 2659 uint32_t u; 2660 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_min_s { 2661 uint32_t unimpl : 8; 2662 uint32_t min : 8; 2663 uint32_t reserved_16_31 : 16; 2664 } s; 2665 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_min_s cn; */ 2666 }; 2667 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_min ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_min_t; 2668 2669 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN(uint64_t a) __attribute__ ((pure, always_inline)); 2670 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN(uint64_t a) 2671 { 2672 if (a <= 19) 2673 return 0x87e1b0250200ll + 0x1000000ll * ((a) & 0x1f); 2674 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN", 1, a, 0, 0, 0, 0, 0); 2675 } 2676 2677 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_min_t 2678 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN(a) CSR_TYPE_RSL32b 2679 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN" 2680 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN(a) 0x0 /* PF_BAR0 */ 2681 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN(a) (a) 2682 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_MIN(a) (a), -1, -1, -1 2683 2684 /** 2685 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_winwd 2686 * 2687 * DSS Ddrctl Regb Chb Mpam S Mpamcfg Mbw Winwd Register 2688 * MPAM memory bandwidth partitioning window width register. 2689 * 2690 * Note: This IP uses a custom implementation to set BW accounting widow. 2691 * MPAMCFG_MBW_WINWD hence is not compliant to the MPAM spec. SW should not use 2692 * MPAMCFG_MBW_WINWD and instead rely on MPAMF_CUST_WINDW register 2693 */ 2694 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_winwd { 2695 uint32_t u; 2696 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_winwd_s { 2697 uint32_t us_frac : 8; 2698 uint32_t us_int : 16; 2699 uint32_t reserved_24_31 : 8; 2700 } s; 2701 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_winwd_s cn; */ 2702 }; 2703 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_winwd ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_winwd_t; 2704 2705 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD(uint64_t a) __attribute__ ((pure, always_inline)); 2706 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD(uint64_t a) 2707 { 2708 if (a <= 19) 2709 return 0x87e1b0250220ll + 0x1000000ll * ((a) & 0x1f); 2710 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD", 1, a, 0, 0, 0, 0, 0); 2711 } 2712 2713 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_mbw_winwd_t 2714 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD(a) CSR_TYPE_RSL32b 2715 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD" 2716 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD(a) 0x0 /* PF_BAR0 */ 2717 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD(a) (a) 2718 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_MBW_WINWD(a) (a), -1, -1, -1 2719 2720 /** 2721 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamcfg_part_sel 2722 * 2723 * DSS Ddrctl Regb Chb Mpam S Mpamcfg Part Sel Register 2724 * MPAM partition configuration selection register 2725 */ 2726 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_part_sel { 2727 uint32_t u; 2728 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_part_sel_s { 2729 uint32_t partid_sel : 16; 2730 uint32_t internal : 1; 2731 uint32_t reserved_17_31 : 15; 2732 } s; 2733 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_part_sel_s cn; */ 2734 }; 2735 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_part_sel ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_part_sel_t; 2736 2737 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL(uint64_t a) __attribute__ ((pure, always_inline)); 2738 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL(uint64_t a) 2739 { 2740 if (a <= 19) 2741 return 0x87e1b0250100ll + 0x1000000ll * ((a) & 0x1f); 2742 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL", 1, a, 0, 0, 0, 0, 0); 2743 } 2744 2745 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamcfg_part_sel_t 2746 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL(a) CSR_TYPE_RSL32b 2747 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL" 2748 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL(a) 0x0 /* PF_BAR0 */ 2749 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL(a) (a) 2750 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMCFG_PART_SEL(a) (a), -1, -1, -1 2751 2752 /** 2753 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_aidr 2754 * 2755 * DSS Ddrctl Regb Chb Mpam S Mpamf Aidr Register 2756 * MPAM architecture ID register. 2757 */ 2758 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_aidr { 2759 uint32_t u; 2760 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_aidr_s { 2761 uint32_t archminorrev : 4; 2762 uint32_t archmajorrev : 4; 2763 uint32_t reserved_8_31 : 24; 2764 } s; 2765 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_aidr_s cn; */ 2766 }; 2767 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_aidr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_aidr_t; 2768 2769 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR(uint64_t a) __attribute__ ((pure, always_inline)); 2770 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR(uint64_t a) 2771 { 2772 if (a <= 19) 2773 return 0x87e1b0250020ll + 0x1000000ll * ((a) & 0x1f); 2774 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR", 1, a, 0, 0, 0, 0, 0); 2775 } 2776 2777 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_aidr_t 2778 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR(a) CSR_TYPE_RSL32b 2779 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR" 2780 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR(a) 0x0 /* PF_BAR0 */ 2781 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR(a) (a) 2782 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_AIDR(a) (a), -1, -1, -1 2783 2784 /** 2785 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_cust_cfg 2786 * 2787 * DSS Ddrctl Regb Chb Mpam S Mpamf Cust Cfg Register 2788 * MPAM Custom Register - MPAM Disable 2789 */ 2790 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_cfg { 2791 uint32_t u; 2792 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_cfg_s { 2793 uint32_t dis_mpam : 1; 2794 uint32_t reserved_1_31 : 31; 2795 } s; 2796 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_cfg_s cn; */ 2797 }; 2798 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_cfg ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_cfg_t; 2799 2800 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG(uint64_t a) __attribute__ ((pure, always_inline)); 2801 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG(uint64_t a) 2802 { 2803 if (a <= 19) 2804 return 0x87e1b0250a10ll + 0x1000000ll * ((a) & 0x1f); 2805 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG", 1, a, 0, 0, 0, 0, 0); 2806 } 2807 2808 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_cfg_t 2809 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG(a) CSR_TYPE_RSL32b 2810 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG" 2811 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG(a) 0x0 /* PF_BAR0 */ 2812 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG(a) (a) 2813 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_CFG(a) (a), -1, -1, -1 2814 2815 /** 2816 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_cust_mbwc 2817 * 2818 * DSS Ddrctl Regb Chb Mpam S Mpamf Cust Mbwc Register 2819 * MPAM Custom Register - Memory Bandwitdh Counter 2820 */ 2821 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_mbwc { 2822 uint32_t u; 2823 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_mbwc_s { 2824 uint32_t mbwc : 24; 2825 uint32_t reserved_24_31 : 8; 2826 } s; 2827 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_mbwc_s cn; */ 2828 }; 2829 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_mbwc ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_mbwc_t; 2830 2831 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC(uint64_t a) __attribute__ ((pure, always_inline)); 2832 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC(uint64_t a) 2833 { 2834 if (a <= 19) 2835 return 0x87e1b0250a08ll + 0x1000000ll * ((a) & 0x1f); 2836 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC", 1, a, 0, 0, 0, 0, 0); 2837 } 2838 2839 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_mbwc_t 2840 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC(a) CSR_TYPE_RSL32b 2841 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC" 2842 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC(a) 0x0 /* PF_BAR0 */ 2843 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC(a) (a) 2844 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_MBWC(a) (a), -1, -1, -1 2845 2846 /** 2847 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_cust_windw 2848 * 2849 * DSS Ddrctl Regb Chb Mpam S Mpamf Cust Windw Register 2850 * MPAM Custom Register containing the current bandwidth accounting window period 2851 */ 2852 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_windw { 2853 uint32_t u; 2854 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_windw_s { 2855 uint32_t wind_cyc_count : 24; 2856 uint32_t reserved_24_31 : 8; 2857 } s; 2858 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_windw_s cn; */ 2859 }; 2860 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_windw ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_windw_t; 2861 2862 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW(uint64_t a) __attribute__ ((pure, always_inline)); 2863 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW(uint64_t a) 2864 { 2865 if (a <= 19) 2866 return 0x87e1b0250a0cll + 0x1000000ll * ((a) & 0x1f); 2867 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW", 1, a, 0, 0, 0, 0, 0); 2868 } 2869 2870 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_cust_windw_t 2871 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW(a) CSR_TYPE_RSL32b 2872 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW" 2873 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW(a) 0x0 /* PF_BAR0 */ 2874 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW(a) (a) 2875 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_CUST_WINDW(a) (a), -1, -1, -1 2876 2877 /** 2878 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_ecr 2879 * 2880 * DSS Ddrctl Regb Chb Mpam S Mpamf Ecr Register 2881 * MPAM Error Control Register 2882 */ 2883 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_ecr { 2884 uint32_t u; 2885 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_ecr_s { 2886 uint32_t inten : 1; 2887 uint32_t reserved_1_31 : 31; 2888 } s; 2889 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_ecr_s cn; */ 2890 }; 2891 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_ecr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_ecr_t; 2892 2893 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR(uint64_t a) __attribute__ ((pure, always_inline)); 2894 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR(uint64_t a) 2895 { 2896 if (a <= 19) 2897 return 0x87e1b02500f0ll + 0x1000000ll * ((a) & 0x1f); 2898 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR", 1, a, 0, 0, 0, 0, 0); 2899 } 2900 2901 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_ecr_t 2902 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR(a) CSR_TYPE_RSL32b 2903 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR" 2904 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR(a) 0x0 /* PF_BAR0 */ 2905 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR(a) (a) 2906 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ECR(a) (a), -1, -1, -1 2907 2908 /** 2909 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_esr 2910 * 2911 * DSS Ddrctl Regb Chb Mpam S Mpamf Esr Register 2912 * MPAM Error Status Register 2913 */ 2914 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_esr { 2915 uint32_t u; 2916 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_esr_s { 2917 uint32_t partidmon : 16; 2918 uint32_t mpamf_esr_pmg : 8; 2919 uint32_t errcode : 4; 2920 uint32_t reserved_28_30 : 3; 2921 uint32_t ovrwr : 1; 2922 } s; 2923 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_esr_s cn; */ 2924 }; 2925 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_esr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_esr_t; 2926 2927 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR(uint64_t a) __attribute__ ((pure, always_inline)); 2928 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR(uint64_t a) 2929 { 2930 if (a <= 19) 2931 return 0x87e1b02500f8ll + 0x1000000ll * ((a) & 0x1f); 2932 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR", 1, a, 0, 0, 0, 0, 0); 2933 } 2934 2935 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_esr_t 2936 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR(a) CSR_TYPE_RSL32b 2937 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR" 2938 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR(a) 0x0 /* PF_BAR0 */ 2939 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR(a) (a) 2940 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_ESR(a) (a), -1, -1, -1 2941 2942 /** 2943 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_idr 2944 * 2945 * DSS Ddrctl Regb Chb Mpam S Mpamf Idr Register 2946 * MPAM features ID register for a memory system component. 2947 */ 2948 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr { 2949 uint32_t u; 2950 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_s { 2951 uint32_t partid_max : 16; 2952 uint32_t pmg_max : 8; 2953 uint32_t has_ccap_part : 1; 2954 uint32_t has_cport_part : 1; 2955 uint32_t has_mbw_part : 1; 2956 uint32_t has_pri_part : 1; 2957 uint32_t ext : 1; 2958 uint32_t has_impl_part : 1; 2959 uint32_t has_msmon : 1; 2960 uint32_t has_partid_nrw : 1; 2961 } s; 2962 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_s cn; */ 2963 }; 2964 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_t; 2965 2966 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 2967 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR(uint64_t a) 2968 { 2969 if (a <= 19) 2970 return 0x87e1b0250000ll + 0x1000000ll * ((a) & 0x1f); 2971 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR", 1, a, 0, 0, 0, 0, 0); 2972 } 2973 2974 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_t 2975 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR(a) CSR_TYPE_RSL32b 2976 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR" 2977 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR(a) 0x0 /* PF_BAR0 */ 2978 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR(a) (a) 2979 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR(a) (a), -1, -1, -1 2980 2981 /** 2982 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_idr_32 2983 * 2984 * DSS Ddrctl Regb Chb Mpam S Mpamf Idr 32 Register 2985 * Extended MPAM features ID register for a memory system component present only when 2986 * MPAM V1.1 Version is enabled. At this offset MPAMF_IDR[63:32] can be accessed 2987 */ 2988 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_32 { 2989 uint32_t u; 2990 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_32_s { 2991 uint32_t has_ris : 1; 2992 uint32_t reserved_1_3 : 3; 2993 uint32_t has_no_impl_part : 1; 2994 uint32_t has_no_impl_msmon : 1; 2995 uint32_t has_extd_esr : 1; 2996 uint32_t has_esr : 1; 2997 uint32_t has_err_msi : 1; 2998 uint32_t reserved_9_31 : 23; 2999 } s; 3000 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_32_s cn; */ 3001 }; 3002 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_32 ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_32_t; 3003 3004 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32(uint64_t a) __attribute__ ((pure, always_inline)); 3005 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32(uint64_t a) 3006 { 3007 if (a <= 19) 3008 return 0x87e1b0250004ll + 0x1000000ll * ((a) & 0x1f); 3009 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32", 1, a, 0, 0, 0, 0, 0); 3010 } 3011 3012 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_idr_32_t 3013 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32(a) CSR_TYPE_RSL32b 3014 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32" 3015 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32(a) 0x0 /* PF_BAR0 */ 3016 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32(a) (a) 3017 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IDR_32(a) (a), -1, -1, -1 3018 3019 /** 3020 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_iidr 3021 * 3022 * DSS Ddrctl Regb Chb Mpam S Mpamf Iidr Register 3023 * MPAM implementation ID register. 3024 */ 3025 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_iidr { 3026 uint32_t u; 3027 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_iidr_s { 3028 uint32_t implementer : 12; 3029 uint32_t revision : 4; 3030 uint32_t variant : 4; 3031 uint32_t productid : 12; 3032 } s; 3033 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_iidr_s cn; */ 3034 }; 3035 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_iidr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_iidr_t; 3036 3037 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR(uint64_t a) __attribute__ ((pure, always_inline)); 3038 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR(uint64_t a) 3039 { 3040 if (a <= 19) 3041 return 0x87e1b0250018ll + 0x1000000ll * ((a) & 0x1f); 3042 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR", 1, a, 0, 0, 0, 0, 0); 3043 } 3044 3045 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_iidr_t 3046 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR(a) CSR_TYPE_RSL32b 3047 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR" 3048 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR(a) 0x0 /* PF_BAR0 */ 3049 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR(a) (a) 3050 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IIDR(a) (a), -1, -1, -1 3051 3052 /** 3053 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_impl_idr 3054 * 3055 * DSS Ddrctl Regb Chb Mpam S Mpamf Impl Idr Register 3056 * MPAMF implementation-specific partitioning feature ID register for a memory system component. 3057 */ 3058 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_impl_idr { 3059 uint32_t u; 3060 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_impl_idr_s { 3061 uint32_t mpam_cust_offset : 32; 3062 } s; 3063 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_impl_idr_s cn; */ 3064 }; 3065 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_impl_idr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_impl_idr_t; 3066 3067 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 3068 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR(uint64_t a) 3069 { 3070 if (a <= 19) 3071 return 0x87e1b0250028ll + 0x1000000ll * ((a) & 0x1f); 3072 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR", 1, a, 0, 0, 0, 0, 0); 3073 } 3074 3075 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_impl_idr_t 3076 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR(a) CSR_TYPE_RSL32b 3077 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR" 3078 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR(a) 0x0 /* PF_BAR0 */ 3079 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR(a) (a) 3080 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_IMPL_IDR(a) (a), -1, -1, -1 3081 3082 /** 3083 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_mbw_idr 3084 * 3085 * DSS Ddrctl Regb Chb Mpam S Mpamf Mbw Idr Register 3086 * MPAM features memory bandwidth partitioning ID register 3087 */ 3088 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbw_idr { 3089 uint32_t u; 3090 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbw_idr_s { 3091 uint32_t bwa_wd : 6; 3092 uint32_t reserved_6_9 : 4; 3093 uint32_t has_min : 1; 3094 uint32_t has_max : 1; 3095 uint32_t has_pbm : 1; 3096 uint32_t has_prop : 1; 3097 uint32_t windwr : 1; 3098 uint32_t reserved_15 : 1; 3099 uint32_t bwpbm_wd : 13; 3100 uint32_t reserved_29_31 : 3; 3101 } s; 3102 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbw_idr_s cn; */ 3103 }; 3104 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbw_idr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbw_idr_t; 3105 3106 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 3107 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR(uint64_t a) 3108 { 3109 if (a <= 19) 3110 return 0x87e1b0250040ll + 0x1000000ll * ((a) & 0x1f); 3111 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR", 1, a, 0, 0, 0, 0, 0); 3112 } 3113 3114 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbw_idr_t 3115 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR(a) CSR_TYPE_RSL32b 3116 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR" 3117 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR(a) 0x0 /* PF_BAR0 */ 3118 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR(a) (a) 3119 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBW_IDR(a) (a), -1, -1, -1 3120 3121 /** 3122 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_mbwumon_idr 3123 * 3124 * DSS Ddrctl Regb Chb Mpam S Mpamf Mbwumon Idr Register 3125 * MPAM Memory BandWidth Monitor ID register. 3126 */ 3127 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbwumon_idr { 3128 uint32_t u; 3129 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbwumon_idr_s { 3130 uint32_t num_mon : 16; 3131 uint32_t reserved_16_25 : 10; 3132 uint32_t has_ofsr : 1; 3133 uint32_t reserved_27 : 1; 3134 uint32_t has_rwbw : 1; 3135 uint32_t lwd : 1; 3136 uint32_t has_long : 1; 3137 uint32_t has_capture : 1; 3138 } s; 3139 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbwumon_idr_s cn; */ 3140 }; 3141 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbwumon_idr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbwumon_idr_t; 3142 3143 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 3144 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR(uint64_t a) 3145 { 3146 if (a <= 19) 3147 return 0x87e1b0250090ll + 0x1000000ll * ((a) & 0x1f); 3148 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR", 1, a, 0, 0, 0, 0, 0); 3149 } 3150 3151 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_mbwumon_idr_t 3152 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR(a) CSR_TYPE_RSL32b 3153 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR" 3154 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR(a) 0x0 /* PF_BAR0 */ 3155 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR(a) (a) 3156 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MBWUMON_IDR(a) (a), -1, -1, -1 3157 3158 /** 3159 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_msmon_idr 3160 * 3161 * DSS Ddrctl Regb Chb Mpam S Mpamf Msmon Idr Register 3162 * MPAM Memory System Monitor ID register. 3163 */ 3164 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_msmon_idr { 3165 uint32_t u; 3166 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_msmon_idr_s { 3167 uint32_t reserved_0_15 : 16; 3168 uint32_t msmon_csu : 1; 3169 uint32_t msmon_mbwu : 1; 3170 uint32_t reserved_18_27 : 10; 3171 uint32_t has_oflow_sr : 1; 3172 uint32_t has_oflow_msi : 1; 3173 uint32_t no_hw_oflw_intr : 1; 3174 uint32_t has_local_capt_evnt : 1; 3175 } s; 3176 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_msmon_idr_s cn; */ 3177 }; 3178 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_msmon_idr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_msmon_idr_t; 3179 3180 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR(uint64_t a) __attribute__ ((pure, always_inline)); 3181 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR(uint64_t a) 3182 { 3183 if (a <= 19) 3184 return 0x87e1b0250080ll + 0x1000000ll * ((a) & 0x1f); 3185 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR", 1, a, 0, 0, 0, 0, 0); 3186 } 3187 3188 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_msmon_idr_t 3189 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR(a) CSR_TYPE_RSL32b 3190 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR" 3191 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR(a) 0x0 /* PF_BAR0 */ 3192 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR(a) (a) 3193 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_MSMON_IDR(a) (a), -1, -1, -1 3194 3195 /** 3196 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_mpamf_sidr 3197 * 3198 * DSS Ddrctl Regb Chb Mpam S Mpamf Sidr Register 3199 * MPAM features secure ID register. 3200 */ 3201 union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_sidr { 3202 uint32_t u; 3203 struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_sidr_s { 3204 uint32_t s_partid_max : 16; 3205 uint32_t s_pmg_max : 8; 3206 uint32_t reserved_24_31 : 8; 3207 } s; 3208 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_sidr_s cn; */ 3209 }; 3210 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_sidr ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_sidr_t; 3211 3212 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR(uint64_t a) __attribute__ ((pure, always_inline)); 3213 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR(uint64_t a) 3214 { 3215 if (a <= 19) 3216 return 0x87e1b0250008ll + 0x1000000ll * ((a) & 0x1f); 3217 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR", 1, a, 0, 0, 0, 0, 0); 3218 } 3219 3220 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR(a) ody_dssx_ddrctl_regb_chb_mpam_s_mpamf_sidr_t 3221 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR(a) CSR_TYPE_RSL32b 3222 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR" 3223 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR(a) 0x0 /* PF_BAR0 */ 3224 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR(a) (a) 3225 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MPAMF_SIDR(a) (a), -1, -1, -1 3226 3227 /** 3228 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_capt_evnt 3229 * 3230 * DSS Ddrctl Regb Chb Mpam S Msmon Capt Evnt Register 3231 * MPAM Monitor Capture Event register 3232 */ 3233 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_capt_evnt { 3234 uint32_t u; 3235 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_capt_evnt_s { 3236 uint32_t now : 1; 3237 uint32_t all : 1; 3238 uint32_t reserved_2_31 : 30; 3239 } s; 3240 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_capt_evnt_s cn; */ 3241 }; 3242 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_capt_evnt ody_dssx_ddrctl_regb_chb_mpam_s_msmon_capt_evnt_t; 3243 3244 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT(uint64_t a) __attribute__ ((pure, always_inline)); 3245 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT(uint64_t a) 3246 { 3247 if (a <= 19) 3248 return 0x87e1b0250808ll + 0x1000000ll * ((a) & 0x1f); 3249 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT", 1, a, 0, 0, 0, 0, 0); 3250 } 3251 3252 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_capt_evnt_t 3253 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT(a) CSR_TYPE_RSL32b 3254 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT" 3255 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT(a) 0x0 /* PF_BAR0 */ 3256 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT(a) (a) 3257 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CAPT_EVNT(a) (a), -1, -1, -1 3258 3259 /** 3260 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_ctl 3261 * 3262 * DSS Ddrctl Regb Chb Mpam S Msmon Cfg Mbwu Ctl Register 3263 * MPAM MBWU Configuration Control register 3264 */ 3265 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_ctl { 3266 uint32_t u; 3267 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_ctl_s { 3268 uint32_t mon_type : 8; 3269 uint32_t reserved_8_13 : 6; 3270 uint32_t oflow_intr_l : 1; 3271 uint32_t oflow_status_l : 1; 3272 uint32_t match_partid : 1; 3273 uint32_t match_pmg : 1; 3274 uint32_t reserved_18_23 : 6; 3275 uint32_t oflow_frz : 1; 3276 uint32_t reserved_25_26 : 2; 3277 uint32_t capt_reset : 1; 3278 uint32_t capt_evnt : 3; 3279 uint32_t en : 1; 3280 } s; 3281 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_ctl_s cn; */ 3282 }; 3283 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_ctl ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_ctl_t; 3284 3285 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL(uint64_t a) __attribute__ ((pure, always_inline)); 3286 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL(uint64_t a) 3287 { 3288 if (a <= 19) 3289 return 0x87e1b0250828ll + 0x1000000ll * ((a) & 0x1f); 3290 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL", 1, a, 0, 0, 0, 0, 0); 3291 } 3292 3293 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_ctl_t 3294 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL(a) CSR_TYPE_RSL32b 3295 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL" 3296 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL(a) 0x0 /* PF_BAR0 */ 3297 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL(a) (a) 3298 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_CTL(a) (a), -1, -1, -1 3299 3300 /** 3301 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_flt 3302 * 3303 * DSS Ddrctl Regb Chb Mpam S Msmon Cfg Mbwu Flt Register 3304 * MPAM MBWU Configuration Filter register 3305 */ 3306 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_flt { 3307 uint32_t u; 3308 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_flt_s { 3309 uint32_t partid : 16; 3310 uint32_t pmg : 8; 3311 uint32_t reserved_24_29 : 6; 3312 uint32_t rwbw : 2; 3313 } s; 3314 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_flt_s cn; */ 3315 }; 3316 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_flt ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_flt_t; 3317 3318 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT(uint64_t a) __attribute__ ((pure, always_inline)); 3319 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT(uint64_t a) 3320 { 3321 if (a <= 19) 3322 return 0x87e1b0250820ll + 0x1000000ll * ((a) & 0x1f); 3323 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT", 1, a, 0, 0, 0, 0, 0); 3324 } 3325 3326 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mbwu_flt_t 3327 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT(a) CSR_TYPE_RSL32b 3328 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT" 3329 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT(a) 0x0 /* PF_BAR0 */ 3330 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT(a) (a) 3331 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MBWU_FLT(a) (a), -1, -1, -1 3332 3333 /** 3334 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_cfg_mon_sel 3335 * 3336 * DSS Ddrctl Regb Chb Mpam S Msmon Cfg Mon Sel Register 3337 * MPAM Monitor configuration selection register 3338 */ 3339 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mon_sel { 3340 uint32_t u; 3341 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mon_sel_s { 3342 uint32_t mon_sel : 16; 3343 uint32_t reserved_16_31 : 16; 3344 } s; 3345 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mon_sel_s cn; */ 3346 }; 3347 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mon_sel ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mon_sel_t; 3348 3349 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL(uint64_t a) __attribute__ ((pure, always_inline)); 3350 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL(uint64_t a) 3351 { 3352 if (a <= 19) 3353 return 0x87e1b0250800ll + 0x1000000ll * ((a) & 0x1f); 3354 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL", 1, a, 0, 0, 0, 0, 0); 3355 } 3356 3357 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_cfg_mon_sel_t 3358 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL(a) CSR_TYPE_RSL32b 3359 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL" 3360 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL(a) 0x0 /* PF_BAR0 */ 3361 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL(a) (a) 3362 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_CFG_MON_SEL(a) (a), -1, -1, -1 3363 3364 /** 3365 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_mbwu_l 3366 * 3367 * DSS Ddrctl Regb Chb Mpam S Msmon Mbwu L Register 3368 * MPAM MBWU Long register 3369 */ 3370 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l { 3371 uint32_t u; 3372 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_s { 3373 uint32_t value : 32; 3374 } s; 3375 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_s cn; */ 3376 }; 3377 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_t; 3378 3379 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L(uint64_t a) __attribute__ ((pure, always_inline)); 3380 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L(uint64_t a) 3381 { 3382 if (a <= 19) 3383 return 0x87e1b0250880ll + 0x1000000ll * ((a) & 0x1f); 3384 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L", 1, a, 0, 0, 0, 0, 0); 3385 } 3386 3387 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_t 3388 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L(a) CSR_TYPE_RSL32b 3389 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L" 3390 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L(a) 0x0 /* PF_BAR0 */ 3391 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L(a) (a) 3392 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L(a) (a), -1, -1, -1 3393 3394 /** 3395 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_32 3396 * 3397 * DSS Ddrctl Regb Chb Mpam S Msmon Mbwu L 32 Register 3398 * MPAM MBWU Long MSB 32bits register 3399 */ 3400 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_32 { 3401 uint32_t u; 3402 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_32_s { 3403 uint32_t value : 31; 3404 uint32_t nrdy : 1; 3405 } s; 3406 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_32_s cn; */ 3407 }; 3408 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_32 ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_32_t; 3409 3410 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32(uint64_t a) __attribute__ ((pure, always_inline)); 3411 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32(uint64_t a) 3412 { 3413 if (a <= 19) 3414 return 0x87e1b0250884ll + 0x1000000ll * ((a) & 0x1f); 3415 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32", 1, a, 0, 0, 0, 0, 0); 3416 } 3417 3418 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_32_t 3419 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32(a) CSR_TYPE_RSL32b 3420 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32" 3421 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32(a) 0x0 /* PF_BAR0 */ 3422 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32(a) (a) 3423 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_32(a) (a), -1, -1, -1 3424 3425 /** 3426 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture 3427 * 3428 * DSS Ddrctl Regb Chb Mpam S Msmon Mbwu L Capture Register 3429 * MPAM MBWU Long Capture register 3430 */ 3431 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture { 3432 uint32_t u; 3433 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_s { 3434 uint32_t value : 32; 3435 } s; 3436 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_s cn; */ 3437 }; 3438 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_t; 3439 3440 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE(uint64_t a) __attribute__ ((pure, always_inline)); 3441 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE(uint64_t a) 3442 { 3443 if (a <= 19) 3444 return 0x87e1b0250890ll + 0x1000000ll * ((a) & 0x1f); 3445 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE", 1, a, 0, 0, 0, 0, 0); 3446 } 3447 3448 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_t 3449 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE(a) CSR_TYPE_RSL32b 3450 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE" 3451 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE(a) 0x0 /* PF_BAR0 */ 3452 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE(a) (a) 3453 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE(a) (a), -1, -1, -1 3454 3455 /** 3456 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_32 3457 * 3458 * DSS Ddrctl Regb Chb Mpam S Msmon Mbwu L Capture 32 Register 3459 * MPAM MBWU Long Capture MSB 32bits register 3460 */ 3461 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_32 { 3462 uint32_t u; 3463 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_32_s { 3464 uint32_t value : 31; 3465 uint32_t nrdy : 1; 3466 } s; 3467 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_32_s cn; */ 3468 }; 3469 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_32 ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_32_t; 3470 3471 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32(uint64_t a) __attribute__ ((pure, always_inline)); 3472 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32(uint64_t a) 3473 { 3474 if (a <= 19) 3475 return 0x87e1b0250894ll + 0x1000000ll * ((a) & 0x1f); 3476 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32", 1, a, 0, 0, 0, 0, 0); 3477 } 3478 3479 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_l_capture_32_t 3480 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32(a) CSR_TYPE_RSL32b 3481 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32" 3482 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32(a) 0x0 /* PF_BAR0 */ 3483 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32(a) (a) 3484 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_L_CAPTURE_32(a) (a), -1, -1, -1 3485 3486 /** 3487 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_mbwu_ofsr 3488 * 3489 * DSS Ddrctl Regb Chb Mpam S Msmon Mbwu Ofsr Register 3490 * MPAM MBWU OFSR register 3491 */ 3492 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_ofsr { 3493 uint32_t u; 3494 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_ofsr_s { 3495 uint32_t ofpnd : 32; 3496 } s; 3497 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_ofsr_s cn; */ 3498 }; 3499 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_ofsr ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_ofsr_t; 3500 3501 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR(uint64_t a) __attribute__ ((pure, always_inline)); 3502 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR(uint64_t a) 3503 { 3504 if (a <= 19) 3505 return 0x87e1b0250898ll + 0x1000000ll * ((a) & 0x1f); 3506 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR", 1, a, 0, 0, 0, 0, 0); 3507 } 3508 3509 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_mbwu_ofsr_t 3510 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR(a) CSR_TYPE_RSL32b 3511 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR" 3512 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR(a) 0x0 /* PF_BAR0 */ 3513 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR(a) (a) 3514 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_MBWU_OFSR(a) (a), -1, -1, -1 3515 3516 /** 3517 * Register (RSL32b) dss#_ddrctl_regb_chb_mpam_s_msmon_oflow_sr 3518 * 3519 * DSS Ddrctl Regb Chb Mpam S Msmon Oflow Sr Register 3520 * MPAM MSMON OFLOW SR register 3521 */ 3522 union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_oflow_sr { 3523 uint32_t u; 3524 struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_oflow_sr_s { 3525 uint32_t reserved_0_29 : 30; 3526 uint32_t mbwu_oflow_pnd : 1; 3527 uint32_t reserved_31 : 1; 3528 } s; 3529 /* struct ody_dssx_ddrctl_regb_chb_mpam_s_msmon_oflow_sr_s cn; */ 3530 }; 3531 typedef union ody_dssx_ddrctl_regb_chb_mpam_s_msmon_oflow_sr ody_dssx_ddrctl_regb_chb_mpam_s_msmon_oflow_sr_t; 3532 3533 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR(uint64_t a) __attribute__ ((pure, always_inline)); 3534 static inline uint64_t ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR(uint64_t a) 3535 { 3536 if (a <= 19) 3537 return 0x87e1b02508f0ll + 0x1000000ll * ((a) & 0x1f); 3538 __ody_csr_fatal("DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR", 1, a, 0, 0, 0, 0, 0); 3539 } 3540 3541 #define typedef_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR(a) ody_dssx_ddrctl_regb_chb_mpam_s_msmon_oflow_sr_t 3542 #define bustype_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR(a) CSR_TYPE_RSL32b 3543 #define basename_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR(a) "DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR" 3544 #define device_bar_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR(a) 0x0 /* PF_BAR0 */ 3545 #define busnum_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR(a) (a) 3546 #define arguments_ODY_DSSX_DDRCTL_REGB_CHB_MPAM_S_MSMON_OFLOW_SR(a) (a), -1, -1, -1 3547 3548 /** 3549 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_adveccindex 3550 * 3551 * DSS Ddrctl Regb Ddrc Ch0 Adveccindex Register 3552 * Advanced ECC Index Register 3553 */ 3554 union ody_dssx_ddrctl_regb_ddrc_ch0_adveccindex { 3555 uint32_t u; 3556 struct ody_dssx_ddrctl_regb_ddrc_ch0_adveccindex_s { 3557 uint32_t ecc_syndrome_sel : 3; 3558 uint32_t ecc_err_symbol_sel : 2; 3559 uint32_t ecc_poison_beats_sel : 4; 3560 uint32_t reserved_9_31 : 23; 3561 } s; 3562 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_adveccindex_s cn; */ 3563 }; 3564 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_adveccindex ody_dssx_ddrctl_regb_ddrc_ch0_adveccindex_t; 3565 3566 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX(uint64_t a) __attribute__ ((pure, always_inline)); 3567 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX(uint64_t a) 3568 { 3569 if (a <= 19) 3570 return 0x87e1b0210650ll + 0x1000000ll * ((a) & 0x1f); 3571 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX", 1, a, 0, 0, 0, 0, 0); 3572 } 3573 3574 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX(a) ody_dssx_ddrctl_regb_ddrc_ch0_adveccindex_t 3575 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX(a) CSR_TYPE_RSL32b 3576 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX" 3577 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX(a) 0x0 /* PF_BAR0 */ 3578 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX(a) (a) 3579 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCINDEX(a) (a), -1, -1, -1 3580 3581 /** 3582 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_adveccstat 3583 * 3584 * DSS Ddrctl Regb Ddrc Ch0 Adveccstat Register 3585 * Advanced ECC Status Register 3586 */ 3587 union ody_dssx_ddrctl_regb_ddrc_ch0_adveccstat { 3588 uint32_t u; 3589 struct ody_dssx_ddrctl_regb_ddrc_ch0_adveccstat_s { 3590 uint32_t advecc_corrected_err : 1; 3591 uint32_t advecc_uncorrected_err : 1; 3592 uint32_t advecc_num_err_symbol : 3; 3593 uint32_t advecc_err_symbol_pos : 7; 3594 uint32_t reserved_12_15 : 4; 3595 uint32_t advecc_err_symbol_bits : 8; 3596 uint32_t advecc_ce_kbd_stat : 4; 3597 uint32_t advecc_ue_kbd_stat : 2; 3598 uint32_t sbr_read_advecc_ce : 1; 3599 uint32_t sbr_read_advecc_ue : 1; 3600 } s; 3601 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_adveccstat_s cn; */ 3602 }; 3603 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_adveccstat ody_dssx_ddrctl_regb_ddrc_ch0_adveccstat_t; 3604 3605 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 3606 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT(uint64_t a) 3607 { 3608 if (a <= 19) 3609 return 0x87e1b0210654ll + 0x1000000ll * ((a) & 0x1f); 3610 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT", 1, a, 0, 0, 0, 0, 0); 3611 } 3612 3613 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_adveccstat_t 3614 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT(a) CSR_TYPE_RSL32b 3615 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT" 3616 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT(a) 0x0 /* PF_BAR0 */ 3617 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT(a) (a) 3618 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ADVECCSTAT(a) (a), -1, -1, -1 3619 3620 /** 3621 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_capar_cmdbuf_ctrl 3622 * 3623 * DSS Ddrctl Regb Ddrc Ch0 Capar Cmdbuf Ctrl Register 3624 * CA Parity Retry command buffer control register 3625 */ 3626 union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_ctrl { 3627 uint32_t u; 3628 struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_ctrl_s { 3629 uint32_t capar_cmdbuf_wdata : 16; 3630 uint32_t capar_cmdbuf_addr : 6; 3631 uint32_t reserved_22_28 : 7; 3632 uint32_t capar_cmdbuf_op_mode : 1; 3633 uint32_t capar_cmdbuf_rw_type : 1; 3634 uint32_t capar_cmdbuf_rw_start : 1; 3635 } s; 3636 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_ctrl_s cn; */ 3637 }; 3638 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_ctrl ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_ctrl_t; 3639 3640 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 3641 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL(uint64_t a) 3642 { 3643 if (a <= 19) 3644 return 0x87e1b0210b50ll + 0x1000000ll * ((a) & 0x1f); 3645 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL", 1, a, 0, 0, 0, 0, 0); 3646 } 3647 3648 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL(a) ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_ctrl_t 3649 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL(a) CSR_TYPE_RSL32b 3650 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL" 3651 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL(a) 0x0 /* PF_BAR0 */ 3652 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL(a) (a) 3653 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_CTRL(a) (a), -1, -1, -1 3654 3655 /** 3656 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_capar_cmdbuf_stat 3657 * 3658 * DSS Ddrctl Regb Ddrc Ch0 Capar Cmdbuf Stat Register 3659 * CA Parity Retry command buffer status register. 3660 */ 3661 union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_stat { 3662 uint32_t u; 3663 struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_stat_s { 3664 uint32_t capar_cmdbuf_rdata : 16; 3665 uint32_t reserved_16_31 : 16; 3666 } s; 3667 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_stat_s cn; */ 3668 }; 3669 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_stat ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_stat_t; 3670 3671 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT(uint64_t a) __attribute__ ((pure, always_inline)); 3672 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT(uint64_t a) 3673 { 3674 if (a <= 19) 3675 return 0x87e1b0210b54ll + 0x1000000ll * ((a) & 0x1f); 3676 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT", 1, a, 0, 0, 0, 0, 0); 3677 } 3678 3679 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdbuf_stat_t 3680 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT(a) CSR_TYPE_RSL32b 3681 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT" 3682 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT(a) 0x0 /* PF_BAR0 */ 3683 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT(a) (a) 3684 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDBUF_STAT(a) (a), -1, -1, -1 3685 3686 /** 3687 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_capar_cmdfifo_ctrl 3688 * 3689 * DSS Ddrctl Regb Ddrc Ch0 Capar Cmdfifo Ctrl Register 3690 * PASCAPAR CMDFIFO CTRL Register 3691 */ 3692 union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_ctrl { 3693 uint32_t u; 3694 struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_ctrl_s { 3695 uint32_t reserved_0_15 : 16; 3696 uint32_t cmdfifo_rd_addr : 8; 3697 uint32_t reserved_24_31 : 8; 3698 } s; 3699 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_ctrl_s cn; */ 3700 }; 3701 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_ctrl ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_ctrl_t; 3702 3703 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 3704 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL(uint64_t a) 3705 { 3706 if (a <= 19) 3707 return 0x87e1b0210dc0ll + 0x1000000ll * ((a) & 0x1f); 3708 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL", 1, a, 0, 0, 0, 0, 0); 3709 } 3710 3711 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL(a) ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_ctrl_t 3712 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL(a) CSR_TYPE_RSL32b 3713 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL" 3714 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL(a) 0x0 /* PF_BAR0 */ 3715 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL(a) (a) 3716 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_CTRL(a) (a), -1, -1, -1 3717 3718 /** 3719 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_capar_cmdfifo_log 3720 * 3721 * DSS Ddrctl Regb Ddrc Ch0 Capar Cmdfifo Log Register 3722 * PASCAPAR CMDFIFO LOG Register 3723 */ 3724 union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_log { 3725 uint32_t u; 3726 struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_log_s { 3727 uint32_t cmdfifo_window_cmd_num : 9; 3728 uint32_t reserved_9_15 : 7; 3729 uint32_t cmdfifo_recorded_cmd_num : 9; 3730 uint32_t reserved_25_30 : 6; 3731 uint32_t cmdfifo_overflow : 1; 3732 } s; 3733 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_log_s cn; */ 3734 }; 3735 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_log ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_log_t; 3736 3737 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG(uint64_t a) __attribute__ ((pure, always_inline)); 3738 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG(uint64_t a) 3739 { 3740 if (a <= 19) 3741 return 0x87e1b0210dc8ll + 0x1000000ll * ((a) & 0x1f); 3742 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG", 1, a, 0, 0, 0, 0, 0); 3743 } 3744 3745 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG(a) ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_log_t 3746 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG(a) CSR_TYPE_RSL32b 3747 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG" 3748 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG(a) 0x0 /* PF_BAR0 */ 3749 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG(a) (a) 3750 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_LOG(a) (a), -1, -1, -1 3751 3752 /** 3753 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_capar_cmdfifo_stat 3754 * 3755 * DSS Ddrctl Regb Ddrc Ch0 Capar Cmdfifo Stat Register 3756 * PASCAPAR CMDFIFO STAT Register 3757 */ 3758 union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_stat { 3759 uint32_t u; 3760 struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_stat_s { 3761 uint32_t cmdfifo_rd_data : 13; 3762 uint32_t reserved_13_31 : 19; 3763 } s; 3764 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_stat_s cn; */ 3765 }; 3766 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_stat ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_stat_t; 3767 3768 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT(uint64_t a) __attribute__ ((pure, always_inline)); 3769 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT(uint64_t a) 3770 { 3771 if (a <= 19) 3772 return 0x87e1b0210dc4ll + 0x1000000ll * ((a) & 0x1f); 3773 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT", 1, a, 0, 0, 0, 0, 0); 3774 } 3775 3776 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_capar_cmdfifo_stat_t 3777 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT(a) CSR_TYPE_RSL32b 3778 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT" 3779 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT(a) 0x0 /* PF_BAR0 */ 3780 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT(a) (a) 3781 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_CMDFIFO_STAT(a) (a), -1, -1, -1 3782 3783 /** 3784 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_capar_dbg_stat0 3785 * 3786 * DSS Ddrctl Regb Ddrc Ch0 Capar Dbg Stat0 Register 3787 * PASCAPAR DEBUG STAT0 Register 3788 */ 3789 union ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat0 { 3790 uint32_t u; 3791 struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat0_s { 3792 uint32_t dbg_capar_retry_mc_addr : 6; 3793 uint32_t reserved_6_15 : 10; 3794 uint32_t dbg_capar_retry_mc_code : 16; 3795 } s; 3796 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat0_s cn; */ 3797 }; 3798 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat0 ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat0_t; 3799 3800 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0(uint64_t a) __attribute__ ((pure, always_inline)); 3801 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0(uint64_t a) 3802 { 3803 if (a <= 19) 3804 return 0x87e1b0210db8ll + 0x1000000ll * ((a) & 0x1f); 3805 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0", 1, a, 0, 0, 0, 0, 0); 3806 } 3807 3808 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat0_t 3809 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0(a) CSR_TYPE_RSL32b 3810 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0" 3811 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0(a) 0x0 /* PF_BAR0 */ 3812 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0(a) (a) 3813 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT0(a) (a), -1, -1, -1 3814 3815 /** 3816 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_capar_dbg_stat1 3817 * 3818 * DSS Ddrctl Regb Ddrc Ch0 Capar Dbg Stat1 Register 3819 * PASCAPAR DEBUG STAT1 Register 3820 */ 3821 union ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat1 { 3822 uint32_t u; 3823 struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat1_s { 3824 uint32_t dbg_capar_retry_state_sceu : 3; 3825 uint32_t reserved_3 : 1; 3826 uint32_t dbg_capar_retry_state_mceu : 3; 3827 uint32_t reserved_7 : 1; 3828 uint32_t dbg_capar_retry_state_csm : 2; 3829 uint32_t reserved_10_31 : 22; 3830 } s; 3831 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat1_s cn; */ 3832 }; 3833 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat1 ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat1_t; 3834 3835 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1(uint64_t a) __attribute__ ((pure, always_inline)); 3836 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1(uint64_t a) 3837 { 3838 if (a <= 19) 3839 return 0x87e1b0210dbcll + 0x1000000ll * ((a) & 0x1f); 3840 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1", 1, a, 0, 0, 0, 0, 0); 3841 } 3842 3843 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1(a) ody_dssx_ddrctl_regb_ddrc_ch0_capar_dbg_stat1_t 3844 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1(a) CSR_TYPE_RSL32b 3845 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1" 3846 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1(a) 0x0 /* PF_BAR0 */ 3847 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1(a) (a) 3848 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPAR_DBG_STAT1(a) (a), -1, -1, -1 3849 3850 /** 3851 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_caparpoisonctl 3852 * 3853 * DSS Ddrctl Regb Ddrc Ch0 Caparpoisonctl Register 3854 * CA parity poison control Register 3855 */ 3856 union ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonctl { 3857 uint32_t u; 3858 struct ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonctl_s { 3859 uint32_t capar_poison_inject_en : 1; 3860 uint32_t reserved_1_7 : 7; 3861 uint32_t capar_poison_cmdtype : 2; 3862 uint32_t reserved_10_11 : 2; 3863 uint32_t capar_poison_position : 8; 3864 uint32_t reserved_20_31 : 12; 3865 } s; 3866 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonctl_s cn; */ 3867 }; 3868 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonctl ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonctl_t; 3869 3870 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL(uint64_t a) __attribute__ ((pure, always_inline)); 3871 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL(uint64_t a) 3872 { 3873 if (a <= 19) 3874 return 0x87e1b0210810ll + 0x1000000ll * ((a) & 0x1f); 3875 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL", 1, a, 0, 0, 0, 0, 0); 3876 } 3877 3878 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonctl_t 3879 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL(a) CSR_TYPE_RSL32b 3880 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL" 3881 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL(a) 0x0 /* PF_BAR0 */ 3882 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL(a) (a) 3883 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONCTL(a) (a), -1, -1, -1 3884 3885 /** 3886 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_caparpoisonstat 3887 * 3888 * DSS Ddrctl Regb Ddrc Ch0 Caparpoisonstat Register 3889 * CA parity poison status Register 3890 */ 3891 union ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonstat { 3892 uint32_t u; 3893 struct ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonstat_s { 3894 uint32_t capar_poison_complete : 1; 3895 uint32_t reserved_1_31 : 31; 3896 } s; 3897 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonstat_s cn; */ 3898 }; 3899 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonstat ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonstat_t; 3900 3901 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 3902 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT(uint64_t a) 3903 { 3904 if (a <= 19) 3905 return 0x87e1b0210814ll + 0x1000000ll * ((a) & 0x1f); 3906 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT", 1, a, 0, 0, 0, 0, 0); 3907 } 3908 3909 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_caparpoisonstat_t 3910 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT(a) CSR_TYPE_RSL32b 3911 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT" 3912 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT(a) 0x0 /* PF_BAR0 */ 3913 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT(a) (a) 3914 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CAPARPOISONSTAT(a) (a), -1, -1, -1 3915 3916 /** 3917 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_chctl 3918 * 3919 * DSS Ddrctl Regb Ddrc Ch0 Chctl Register 3920 * Channel Control Register 3921 */ 3922 union ody_dssx_ddrctl_regb_ddrc_ch0_chctl { 3923 uint32_t u; 3924 struct ody_dssx_ddrctl_regb_ddrc_ch0_chctl_s { 3925 uint32_t dual_channel_en : 1; 3926 uint32_t reserved_1_31 : 31; 3927 } s; 3928 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_chctl_s cn; */ 3929 }; 3930 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_chctl ody_dssx_ddrctl_regb_ddrc_ch0_chctl_t; 3931 3932 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL(uint64_t a) __attribute__ ((pure, always_inline)); 3933 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL(uint64_t a) 3934 { 3935 if (a <= 19) 3936 return 0x87e1b0210c8cll + 0x1000000ll * ((a) & 0x1f); 3937 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL", 1, a, 0, 0, 0, 0, 0); 3938 } 3939 3940 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_chctl_t 3941 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL(a) CSR_TYPE_RSL32b 3942 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL" 3943 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL(a) 0x0 /* PF_BAR0 */ 3944 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL(a) (a) 3945 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CHCTL(a) (a), -1, -1, -1 3946 3947 /** 3948 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_cmdcfg 3949 * 3950 * DSS Ddrctl Regb Ddrc Ch0 Cmdcfg Register 3951 * Software DDR command configuration register 3952 */ 3953 union ody_dssx_ddrctl_regb_ddrc_ch0_cmdcfg { 3954 uint32_t u; 3955 struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdcfg_s { 3956 uint32_t cmd_type : 1; 3957 uint32_t multi_cyc_cs_en : 1; 3958 uint32_t pde_odt_ctrl : 1; 3959 uint32_t pd_mrr_nt_odt_en : 1; 3960 uint32_t cmd_timer_x32 : 12; 3961 uint32_t mrr_grp_sel : 3; 3962 uint32_t reserved_19_20 : 2; 3963 uint32_t ctrlupd_retry_thr : 4; 3964 uint32_t reserved_25_31 : 7; 3965 } s; 3966 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdcfg_s cn; */ 3967 }; 3968 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_cmdcfg ody_dssx_ddrctl_regb_ddrc_ch0_cmdcfg_t; 3969 3970 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG(uint64_t a) __attribute__ ((pure, always_inline)); 3971 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG(uint64_t a) 3972 { 3973 if (a <= 19) 3974 return 0x87e1b0210b00ll + 0x1000000ll * ((a) & 0x1f); 3975 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG", 1, a, 0, 0, 0, 0, 0); 3976 } 3977 3978 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG(a) ody_dssx_ddrctl_regb_ddrc_ch0_cmdcfg_t 3979 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG(a) CSR_TYPE_RSL32b 3980 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG" 3981 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG(a) 0x0 /* PF_BAR0 */ 3982 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG(a) (a) 3983 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCFG(a) (a), -1, -1, -1 3984 3985 /** 3986 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_cmdctl 3987 * 3988 * DSS Ddrctl Regb Ddrc Ch0 Cmdctl Register 3989 * Software DDR command control register 3990 */ 3991 union ody_dssx_ddrctl_regb_ddrc_ch0_cmdctl { 3992 uint32_t u; 3993 struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdctl_s { 3994 uint32_t cmd_ctrl : 24; 3995 uint32_t cmd_code : 5; 3996 uint32_t cmd_seq_ongoing : 1; 3997 uint32_t cmd_seq_last : 1; 3998 uint32_t cmd_start : 1; 3999 } s; 4000 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdctl_s cn; */ 4001 }; 4002 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_cmdctl ody_dssx_ddrctl_regb_ddrc_ch0_cmdctl_t; 4003 4004 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL(uint64_t a) __attribute__ ((pure, always_inline)); 4005 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL(uint64_t a) 4006 { 4007 if (a <= 19) 4008 return 0x87e1b0210b04ll + 0x1000000ll * ((a) & 0x1f); 4009 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL", 1, a, 0, 0, 0, 0, 0); 4010 } 4011 4012 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_cmdctl_t 4013 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL(a) CSR_TYPE_RSL32b 4014 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL" 4015 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL(a) 0x0 /* PF_BAR0 */ 4016 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL(a) (a) 4017 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDCTL(a) (a), -1, -1, -1 4018 4019 /** 4020 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_cmdextctl 4021 * 4022 * DSS Ddrctl Regb Ddrc Ch0 Cmdextctl Register 4023 * Software DDR command extended control register 4024 */ 4025 union ody_dssx_ddrctl_regb_ddrc_ch0_cmdextctl { 4026 uint32_t u; 4027 struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdextctl_s { 4028 uint32_t cmd_ext_ctrl : 32; 4029 } s; 4030 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdextctl_s cn; */ 4031 }; 4032 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_cmdextctl ody_dssx_ddrctl_regb_ddrc_ch0_cmdextctl_t; 4033 4034 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL(uint64_t a) __attribute__ ((pure, always_inline)); 4035 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL(uint64_t a) 4036 { 4037 if (a <= 19) 4038 return 0x87e1b0210b08ll + 0x1000000ll * ((a) & 0x1f); 4039 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL", 1, a, 0, 0, 0, 0, 0); 4040 } 4041 4042 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_cmdextctl_t 4043 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL(a) CSR_TYPE_RSL32b 4044 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL" 4045 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL(a) 0x0 /* PF_BAR0 */ 4046 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL(a) (a) 4047 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDEXTCTL(a) (a), -1, -1, -1 4048 4049 /** 4050 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_cmdmrrdata 4051 * 4052 * DSS Ddrctl Regb Ddrc Ch0 Cmdmrrdata Register 4053 * Software DDR command MRR Data register 4054 */ 4055 union ody_dssx_ddrctl_regb_ddrc_ch0_cmdmrrdata { 4056 uint32_t u; 4057 struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdmrrdata_s { 4058 uint32_t cmd_mrr_data : 32; 4059 } s; 4060 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdmrrdata_s cn; */ 4061 }; 4062 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_cmdmrrdata ody_dssx_ddrctl_regb_ddrc_ch0_cmdmrrdata_t; 4063 4064 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA(uint64_t a) __attribute__ ((pure, always_inline)); 4065 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA(uint64_t a) 4066 { 4067 if (a <= 19) 4068 return 0x87e1b0210b14ll + 0x1000000ll * ((a) & 0x1f); 4069 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA", 1, a, 0, 0, 0, 0, 0); 4070 } 4071 4072 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA(a) ody_dssx_ddrctl_regb_ddrc_ch0_cmdmrrdata_t 4073 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA(a) CSR_TYPE_RSL32b 4074 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA" 4075 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA(a) 0x0 /* PF_BAR0 */ 4076 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA(a) (a) 4077 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDMRRDATA(a) (a), -1, -1, -1 4078 4079 /** 4080 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_cmdstat 4081 * 4082 * DSS Ddrctl Regb Ddrc Ch0 Cmdstat Register 4083 * Software DDR command status register 4084 */ 4085 union ody_dssx_ddrctl_regb_ddrc_ch0_cmdstat { 4086 uint32_t u; 4087 struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdstat_s { 4088 uint32_t mrr_data_vld : 1; 4089 uint32_t rd_data_vld : 1; 4090 uint32_t ddr5_2n_mode : 1; 4091 uint32_t reserved_3_7 : 5; 4092 uint32_t swcmd_lock : 1; 4093 uint32_t ducmd_lock : 1; 4094 uint32_t lccmd_lock : 1; 4095 uint32_t reserved_11 : 1; 4096 uint32_t cmd_rslt : 18; 4097 uint32_t cmd_err : 1; 4098 uint32_t cmd_done : 1; 4099 } s; 4100 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_cmdstat_s cn; */ 4101 }; 4102 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_cmdstat ody_dssx_ddrctl_regb_ddrc_ch0_cmdstat_t; 4103 4104 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 4105 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT(uint64_t a) 4106 { 4107 if (a <= 19) 4108 return 0x87e1b0210b0cll + 0x1000000ll * ((a) & 0x1f); 4109 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT", 1, a, 0, 0, 0, 0, 0); 4110 } 4111 4112 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_cmdstat_t 4113 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT(a) CSR_TYPE_RSL32b 4114 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT" 4115 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT(a) 0x0 /* PF_BAR0 */ 4116 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT(a) (a) 4117 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CMDSTAT(a) (a), -1, -1, -1 4118 4119 /** 4120 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcparctl0 4121 * 4122 * DSS Ddrctl Regb Ddrc Ch0 Crcparctl0 Register 4123 * CRC Parity Control Register0 4124 */ 4125 union ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl0 { 4126 uint32_t u; 4127 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl0_s { 4128 uint32_t capar_err_intr_en : 1; 4129 uint32_t capar_err_intr_clr : 1; 4130 uint32_t capar_err_intr_force : 1; 4131 uint32_t reserved_3 : 1; 4132 uint32_t capar_err_max_reached_intr_en : 1; 4133 uint32_t capar_err_max_reached_intr_clr : 1; 4134 uint32_t capar_err_max_reached_intr_force : 1; 4135 uint32_t capar_err_cnt_clr : 1; 4136 uint32_t wr_crc_err_intr_en : 1; 4137 uint32_t wr_crc_err_intr_clr : 1; 4138 uint32_t wr_crc_err_intr_force : 1; 4139 uint32_t reserved_11 : 1; 4140 uint32_t wr_crc_err_max_reached_intr_en : 1; 4141 uint32_t wr_crc_err_max_reached_intr_clr : 1; 4142 uint32_t wr_crc_err_max_reached_intr_force : 1; 4143 uint32_t wr_crc_err_cnt_clr : 1; 4144 uint32_t reserved_16_19 : 4; 4145 uint32_t rd_crc_err_max_reached_int_en : 1; 4146 uint32_t rd_crc_err_max_reached_int_clr : 1; 4147 uint32_t rd_crc_err_cnt_clr : 1; 4148 uint32_t rd_crc_err_max_reached_intr_force : 1; 4149 uint32_t capar_fatl_err_intr_en : 1; 4150 uint32_t capar_fatl_err_intr_clr : 1; 4151 uint32_t capar_fatl_err_intr_force : 1; 4152 uint32_t reserved_27_31 : 5; 4153 } s; 4154 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl0_s cn; */ 4155 }; 4156 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl0 ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl0_t; 4157 4158 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0(uint64_t a) __attribute__ ((pure, always_inline)); 4159 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0(uint64_t a) 4160 { 4161 if (a <= 19) 4162 return 0x87e1b0210800ll + 0x1000000ll * ((a) & 0x1f); 4163 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0", 1, a, 0, 0, 0, 0, 0); 4164 } 4165 4166 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl0_t 4167 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0(a) CSR_TYPE_RSL32b 4168 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0" 4169 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0(a) 0x0 /* PF_BAR0 */ 4170 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0(a) (a) 4171 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL0(a) (a), -1, -1, -1 4172 4173 /** 4174 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcparctl1 4175 * 4176 * DSS Ddrctl Regb Ddrc Ch0 Crcparctl1 Register 4177 * CRC Parity Control Register 1 4178 */ 4179 union ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl1 { 4180 uint32_t u; 4181 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl1_s { 4182 uint32_t parity_enable : 1; 4183 uint32_t bypass_internal_crc : 1; 4184 uint32_t reserved_2 : 1; 4185 uint32_t rd_crc_enable : 1; 4186 uint32_t wr_crc_enable : 1; 4187 uint32_t reserved_5 : 1; 4188 uint32_t dis_rd_crc_ecc_upr_nibble : 1; 4189 uint32_t crc_inc_dm : 1; 4190 uint32_t reserved_8_14 : 7; 4191 uint32_t dfi_alert_async_mode : 1; 4192 uint32_t capar_err_max_reached_th : 12; 4193 uint32_t reserved_28_31 : 4; 4194 } s; 4195 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl1_s cn; */ 4196 }; 4197 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl1 ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl1_t; 4198 4199 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1(uint64_t a) __attribute__ ((pure, always_inline)); 4200 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1(uint64_t a) 4201 { 4202 if (a <= 19) 4203 return 0x87e1b0210804ll + 0x1000000ll * ((a) & 0x1f); 4204 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1", 1, a, 0, 0, 0, 0, 0); 4205 } 4206 4207 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl1_t 4208 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1(a) CSR_TYPE_RSL32b 4209 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1" 4210 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1(a) 0x0 /* PF_BAR0 */ 4211 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1(a) (a) 4212 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL1(a) (a), -1, -1, -1 4213 4214 /** 4215 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcparctl2 4216 * 4217 * DSS Ddrctl Regb Ddrc Ch0 Crcparctl2 Register 4218 * CRC Parity Control Register 2 4219 */ 4220 union ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl2 { 4221 uint32_t u; 4222 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl2_s { 4223 uint32_t wr_crc_err_max_reached_th : 12; 4224 uint32_t reserved_12_15 : 4; 4225 uint32_t rd_crc_err_max_reached_th : 12; 4226 uint32_t reserved_28_31 : 4; 4227 } s; 4228 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl2_s cn; */ 4229 }; 4230 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl2 ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl2_t; 4231 4232 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2(uint64_t a) __attribute__ ((pure, always_inline)); 4233 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2(uint64_t a) 4234 { 4235 if (a <= 19) 4236 return 0x87e1b0210808ll + 0x1000000ll * ((a) & 0x1f); 4237 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2", 1, a, 0, 0, 0, 0, 0); 4238 } 4239 4240 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcparctl2_t 4241 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2(a) CSR_TYPE_RSL32b 4242 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2" 4243 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2(a) 0x0 /* PF_BAR0 */ 4244 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2(a) (a) 4245 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARCTL2(a) (a), -1, -1, -1 4246 4247 /** 4248 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcparstat 4249 * 4250 * DSS Ddrctl Regb Ddrc Ch0 Crcparstat Register 4251 * CRC Parity Status Register 4252 */ 4253 union ody_dssx_ddrctl_regb_ddrc_ch0_crcparstat { 4254 uint32_t u; 4255 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcparstat_s { 4256 uint32_t reserved_0_15 : 16; 4257 uint32_t capar_err_intr : 1; 4258 uint32_t capar_err_max_reached_intr : 1; 4259 uint32_t capar_fatl_err_intr : 1; 4260 uint32_t reserved_19_23 : 5; 4261 uint32_t wr_crc_err_intr : 1; 4262 uint32_t wr_crc_err_max_reached_intr : 1; 4263 uint32_t wr_crc_retry_limit_intr : 1; 4264 uint32_t rd_retry_limit_intr : 1; 4265 uint32_t capar_retry_limit_reached_intr : 1; 4266 uint32_t reserved_29_31 : 3; 4267 } s; 4268 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcparstat_s cn; */ 4269 }; 4270 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcparstat ody_dssx_ddrctl_regb_ddrc_ch0_crcparstat_t; 4271 4272 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 4273 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT(uint64_t a) 4274 { 4275 if (a <= 19) 4276 return 0x87e1b021080cll + 0x1000000ll * ((a) & 0x1f); 4277 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT", 1, a, 0, 0, 0, 0, 0); 4278 } 4279 4280 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcparstat_t 4281 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT(a) CSR_TYPE_RSL32b 4282 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT" 4283 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT(a) 0x0 /* PF_BAR0 */ 4284 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT(a) (a) 4285 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPARSTAT(a) (a), -1, -1, -1 4286 4287 /** 4288 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcpoisonctl0 4289 * 4290 * DSS Ddrctl Regb Ddrc Ch0 Crcpoisonctl0 Register 4291 * CRC poison control register 4292 */ 4293 union ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonctl0 { 4294 uint32_t u; 4295 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonctl0_s { 4296 uint32_t crc_poison_inject_en : 1; 4297 uint32_t crc_poison_type : 1; 4298 uint32_t reserved_2_7 : 6; 4299 uint32_t crc_poison_nibble : 5; 4300 uint32_t reserved_13_15 : 3; 4301 uint32_t crc_poison_times : 5; 4302 uint32_t reserved_21_31 : 11; 4303 } s; 4304 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonctl0_s cn; */ 4305 }; 4306 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonctl0 ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonctl0_t; 4307 4308 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0(uint64_t a) __attribute__ ((pure, always_inline)); 4309 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0(uint64_t a) 4310 { 4311 if (a <= 19) 4312 return 0x87e1b0210820ll + 0x1000000ll * ((a) & 0x1f); 4313 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0", 1, a, 0, 0, 0, 0, 0); 4314 } 4315 4316 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonctl0_t 4317 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0(a) CSR_TYPE_RSL32b 4318 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0" 4319 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0(a) 0x0 /* PF_BAR0 */ 4320 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0(a) (a) 4321 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONCTL0(a) (a), -1, -1, -1 4322 4323 /** 4324 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcpoisonstat 4325 * 4326 * DSS Ddrctl Regb Ddrc Ch0 Crcpoisonstat Register 4327 * CRC poison status register 4328 */ 4329 union ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonstat { 4330 uint32_t u; 4331 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonstat_s { 4332 uint32_t crc_poison_complete : 1; 4333 uint32_t reserved_1_31 : 31; 4334 } s; 4335 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonstat_s cn; */ 4336 }; 4337 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonstat ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonstat_t; 4338 4339 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 4340 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT(uint64_t a) 4341 { 4342 if (a <= 19) 4343 return 0x87e1b021082cll + 0x1000000ll * ((a) & 0x1f); 4344 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT", 1, a, 0, 0, 0, 0, 0); 4345 } 4346 4347 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcpoisonstat_t 4348 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT(a) CSR_TYPE_RSL32b 4349 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT" 4350 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT(a) 0x0 /* PF_BAR0 */ 4351 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT(a) (a) 4352 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCPOISONSTAT(a) (a), -1, -1, -1 4353 4354 /** 4355 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcstat0 4356 * 4357 * DSS Ddrctl Regb Ddrc Ch0 Crcstat0 Register 4358 * CRC Error Status Register Nibbles 0 and 1 4359 */ 4360 union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat0 { 4361 uint32_t u; 4362 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat0_s { 4363 uint32_t rd_crc_err_cnt_nibble_0 : 12; 4364 uint32_t reserved_12_15 : 4; 4365 uint32_t rd_crc_err_cnt_nibble_1 : 12; 4366 uint32_t reserved_28_31 : 4; 4367 } s; 4368 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat0_s cn; */ 4369 }; 4370 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat0 ody_dssx_ddrctl_regb_ddrc_ch0_crcstat0_t; 4371 4372 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0(uint64_t a) __attribute__ ((pure, always_inline)); 4373 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0(uint64_t a) 4374 { 4375 if (a <= 19) 4376 return 0x87e1b0210848ll + 0x1000000ll * ((a) & 0x1f); 4377 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0", 1, a, 0, 0, 0, 0, 0); 4378 } 4379 4380 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcstat0_t 4381 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0(a) CSR_TYPE_RSL32b 4382 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0" 4383 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0(a) 0x0 /* PF_BAR0 */ 4384 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0(a) (a) 4385 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT0(a) (a), -1, -1, -1 4386 4387 /** 4388 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcstat1 4389 * 4390 * DSS Ddrctl Regb Ddrc Ch0 Crcstat1 Register 4391 * CRC Error Status Register Nibbles 2 and 3 4392 */ 4393 union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat1 { 4394 uint32_t u; 4395 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat1_s { 4396 uint32_t rd_crc_err_cnt_nibble_2 : 12; 4397 uint32_t reserved_12_15 : 4; 4398 uint32_t rd_crc_err_cnt_nibble_3 : 12; 4399 uint32_t reserved_28_31 : 4; 4400 } s; 4401 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat1_s cn; */ 4402 }; 4403 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat1 ody_dssx_ddrctl_regb_ddrc_ch0_crcstat1_t; 4404 4405 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1(uint64_t a) __attribute__ ((pure, always_inline)); 4406 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1(uint64_t a) 4407 { 4408 if (a <= 19) 4409 return 0x87e1b021084cll + 0x1000000ll * ((a) & 0x1f); 4410 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1", 1, a, 0, 0, 0, 0, 0); 4411 } 4412 4413 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcstat1_t 4414 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1(a) CSR_TYPE_RSL32b 4415 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1" 4416 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1(a) 0x0 /* PF_BAR0 */ 4417 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1(a) (a) 4418 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT1(a) (a), -1, -1, -1 4419 4420 /** 4421 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcstat10 4422 * 4423 * DSS Ddrctl Regb Ddrc Ch0 Crcstat10 Register 4424 * CRC Error Status 10th Registser 4425 */ 4426 union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat10 { 4427 uint32_t u; 4428 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat10_s { 4429 uint32_t wr_crc_err_cnt : 12; 4430 uint32_t capar_err_cnt : 12; 4431 uint32_t reserved_24_31 : 8; 4432 } s; 4433 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat10_s cn; */ 4434 }; 4435 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat10 ody_dssx_ddrctl_regb_ddrc_ch0_crcstat10_t; 4436 4437 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10(uint64_t a) __attribute__ ((pure, always_inline)); 4438 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10(uint64_t a) 4439 { 4440 if (a <= 19) 4441 return 0x87e1b0210870ll + 0x1000000ll * ((a) & 0x1f); 4442 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10", 1, a, 0, 0, 0, 0, 0); 4443 } 4444 4445 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcstat10_t 4446 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10(a) CSR_TYPE_RSL32b 4447 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10" 4448 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10(a) 0x0 /* PF_BAR0 */ 4449 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10(a) (a) 4450 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT10(a) (a), -1, -1, -1 4451 4452 /** 4453 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcstat2 4454 * 4455 * DSS Ddrctl Regb Ddrc Ch0 Crcstat2 Register 4456 * CRC Error Status Register Nibbles 4 and 5 4457 */ 4458 union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat2 { 4459 uint32_t u; 4460 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat2_s { 4461 uint32_t rd_crc_err_cnt_nibble_4 : 12; 4462 uint32_t reserved_12_15 : 4; 4463 uint32_t rd_crc_err_cnt_nibble_5 : 12; 4464 uint32_t reserved_28_31 : 4; 4465 } s; 4466 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat2_s cn; */ 4467 }; 4468 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat2 ody_dssx_ddrctl_regb_ddrc_ch0_crcstat2_t; 4469 4470 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2(uint64_t a) __attribute__ ((pure, always_inline)); 4471 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2(uint64_t a) 4472 { 4473 if (a <= 19) 4474 return 0x87e1b0210850ll + 0x1000000ll * ((a) & 0x1f); 4475 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2", 1, a, 0, 0, 0, 0, 0); 4476 } 4477 4478 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcstat2_t 4479 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2(a) CSR_TYPE_RSL32b 4480 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2" 4481 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2(a) 0x0 /* PF_BAR0 */ 4482 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2(a) (a) 4483 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT2(a) (a), -1, -1, -1 4484 4485 /** 4486 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcstat3 4487 * 4488 * DSS Ddrctl Regb Ddrc Ch0 Crcstat3 Register 4489 * CRC Error Status Register Nibbles 6 and 7 4490 */ 4491 union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat3 { 4492 uint32_t u; 4493 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat3_s { 4494 uint32_t rd_crc_err_cnt_nibble_6 : 12; 4495 uint32_t reserved_12_15 : 4; 4496 uint32_t rd_crc_err_cnt_nibble_7 : 12; 4497 uint32_t reserved_28_31 : 4; 4498 } s; 4499 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat3_s cn; */ 4500 }; 4501 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat3 ody_dssx_ddrctl_regb_ddrc_ch0_crcstat3_t; 4502 4503 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3(uint64_t a) __attribute__ ((pure, always_inline)); 4504 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3(uint64_t a) 4505 { 4506 if (a <= 19) 4507 return 0x87e1b0210854ll + 0x1000000ll * ((a) & 0x1f); 4508 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3", 1, a, 0, 0, 0, 0, 0); 4509 } 4510 4511 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcstat3_t 4512 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3(a) CSR_TYPE_RSL32b 4513 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3" 4514 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3(a) 0x0 /* PF_BAR0 */ 4515 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3(a) (a) 4516 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT3(a) (a), -1, -1, -1 4517 4518 /** 4519 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_crcstat4 4520 * 4521 * DSS Ddrctl Regb Ddrc Ch0 Crcstat4 Register 4522 * CRC Error Status Register Nibbles 8 and 9 4523 */ 4524 union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat4 { 4525 uint32_t u; 4526 struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat4_s { 4527 uint32_t rd_crc_err_cnt_nibble_8 : 12; 4528 uint32_t reserved_12_15 : 4; 4529 uint32_t rd_crc_err_cnt_nibble_9 : 12; 4530 uint32_t reserved_28_31 : 4; 4531 } s; 4532 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_crcstat4_s cn; */ 4533 }; 4534 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_crcstat4 ody_dssx_ddrctl_regb_ddrc_ch0_crcstat4_t; 4535 4536 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4(uint64_t a) __attribute__ ((pure, always_inline)); 4537 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4(uint64_t a) 4538 { 4539 if (a <= 19) 4540 return 0x87e1b0210858ll + 0x1000000ll * ((a) & 0x1f); 4541 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4", 1, a, 0, 0, 0, 0, 0); 4542 } 4543 4544 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4(a) ody_dssx_ddrctl_regb_ddrc_ch0_crcstat4_t 4545 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4(a) CSR_TYPE_RSL32b 4546 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4(a) "DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4" 4547 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4(a) 0x0 /* PF_BAR0 */ 4548 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4(a) (a) 4549 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_CRCSTAT4(a) (a), -1, -1, -1 4550 4551 /** 4552 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_dbictl 4553 * 4554 * DSS Ddrctl Regb Ddrc Ch0 Dbictl Register 4555 * DM/DBI Control Register 4556 */ 4557 union ody_dssx_ddrctl_regb_ddrc_ch0_dbictl { 4558 uint32_t u; 4559 struct ody_dssx_ddrctl_regb_ddrc_ch0_dbictl_s { 4560 uint32_t dm_en : 1; 4561 uint32_t reserved_1_31 : 31; 4562 } s; 4563 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_dbictl_s cn; */ 4564 }; 4565 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_dbictl ody_dssx_ddrctl_regb_ddrc_ch0_dbictl_t; 4566 4567 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL(uint64_t a) __attribute__ ((pure, always_inline)); 4568 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL(uint64_t a) 4569 { 4570 if (a <= 19) 4571 return 0x87e1b0210c94ll + 0x1000000ll * ((a) & 0x1f); 4572 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL", 1, a, 0, 0, 0, 0, 0); 4573 } 4574 4575 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_dbictl_t 4576 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL(a) CSR_TYPE_RSL32b 4577 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL" 4578 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL(a) 0x0 /* PF_BAR0 */ 4579 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL(a) (a) 4580 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DBICTL(a) (a), -1, -1, -1 4581 4582 /** 4583 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ddrctl_ver_number 4584 * 4585 * DSS Ddrctl Regb Ddrc Ch0 Ddrctl Ver Number Register 4586 * DDRCTL Version Number Register 4587 */ 4588 union ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_number { 4589 uint32_t u; 4590 struct ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_number_s { 4591 uint32_t ver_number : 32; 4592 } s; 4593 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_number_s cn; */ 4594 }; 4595 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_number ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_number_t; 4596 4597 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER(uint64_t a) __attribute__ ((pure, always_inline)); 4598 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER(uint64_t a) 4599 { 4600 if (a <= 19) 4601 return 0x87e1b0210ff8ll + 0x1000000ll * ((a) & 0x1f); 4602 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER", 1, a, 0, 0, 0, 0, 0); 4603 } 4604 4605 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER(a) ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_number_t 4606 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER(a) CSR_TYPE_RSL32b 4607 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER" 4608 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER(a) 0x0 /* PF_BAR0 */ 4609 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER(a) (a) 4610 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_NUMBER(a) (a), -1, -1, -1 4611 4612 /** 4613 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ddrctl_ver_type 4614 * 4615 * DSS Ddrctl Regb Ddrc Ch0 Ddrctl Ver Type Register 4616 * DDRCTL Version Type Register 4617 */ 4618 union ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_type { 4619 uint32_t u; 4620 struct ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_type_s { 4621 uint32_t ver_type : 32; 4622 } s; 4623 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_type_s cn; */ 4624 }; 4625 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_type ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_type_t; 4626 4627 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE(uint64_t a) __attribute__ ((pure, always_inline)); 4628 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE(uint64_t a) 4629 { 4630 if (a <= 19) 4631 return 0x87e1b0210ffcll + 0x1000000ll * ((a) & 0x1f); 4632 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE", 1, a, 0, 0, 0, 0, 0); 4633 } 4634 4635 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE(a) ody_dssx_ddrctl_regb_ddrc_ch0_ddrctl_ver_type_t 4636 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE(a) CSR_TYPE_RSL32b 4637 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE" 4638 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE(a) 0x0 /* PF_BAR0 */ 4639 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE(a) (a) 4640 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DDRCTL_VER_TYPE(a) (a), -1, -1, -1 4641 4642 /** 4643 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_deratectl1 4644 * 4645 * DSS Ddrctl Regb Ddrc Ch0 Deratectl1 Register 4646 * Temperature Derate Control Register 1 4647 */ 4648 union ody_dssx_ddrctl_regb_ddrc_ch0_deratectl1 { 4649 uint32_t u; 4650 struct ody_dssx_ddrctl_regb_ddrc_ch0_deratectl1_s { 4651 uint32_t active_derate_byte_rank0 : 10; 4652 uint32_t reserved_10_31 : 22; 4653 } s; 4654 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_deratectl1_s cn; */ 4655 }; 4656 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_deratectl1 ody_dssx_ddrctl_regb_ddrc_ch0_deratectl1_t; 4657 4658 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1(uint64_t a) __attribute__ ((pure, always_inline)); 4659 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1(uint64_t a) 4660 { 4661 if (a <= 19) 4662 return 0x87e1b0210104ll + 0x1000000ll * ((a) & 0x1f); 4663 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1", 1, a, 0, 0, 0, 0, 0); 4664 } 4665 4666 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1(a) ody_dssx_ddrctl_regb_ddrc_ch0_deratectl1_t 4667 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1(a) CSR_TYPE_RSL32b 4668 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1" 4669 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1(a) 0x0 /* PF_BAR0 */ 4670 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1(a) (a) 4671 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL1(a) (a), -1, -1, -1 4672 4673 /** 4674 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_deratectl2 4675 * 4676 * DSS Ddrctl Regb Ddrc Ch0 Deratectl2 Register 4677 * Temperature Derate Control Register 2 4678 */ 4679 union ody_dssx_ddrctl_regb_ddrc_ch0_deratectl2 { 4680 uint32_t u; 4681 struct ody_dssx_ddrctl_regb_ddrc_ch0_deratectl2_s { 4682 uint32_t active_derate_byte_rank1 : 10; 4683 uint32_t reserved_10_31 : 22; 4684 } s; 4685 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_deratectl2_s cn; */ 4686 }; 4687 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_deratectl2 ody_dssx_ddrctl_regb_ddrc_ch0_deratectl2_t; 4688 4689 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2(uint64_t a) __attribute__ ((pure, always_inline)); 4690 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2(uint64_t a) 4691 { 4692 if (a <= 19) 4693 return 0x87e1b0210108ll + 0x1000000ll * ((a) & 0x1f); 4694 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2", 1, a, 0, 0, 0, 0, 0); 4695 } 4696 4697 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2(a) ody_dssx_ddrctl_regb_ddrc_ch0_deratectl2_t 4698 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2(a) CSR_TYPE_RSL32b 4699 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2" 4700 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2(a) 0x0 /* PF_BAR0 */ 4701 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2(a) (a) 4702 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL2(a) (a), -1, -1, -1 4703 4704 /** 4705 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_deratectl5 4706 * 4707 * DSS Ddrctl Regb Ddrc Ch0 Deratectl5 Register 4708 * Temperature Derate Control Register 5 4709 */ 4710 union ody_dssx_ddrctl_regb_ddrc_ch0_deratectl5 { 4711 uint32_t u; 4712 struct ody_dssx_ddrctl_regb_ddrc_ch0_deratectl5_s { 4713 uint32_t derate_temp_limit_intr_en : 1; 4714 uint32_t derate_temp_limit_intr_clr : 1; 4715 uint32_t derate_temp_limit_intr_force : 1; 4716 uint32_t reserved_3_31 : 29; 4717 } s; 4718 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_deratectl5_s cn; */ 4719 }; 4720 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_deratectl5 ody_dssx_ddrctl_regb_ddrc_ch0_deratectl5_t; 4721 4722 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5(uint64_t a) __attribute__ ((pure, always_inline)); 4723 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5(uint64_t a) 4724 { 4725 if (a <= 19) 4726 return 0x87e1b0210114ll + 0x1000000ll * ((a) & 0x1f); 4727 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5", 1, a, 0, 0, 0, 0, 0); 4728 } 4729 4730 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5(a) ody_dssx_ddrctl_regb_ddrc_ch0_deratectl5_t 4731 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5(a) CSR_TYPE_RSL32b 4732 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5" 4733 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5(a) 0x0 /* PF_BAR0 */ 4734 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5(a) (a) 4735 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL5(a) (a), -1, -1, -1 4736 4737 /** 4738 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_deratectl6 4739 * 4740 * DSS Ddrctl Regb Ddrc Ch0 Deratectl6 Register 4741 * Temperature Derate Control Register 6 4742 */ 4743 union ody_dssx_ddrctl_regb_ddrc_ch0_deratectl6 { 4744 uint32_t u; 4745 struct ody_dssx_ddrctl_regb_ddrc_ch0_deratectl6_s { 4746 uint32_t derate_mr4_tuf_dis : 1; 4747 uint32_t reserved_1_15 : 15; 4748 uint32_t derate_low_temp_limit : 3; 4749 uint32_t reserved_19 : 1; 4750 uint32_t derate_high_temp_limit : 3; 4751 uint32_t reserved_23_31 : 9; 4752 } s; 4753 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_deratectl6_s cn; */ 4754 }; 4755 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_deratectl6 ody_dssx_ddrctl_regb_ddrc_ch0_deratectl6_t; 4756 4757 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6(uint64_t a) __attribute__ ((pure, always_inline)); 4758 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6(uint64_t a) 4759 { 4760 if (a <= 19) 4761 return 0x87e1b0210118ll + 0x1000000ll * ((a) & 0x1f); 4762 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6", 1, a, 0, 0, 0, 0, 0); 4763 } 4764 4765 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6(a) ody_dssx_ddrctl_regb_ddrc_ch0_deratectl6_t 4766 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6(a) CSR_TYPE_RSL32b 4767 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6" 4768 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6(a) 0x0 /* PF_BAR0 */ 4769 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6(a) (a) 4770 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATECTL6(a) (a), -1, -1, -1 4771 4772 /** 4773 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_deratedbgctl 4774 * 4775 * DSS Ddrctl Regb Ddrc Ch0 Deratedbgctl Register 4776 * Temperature Derate Debug Contrl Register 4777 */ 4778 union ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgctl { 4779 uint32_t u; 4780 struct ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgctl_s { 4781 uint32_t dbg_mr4_grp_sel : 3; 4782 uint32_t reserved_3 : 1; 4783 uint32_t dbg_mr4_rank_sel : 2; 4784 uint32_t reserved_6_31 : 26; 4785 } s; 4786 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgctl_s cn; */ 4787 }; 4788 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgctl ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgctl_t; 4789 4790 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL(uint64_t a) __attribute__ ((pure, always_inline)); 4791 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL(uint64_t a) 4792 { 4793 if (a <= 19) 4794 return 0x87e1b0210124ll + 0x1000000ll * ((a) & 0x1f); 4795 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL", 1, a, 0, 0, 0, 0, 0); 4796 } 4797 4798 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgctl_t 4799 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL(a) CSR_TYPE_RSL32b 4800 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL" 4801 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL(a) 0x0 /* PF_BAR0 */ 4802 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL(a) (a) 4803 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGCTL(a) (a), -1, -1, -1 4804 4805 /** 4806 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_deratedbgstat 4807 * 4808 * DSS Ddrctl Regb Ddrc Ch0 Deratedbgstat Register 4809 * Temperature Derate Debug Status Register 4810 */ 4811 union ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgstat { 4812 uint32_t u; 4813 struct ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgstat_s { 4814 uint32_t dbg_mr4_byte0 : 8; 4815 uint32_t dbg_mr4_byte1 : 8; 4816 uint32_t dbg_mr4_byte2 : 8; 4817 uint32_t dbg_mr4_byte3 : 8; 4818 } s; 4819 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgstat_s cn; */ 4820 }; 4821 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgstat ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgstat_t; 4822 4823 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 4824 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT(uint64_t a) 4825 { 4826 if (a <= 19) 4827 return 0x87e1b0210128ll + 0x1000000ll * ((a) & 0x1f); 4828 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT", 1, a, 0, 0, 0, 0, 0); 4829 } 4830 4831 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_deratedbgstat_t 4832 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT(a) CSR_TYPE_RSL32b 4833 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT" 4834 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT(a) 0x0 /* PF_BAR0 */ 4835 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT(a) (a) 4836 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATEDBGSTAT(a) (a), -1, -1, -1 4837 4838 /** 4839 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_deratestat0 4840 * 4841 * DSS Ddrctl Regb Ddrc Ch0 Deratestat0 Register 4842 * Temperature Derate Status Register 0 4843 */ 4844 union ody_dssx_ddrctl_regb_ddrc_ch0_deratestat0 { 4845 uint32_t u; 4846 struct ody_dssx_ddrctl_regb_ddrc_ch0_deratestat0_s { 4847 uint32_t derate_temp_limit_intr : 1; 4848 uint32_t reserved_1_31 : 31; 4849 } s; 4850 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_deratestat0_s cn; */ 4851 }; 4852 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_deratestat0 ody_dssx_ddrctl_regb_ddrc_ch0_deratestat0_t; 4853 4854 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0(uint64_t a) __attribute__ ((pure, always_inline)); 4855 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0(uint64_t a) 4856 { 4857 if (a <= 19) 4858 return 0x87e1b021011cll + 0x1000000ll * ((a) & 0x1f); 4859 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0", 1, a, 0, 0, 0, 0, 0); 4860 } 4861 4862 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_deratestat0_t 4863 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0(a) CSR_TYPE_RSL32b 4864 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0" 4865 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0(a) 0x0 /* PF_BAR0 */ 4866 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0(a) (a) 4867 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT0(a) (a), -1, -1, -1 4868 4869 /** 4870 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_deratestat1 4871 * 4872 * DSS Ddrctl Regb Ddrc Ch0 Deratestat1 Register 4873 * Temperature Derate Status Register 1 4874 */ 4875 union ody_dssx_ddrctl_regb_ddrc_ch0_deratestat1 { 4876 uint32_t u; 4877 struct ody_dssx_ddrctl_regb_ddrc_ch0_deratestat1_s { 4878 uint32_t refresh_rate_rank0 : 3; 4879 uint32_t reserved_3 : 1; 4880 uint32_t refresh_rate_rank1 : 3; 4881 uint32_t reserved_7_31 : 25; 4882 } s; 4883 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_deratestat1_s cn; */ 4884 }; 4885 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_deratestat1 ody_dssx_ddrctl_regb_ddrc_ch0_deratestat1_t; 4886 4887 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1(uint64_t a) __attribute__ ((pure, always_inline)); 4888 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1(uint64_t a) 4889 { 4890 if (a <= 19) 4891 return 0x87e1b0210120ll + 0x1000000ll * ((a) & 0x1f); 4892 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1", 1, a, 0, 0, 0, 0, 0); 4893 } 4894 4895 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1(a) ody_dssx_ddrctl_regb_ddrc_ch0_deratestat1_t 4896 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1(a) CSR_TYPE_RSL32b 4897 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1" 4898 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1(a) 0x0 /* PF_BAR0 */ 4899 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1(a) (a) 4900 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DERATESTAT1(a) (a), -1, -1, -1 4901 4902 /** 4903 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_dfilpcfg0 4904 * 4905 * DSS Ddrctl Regb Ddrc Ch0 Dfilpcfg0 Register 4906 * DFI Low Power Configuration Register 0 4907 */ 4908 union ody_dssx_ddrctl_regb_ddrc_ch0_dfilpcfg0 { 4909 uint32_t u; 4910 struct ody_dssx_ddrctl_regb_ddrc_ch0_dfilpcfg0_s { 4911 uint32_t dfi_lp_en_pd : 1; 4912 uint32_t reserved_1_3 : 3; 4913 uint32_t dfi_lp_en_sr : 1; 4914 uint32_t reserved_5_15 : 11; 4915 uint32_t dfi_lp_en_data : 1; 4916 uint32_t reserved_17_31 : 15; 4917 } s; 4918 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_dfilpcfg0_s cn; */ 4919 }; 4920 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_dfilpcfg0 ody_dssx_ddrctl_regb_ddrc_ch0_dfilpcfg0_t; 4921 4922 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0(uint64_t a) __attribute__ ((pure, always_inline)); 4923 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0(uint64_t a) 4924 { 4925 if (a <= 19) 4926 return 0x87e1b0210500ll + 0x1000000ll * ((a) & 0x1f); 4927 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0", 1, a, 0, 0, 0, 0, 0); 4928 } 4929 4930 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0(a) ody_dssx_ddrctl_regb_ddrc_ch0_dfilpcfg0_t 4931 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0(a) CSR_TYPE_RSL32b 4932 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0" 4933 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0(a) 0x0 /* PF_BAR0 */ 4934 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0(a) (a) 4935 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFILPCFG0(a) (a), -1, -1, -1 4936 4937 /** 4938 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_dfimisc 4939 * 4940 * DSS Ddrctl Regb Ddrc Ch0 Dfimisc Register 4941 * DFI Miscellaneous Control Register 4942 */ 4943 union ody_dssx_ddrctl_regb_ddrc_ch0_dfimisc { 4944 uint32_t u; 4945 struct ody_dssx_ddrctl_regb_ddrc_ch0_dfimisc_s { 4946 uint32_t reserved_0_1 : 2; 4947 uint32_t dfi_data_cs_polarity : 1; 4948 uint32_t reserved_3_4 : 2; 4949 uint32_t dfi_init_start : 1; 4950 uint32_t reserved_6_7 : 2; 4951 uint32_t dfi_frequency : 5; 4952 uint32_t reserved_13_31 : 19; 4953 } s; 4954 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_dfimisc_s cn; */ 4955 }; 4956 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_dfimisc ody_dssx_ddrctl_regb_ddrc_ch0_dfimisc_t; 4957 4958 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC(uint64_t a) __attribute__ ((pure, always_inline)); 4959 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC(uint64_t a) 4960 { 4961 if (a <= 19) 4962 return 0x87e1b0210510ll + 0x1000000ll * ((a) & 0x1f); 4963 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC", 1, a, 0, 0, 0, 0, 0); 4964 } 4965 4966 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC(a) ody_dssx_ddrctl_regb_ddrc_ch0_dfimisc_t 4967 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC(a) CSR_TYPE_RSL32b 4968 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC" 4969 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC(a) 0x0 /* PF_BAR0 */ 4970 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC(a) (a) 4971 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIMISC(a) (a), -1, -1, -1 4972 4973 /** 4974 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_dfistat 4975 * 4976 * DSS Ddrctl Regb Ddrc Ch0 Dfistat Register 4977 * DFI Status Register 4978 */ 4979 union ody_dssx_ddrctl_regb_ddrc_ch0_dfistat { 4980 uint32_t u; 4981 struct ody_dssx_ddrctl_regb_ddrc_ch0_dfistat_s { 4982 uint32_t dfi_init_complete : 1; 4983 uint32_t dfi_lp_ctrl_ack_stat : 1; 4984 uint32_t dfi_lp_data_ack_stat : 1; 4985 uint32_t reserved_3_31 : 29; 4986 } s; 4987 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_dfistat_s cn; */ 4988 }; 4989 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_dfistat ody_dssx_ddrctl_regb_ddrc_ch0_dfistat_t; 4990 4991 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT(uint64_t a) __attribute__ ((pure, always_inline)); 4992 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT(uint64_t a) 4993 { 4994 if (a <= 19) 4995 return 0x87e1b0210514ll + 0x1000000ll * ((a) & 0x1f); 4996 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT", 1, a, 0, 0, 0, 0, 0); 4997 } 4998 4999 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_dfistat_t 5000 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT(a) CSR_TYPE_RSL32b 5001 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT" 5002 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT(a) 0x0 /* PF_BAR0 */ 5003 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT(a) (a) 5004 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFISTAT(a) (a), -1, -1, -1 5005 5006 /** 5007 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_dfiupd0 5008 * 5009 * DSS Ddrctl Regb Ddrc Ch0 Dfiupd0 Register 5010 * DFI Update Register 0 5011 */ 5012 union ody_dssx_ddrctl_regb_ddrc_ch0_dfiupd0 { 5013 uint32_t u; 5014 struct ody_dssx_ddrctl_regb_ddrc_ch0_dfiupd0_s { 5015 uint32_t reserved_0_28 : 29; 5016 uint32_t ctrlupd_pre_srx : 1; 5017 uint32_t dis_auto_ctrlupd_srx : 1; 5018 uint32_t reserved_31 : 1; 5019 } s; 5020 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_dfiupd0_s cn; */ 5021 }; 5022 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_dfiupd0 ody_dssx_ddrctl_regb_ddrc_ch0_dfiupd0_t; 5023 5024 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0(uint64_t a) __attribute__ ((pure, always_inline)); 5025 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0(uint64_t a) 5026 { 5027 if (a <= 19) 5028 return 0x87e1b0210508ll + 0x1000000ll * ((a) & 0x1f); 5029 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0", 1, a, 0, 0, 0, 0, 0); 5030 } 5031 5032 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0(a) ody_dssx_ddrctl_regb_ddrc_ch0_dfiupd0_t 5033 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0(a) CSR_TYPE_RSL32b 5034 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0" 5035 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0(a) 0x0 /* PF_BAR0 */ 5036 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0(a) (a) 5037 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DFIUPD0(a) (a), -1, -1, -1 5038 5039 /** 5040 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_dimmctl 5041 * 5042 * DSS Ddrctl Regb Ddrc Ch0 Dimmctl Register 5043 * DIMM Control Register 5044 */ 5045 union ody_dssx_ddrctl_regb_ddrc_ch0_dimmctl { 5046 uint32_t u; 5047 struct ody_dssx_ddrctl_regb_ddrc_ch0_dimmctl_s { 5048 uint32_t dimm_stagger_cs_en : 1; 5049 uint32_t reserved_1_9 : 9; 5050 uint32_t dimm_type : 2; 5051 uint32_t reserved_12_14 : 3; 5052 uint32_t dimm_selfref_clock_stop_mode : 1; 5053 uint32_t reserved_16_31 : 16; 5054 } s; 5055 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_dimmctl_s cn; */ 5056 }; 5057 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_dimmctl ody_dssx_ddrctl_regb_ddrc_ch0_dimmctl_t; 5058 5059 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL(uint64_t a) __attribute__ ((pure, always_inline)); 5060 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL(uint64_t a) 5061 { 5062 if (a <= 19) 5063 return 0x87e1b0210c88ll + 0x1000000ll * ((a) & 0x1f); 5064 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL", 1, a, 0, 0, 0, 0, 0); 5065 } 5066 5067 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_dimmctl_t 5068 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL(a) CSR_TYPE_RSL32b 5069 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL" 5070 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL(a) 0x0 /* PF_BAR0 */ 5071 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL(a) (a) 5072 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DIMMCTL(a) (a), -1, -1, -1 5073 5074 /** 5075 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_dqsosccfg0 5076 * 5077 * DSS Ddrctl Regb Ddrc Ch0 Dqsosccfg0 Register 5078 * DQSOSC Config Register 0 5079 */ 5080 union ody_dssx_ddrctl_regb_ddrc_ch0_dqsosccfg0 { 5081 uint32_t u; 5082 struct ody_dssx_ddrctl_regb_ddrc_ch0_dqsosccfg0_s { 5083 uint32_t dis_dqsosc_srx : 1; 5084 uint32_t reserved_1_31 : 31; 5085 } s; 5086 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_dqsosccfg0_s cn; */ 5087 }; 5088 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_dqsosccfg0 ody_dssx_ddrctl_regb_ddrc_ch0_dqsosccfg0_t; 5089 5090 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0(uint64_t a) __attribute__ ((pure, always_inline)); 5091 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0(uint64_t a) 5092 { 5093 if (a <= 19) 5094 return 0x87e1b0210308ll + 0x1000000ll * ((a) & 0x1f); 5095 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0", 1, a, 0, 0, 0, 0, 0); 5096 } 5097 5098 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0(a) ody_dssx_ddrctl_regb_ddrc_ch0_dqsosccfg0_t 5099 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0(a) CSR_TYPE_RSL32b 5100 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0" 5101 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0(a) 0x0 /* PF_BAR0 */ 5102 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0(a) (a) 5103 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCCFG0(a) (a), -1, -1, -1 5104 5105 /** 5106 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_dqsosctmg0 5107 * 5108 * DSS Ddrctl Regb Ddrc Ch0 Dqsosctmg0 Register 5109 * DQS OSC timing register for DRAM timing set 1 5110 */ 5111 union ody_dssx_ddrctl_regb_ddrc_ch0_dqsosctmg0 { 5112 uint32_t u; 5113 struct ody_dssx_ddrctl_regb_ddrc_ch0_dqsosctmg0_s { 5114 uint32_t t_oscs : 14; 5115 uint32_t reserved_14_31 : 18; 5116 } s; 5117 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_dqsosctmg0_s cn; */ 5118 }; 5119 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_dqsosctmg0 ody_dssx_ddrctl_regb_ddrc_ch0_dqsosctmg0_t; 5120 5121 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0(uint64_t a) __attribute__ ((pure, always_inline)); 5122 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0(uint64_t a) 5123 { 5124 if (a <= 19) 5125 return 0x87e1b021030cll + 0x1000000ll * ((a) & 0x1f); 5126 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0", 1, a, 0, 0, 0, 0, 0); 5127 } 5128 5129 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0(a) ody_dssx_ddrctl_regb_ddrc_ch0_dqsosctmg0_t 5130 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0(a) CSR_TYPE_RSL32b 5131 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0" 5132 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0(a) 0x0 /* PF_BAR0 */ 5133 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0(a) (a) 5134 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DQSOSCTMG0(a) (a), -1, -1, -1 5135 5136 /** 5137 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ds_dbg_ctrl0 5138 * 5139 * DSS Ddrctl Regb Ddrc Ch0 Ds Dbg Ctrl0 Register 5140 * PASDS DEBUG CTRL Register 5141 */ 5142 union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_ctrl0 { 5143 uint32_t u; 5144 struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_ctrl0_s { 5145 uint32_t dbg_bsm_sel_ctrl : 16; 5146 uint32_t dbg_lrsm_sel_ctrl : 16; 5147 } s; 5148 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_ctrl0_s cn; */ 5149 }; 5150 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_ctrl0 ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_ctrl0_t; 5151 5152 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0(uint64_t a) __attribute__ ((pure, always_inline)); 5153 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0(uint64_t a) 5154 { 5155 if (a <= 19) 5156 return 0x87e1b0210d80ll + 0x1000000ll * ((a) & 0x1f); 5157 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0", 1, a, 0, 0, 0, 0, 0); 5158 } 5159 5160 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0(a) ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_ctrl0_t 5161 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0(a) CSR_TYPE_RSL32b 5162 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0" 5163 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0(a) 0x0 /* PF_BAR0 */ 5164 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0(a) (a) 5165 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_CTRL0(a) (a), -1, -1, -1 5166 5167 /** 5168 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ds_dbg_stat0 5169 * 5170 * DSS Ddrctl Regb Ddrc Ch0 Ds Dbg Stat0 Register 5171 * PASDS DEBUG STAT0 Register 5172 */ 5173 union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat0 { 5174 uint32_t u; 5175 struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat0_s { 5176 uint32_t dbg_stat0 : 32; 5177 } s; 5178 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat0_s cn; */ 5179 }; 5180 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat0 ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat0_t; 5181 5182 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0(uint64_t a) __attribute__ ((pure, always_inline)); 5183 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0(uint64_t a) 5184 { 5185 if (a <= 19) 5186 return 0x87e1b0210d84ll + 0x1000000ll * ((a) & 0x1f); 5187 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0", 1, a, 0, 0, 0, 0, 0); 5188 } 5189 5190 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat0_t 5191 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0(a) CSR_TYPE_RSL32b 5192 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0" 5193 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0(a) 0x0 /* PF_BAR0 */ 5194 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0(a) (a) 5195 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT0(a) (a), -1, -1, -1 5196 5197 /** 5198 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ds_dbg_stat1 5199 * 5200 * DSS Ddrctl Regb Ddrc Ch0 Ds Dbg Stat1 Register 5201 * PASDS DEBUG STAT1 Register 5202 */ 5203 union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat1 { 5204 uint32_t u; 5205 struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat1_s { 5206 uint32_t dbg_stat1 : 32; 5207 } s; 5208 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat1_s cn; */ 5209 }; 5210 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat1 ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat1_t; 5211 5212 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1(uint64_t a) __attribute__ ((pure, always_inline)); 5213 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1(uint64_t a) 5214 { 5215 if (a <= 19) 5216 return 0x87e1b0210d88ll + 0x1000000ll * ((a) & 0x1f); 5217 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1", 1, a, 0, 0, 0, 0, 0); 5218 } 5219 5220 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1(a) ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat1_t 5221 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1(a) CSR_TYPE_RSL32b 5222 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1" 5223 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1(a) 0x0 /* PF_BAR0 */ 5224 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1(a) (a) 5225 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT1(a) (a), -1, -1, -1 5226 5227 /** 5228 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ds_dbg_stat2 5229 * 5230 * DSS Ddrctl Regb Ddrc Ch0 Ds Dbg Stat2 Register 5231 * PASDS DEBUG STAT2 Register 5232 */ 5233 union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat2 { 5234 uint32_t u; 5235 struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat2_s { 5236 uint32_t dbg_stat2 : 32; 5237 } s; 5238 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat2_s cn; */ 5239 }; 5240 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat2 ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat2_t; 5241 5242 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2(uint64_t a) __attribute__ ((pure, always_inline)); 5243 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2(uint64_t a) 5244 { 5245 if (a <= 19) 5246 return 0x87e1b0210d8cll + 0x1000000ll * ((a) & 0x1f); 5247 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2", 1, a, 0, 0, 0, 0, 0); 5248 } 5249 5250 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2(a) ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat2_t 5251 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2(a) CSR_TYPE_RSL32b 5252 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2" 5253 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2(a) 0x0 /* PF_BAR0 */ 5254 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2(a) (a) 5255 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT2(a) (a), -1, -1, -1 5256 5257 /** 5258 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ds_dbg_stat3 5259 * 5260 * DSS Ddrctl Regb Ddrc Ch0 Ds Dbg Stat3 Register 5261 * PASDS DEBUG STAT3 Register 5262 */ 5263 union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat3 { 5264 uint32_t u; 5265 struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat3_s { 5266 uint32_t dbg_stat3 : 32; 5267 } s; 5268 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat3_s cn; */ 5269 }; 5270 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat3 ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat3_t; 5271 5272 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3(uint64_t a) __attribute__ ((pure, always_inline)); 5273 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3(uint64_t a) 5274 { 5275 if (a <= 19) 5276 return 0x87e1b0210d90ll + 0x1000000ll * ((a) & 0x1f); 5277 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3", 1, a, 0, 0, 0, 0, 0); 5278 } 5279 5280 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3(a) ody_dssx_ddrctl_regb_ddrc_ch0_ds_dbg_stat3_t 5281 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3(a) CSR_TYPE_RSL32b 5282 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3" 5283 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3(a) 0x0 /* PF_BAR0 */ 5284 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3(a) (a) 5285 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DS_DBG_STAT3(a) (a), -1, -1, -1 5286 5287 /** 5288 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_du_cfgbuf_ctrl 5289 * 5290 * DSS Ddrctl Regb Ddrc Ch0 Du Cfgbuf Ctrl Register 5291 * DDR_UTIL config buffer control register 5292 */ 5293 union ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_ctrl { 5294 uint32_t u; 5295 struct ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_ctrl_s { 5296 uint32_t du_cfgbuf_wdata : 16; 5297 uint32_t du_cfgbuf_addr : 8; 5298 uint32_t du_cfgbuf_select : 1; 5299 uint32_t reserved_25_28 : 4; 5300 uint32_t du_cfgbuf_op_mode : 1; 5301 uint32_t du_cfgbuf_rw_type : 1; 5302 uint32_t du_cfgbuf_rw_start : 1; 5303 } s; 5304 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_ctrl_s cn; */ 5305 }; 5306 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_ctrl ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_ctrl_t; 5307 5308 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 5309 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL(uint64_t a) 5310 { 5311 if (a <= 19) 5312 return 0x87e1b0210b24ll + 0x1000000ll * ((a) & 0x1f); 5313 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL", 1, a, 0, 0, 0, 0, 0); 5314 } 5315 5316 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL(a) ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_ctrl_t 5317 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL(a) CSR_TYPE_RSL32b 5318 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL" 5319 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL(a) 0x0 /* PF_BAR0 */ 5320 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL(a) (a) 5321 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_CTRL(a) (a), -1, -1, -1 5322 5323 /** 5324 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_du_cfgbuf_stat 5325 * 5326 * DSS Ddrctl Regb Ddrc Ch0 Du Cfgbuf Stat Register 5327 * DDR_UTIL config buffer status register. 5328 */ 5329 union ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_stat { 5330 uint32_t u; 5331 struct ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_stat_s { 5332 uint32_t du_cfgbuf_rdata : 16; 5333 uint32_t reserved_16_31 : 16; 5334 } s; 5335 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_stat_s cn; */ 5336 }; 5337 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_stat ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_stat_t; 5338 5339 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT(uint64_t a) __attribute__ ((pure, always_inline)); 5340 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT(uint64_t a) 5341 { 5342 if (a <= 19) 5343 return 0x87e1b0210b28ll + 0x1000000ll * ((a) & 0x1f); 5344 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT", 1, a, 0, 0, 0, 0, 0); 5345 } 5346 5347 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_du_cfgbuf_stat_t 5348 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT(a) CSR_TYPE_RSL32b 5349 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT" 5350 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT(a) 0x0 /* PF_BAR0 */ 5351 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT(a) (a) 5352 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CFGBUF_STAT(a) (a), -1, -1, -1 5353 5354 /** 5355 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_du_cmdbuf_ctrl 5356 * 5357 * DSS Ddrctl Regb Ddrc Ch0 Du Cmdbuf Ctrl Register 5358 * DDR_UTIL command buffer control register 5359 */ 5360 union ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_ctrl { 5361 uint32_t u; 5362 struct ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_ctrl_s { 5363 uint32_t du_cmdbuf_wdata : 16; 5364 uint32_t du_cmdbuf_addr : 8; 5365 uint32_t du_cmdbuf_select : 1; 5366 uint32_t reserved_25_28 : 4; 5367 uint32_t du_cmdbuf_op_mode : 1; 5368 uint32_t du_cmdbuf_rw_type : 1; 5369 uint32_t du_cmdbuf_rw_start : 1; 5370 } s; 5371 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_ctrl_s cn; */ 5372 }; 5373 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_ctrl ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_ctrl_t; 5374 5375 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 5376 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL(uint64_t a) 5377 { 5378 if (a <= 19) 5379 return 0x87e1b0210b2cll + 0x1000000ll * ((a) & 0x1f); 5380 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL", 1, a, 0, 0, 0, 0, 0); 5381 } 5382 5383 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL(a) ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_ctrl_t 5384 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL(a) CSR_TYPE_RSL32b 5385 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL" 5386 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL(a) 0x0 /* PF_BAR0 */ 5387 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL(a) (a) 5388 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_CTRL(a) (a), -1, -1, -1 5389 5390 /** 5391 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_du_cmdbuf_stat 5392 * 5393 * DSS Ddrctl Regb Ddrc Ch0 Du Cmdbuf Stat Register 5394 * DDR_UTIL command buffer status register. 5395 */ 5396 union ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_stat { 5397 uint32_t u; 5398 struct ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_stat_s { 5399 uint32_t du_cmdbuf_rdata : 16; 5400 uint32_t reserved_16_31 : 16; 5401 } s; 5402 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_stat_s cn; */ 5403 }; 5404 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_stat ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_stat_t; 5405 5406 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT(uint64_t a) __attribute__ ((pure, always_inline)); 5407 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT(uint64_t a) 5408 { 5409 if (a <= 19) 5410 return 0x87e1b0210b30ll + 0x1000000ll * ((a) & 0x1f); 5411 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT", 1, a, 0, 0, 0, 0, 0); 5412 } 5413 5414 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_du_cmdbuf_stat_t 5415 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT(a) CSR_TYPE_RSL32b 5416 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT" 5417 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT(a) 0x0 /* PF_BAR0 */ 5418 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT(a) (a) 5419 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_CMDBUF_STAT(a) (a), -1, -1, -1 5420 5421 /** 5422 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_du_dbg_stat0 5423 * 5424 * DSS Ddrctl Regb Ddrc Ch0 Du Dbg Stat0 Register 5425 * PASDU DEBUG STAT0 Register 5426 */ 5427 union ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat0 { 5428 uint32_t u; 5429 struct ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat0_s { 5430 uint32_t du_cur_blk_ucode : 16; 5431 uint32_t du_cur_blk_addr : 8; 5432 uint32_t du_cur_blk_index : 5; 5433 uint32_t du_cur_blk_set : 1; 5434 uint32_t reserved_30_31 : 2; 5435 } s; 5436 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat0_s cn; */ 5437 }; 5438 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat0 ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat0_t; 5439 5440 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0(uint64_t a) __attribute__ ((pure, always_inline)); 5441 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0(uint64_t a) 5442 { 5443 if (a <= 19) 5444 return 0x87e1b0210d94ll + 0x1000000ll * ((a) & 0x1f); 5445 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0", 1, a, 0, 0, 0, 0, 0); 5446 } 5447 5448 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat0_t 5449 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0(a) CSR_TYPE_RSL32b 5450 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0" 5451 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0(a) 0x0 /* PF_BAR0 */ 5452 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0(a) (a) 5453 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT0(a) (a), -1, -1, -1 5454 5455 /** 5456 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_du_dbg_stat1 5457 * 5458 * DSS Ddrctl Regb Ddrc Ch0 Du Dbg Stat1 Register 5459 * PASDU DEBUG STAT1 Register 5460 */ 5461 union ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat1 { 5462 uint32_t u; 5463 struct ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat1_s { 5464 uint32_t du_main_fsm_state : 3; 5465 uint32_t reserved_3 : 1; 5466 uint32_t du_sceu_fsm_state : 3; 5467 uint32_t reserved_7 : 1; 5468 uint32_t du_mceu_fsm_state : 3; 5469 uint32_t reserved_11_31 : 21; 5470 } s; 5471 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat1_s cn; */ 5472 }; 5473 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat1 ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat1_t; 5474 5475 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1(uint64_t a) __attribute__ ((pure, always_inline)); 5476 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1(uint64_t a) 5477 { 5478 if (a <= 19) 5479 return 0x87e1b0210d98ll + 0x1000000ll * ((a) & 0x1f); 5480 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1", 1, a, 0, 0, 0, 0, 0); 5481 } 5482 5483 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1(a) ody_dssx_ddrctl_regb_ddrc_ch0_du_dbg_stat1_t 5484 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1(a) CSR_TYPE_RSL32b 5485 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1" 5486 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1(a) 0x0 /* PF_BAR0 */ 5487 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1(a) (a) 5488 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_DU_DBG_STAT1(a) (a), -1, -1, -1 5489 5490 /** 5491 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccbitmask0 5492 * 5493 * DSS Ddrctl Regb Ddrc Ch0 Eccbitmask0 Register 5494 * ECC Corrected Data Bit Mask Register 0 5495 */ 5496 union ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask0 { 5497 uint32_t u; 5498 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask0_s { 5499 uint32_t ecc_corr_bit_mask_31_0 : 32; 5500 } s; 5501 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask0_s cn; */ 5502 }; 5503 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask0 ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask0_t; 5504 5505 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0(uint64_t a) __attribute__ ((pure, always_inline)); 5506 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0(uint64_t a) 5507 { 5508 if (a <= 19) 5509 return 0x87e1b0210628ll + 0x1000000ll * ((a) & 0x1f); 5510 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0", 1, a, 0, 0, 0, 0, 0); 5511 } 5512 5513 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask0_t 5514 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0(a) CSR_TYPE_RSL32b 5515 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0" 5516 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0(a) 0x0 /* PF_BAR0 */ 5517 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0(a) (a) 5518 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK0(a) (a), -1, -1, -1 5519 5520 /** 5521 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccbitmask1 5522 * 5523 * DSS Ddrctl Regb Ddrc Ch0 Eccbitmask1 Register 5524 * ECC Corrected Data Bit Mask Register 1 5525 */ 5526 union ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask1 { 5527 uint32_t u; 5528 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask1_s { 5529 uint32_t ecc_corr_bit_mask_63_32 : 32; 5530 } s; 5531 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask1_s cn; */ 5532 }; 5533 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask1 ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask1_t; 5534 5535 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1(uint64_t a) __attribute__ ((pure, always_inline)); 5536 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1(uint64_t a) 5537 { 5538 if (a <= 19) 5539 return 0x87e1b021062cll + 0x1000000ll * ((a) & 0x1f); 5540 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1", 1, a, 0, 0, 0, 0, 0); 5541 } 5542 5543 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask1_t 5544 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1(a) CSR_TYPE_RSL32b 5545 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1" 5546 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1(a) 0x0 /* PF_BAR0 */ 5547 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1(a) (a) 5548 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK1(a) (a), -1, -1, -1 5549 5550 /** 5551 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccbitmask2 5552 * 5553 * DSS Ddrctl Regb Ddrc Ch0 Eccbitmask2 Register 5554 * ECC Corrected Data Bit Mask Register 2 5555 */ 5556 union ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask2 { 5557 uint32_t u; 5558 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask2_s { 5559 uint32_t ecc_corr_bit_mask_71_64 : 8; 5560 uint32_t reserved_8_31 : 24; 5561 } s; 5562 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask2_s cn; */ 5563 }; 5564 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask2 ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask2_t; 5565 5566 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2(uint64_t a) __attribute__ ((pure, always_inline)); 5567 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2(uint64_t a) 5568 { 5569 if (a <= 19) 5570 return 0x87e1b0210630ll + 0x1000000ll * ((a) & 0x1f); 5571 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2", 1, a, 0, 0, 0, 0, 0); 5572 } 5573 5574 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccbitmask2_t 5575 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2(a) CSR_TYPE_RSL32b 5576 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2" 5577 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2(a) 0x0 /* PF_BAR0 */ 5578 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2(a) (a) 5579 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCBITMASK2(a) (a), -1, -1, -1 5580 5581 /** 5582 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecccaddr0 5583 * 5584 * DSS Ddrctl Regb Ddrc Ch0 Ecccaddr0 Register 5585 * ECC Corrected Error Address Register 0 5586 */ 5587 union ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr0 { 5588 uint32_t u; 5589 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr0_s { 5590 uint32_t ecc_corr_row : 18; 5591 uint32_t reserved_18_23 : 6; 5592 uint32_t ecc_corr_rank : 1; 5593 uint32_t reserved_25_31 : 7; 5594 } s; 5595 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr0_s cn; */ 5596 }; 5597 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr0 ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr0_t; 5598 5599 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0(uint64_t a) __attribute__ ((pure, always_inline)); 5600 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0(uint64_t a) 5601 { 5602 if (a <= 19) 5603 return 0x87e1b0210614ll + 0x1000000ll * ((a) & 0x1f); 5604 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0", 1, a, 0, 0, 0, 0, 0); 5605 } 5606 5607 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr0_t 5608 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0(a) CSR_TYPE_RSL32b 5609 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0" 5610 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0(a) 0x0 /* PF_BAR0 */ 5611 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0(a) (a) 5612 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR0(a) (a), -1, -1, -1 5613 5614 /** 5615 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecccaddr1 5616 * 5617 * DSS Ddrctl Regb Ddrc Ch0 Ecccaddr1 Register 5618 * ECC Corrected Error Address Register 1 5619 */ 5620 union ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr1 { 5621 uint32_t u; 5622 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr1_s { 5623 uint32_t ecc_corr_col : 11; 5624 uint32_t reserved_11_15 : 5; 5625 uint32_t ecc_corr_bank : 2; 5626 uint32_t reserved_18_23 : 6; 5627 uint32_t ecc_corr_bg : 3; 5628 uint32_t reserved_27_31 : 5; 5629 } s; 5630 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr1_s cn; */ 5631 }; 5632 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr1 ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr1_t; 5633 5634 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1(uint64_t a) __attribute__ ((pure, always_inline)); 5635 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1(uint64_t a) 5636 { 5637 if (a <= 19) 5638 return 0x87e1b0210618ll + 0x1000000ll * ((a) & 0x1f); 5639 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1", 1, a, 0, 0, 0, 0, 0); 5640 } 5641 5642 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecccaddr1_t 5643 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1(a) CSR_TYPE_RSL32b 5644 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1" 5645 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1(a) 0x0 /* PF_BAR0 */ 5646 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1(a) (a) 5647 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCADDR1(a) (a), -1, -1, -1 5648 5649 /** 5650 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecccdata0 5651 * 5652 * DSS Ddrctl Regb Ddrc Ch0 Ecccdata0 Register 5653 * ECC Corrected Data Register 0 5654 */ 5655 union ody_dssx_ddrctl_regb_ddrc_ch0_ecccdata0 { 5656 uint32_t u; 5657 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccdata0_s { 5658 uint32_t ecc_corr_data_31_0 : 32; 5659 } s; 5660 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccdata0_s cn; */ 5661 }; 5662 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecccdata0 ody_dssx_ddrctl_regb_ddrc_ch0_ecccdata0_t; 5663 5664 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0(uint64_t a) __attribute__ ((pure, always_inline)); 5665 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0(uint64_t a) 5666 { 5667 if (a <= 19) 5668 return 0x87e1b021066cll + 0x1000000ll * ((a) & 0x1f); 5669 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0", 1, a, 0, 0, 0, 0, 0); 5670 } 5671 5672 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecccdata0_t 5673 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0(a) CSR_TYPE_RSL32b 5674 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0" 5675 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0(a) 0x0 /* PF_BAR0 */ 5676 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0(a) (a) 5677 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCDATA0(a) (a), -1, -1, -1 5678 5679 /** 5680 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecccfg0 5681 * 5682 * DSS Ddrctl Regb Ddrc Ch0 Ecccfg0 Register 5683 * ECC Configuration Register 0 5684 */ 5685 union ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg0 { 5686 uint32_t u; 5687 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg0_s { 5688 uint32_t ecc_mode : 3; 5689 uint32_t test_mode : 1; 5690 uint32_t ecc_type : 2; 5691 uint32_t reserved_6_22 : 17; 5692 uint32_t dis_scrub : 1; 5693 uint32_t reserved_24_31 : 8; 5694 } s; 5695 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg0_s cn; */ 5696 }; 5697 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg0 ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg0_t; 5698 5699 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0(uint64_t a) __attribute__ ((pure, always_inline)); 5700 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0(uint64_t a) 5701 { 5702 if (a <= 19) 5703 return 0x87e1b0210600ll + 0x1000000ll * ((a) & 0x1f); 5704 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0", 1, a, 0, 0, 0, 0, 0); 5705 } 5706 5707 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg0_t 5708 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0(a) CSR_TYPE_RSL32b 5709 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0" 5710 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0(a) 0x0 /* PF_BAR0 */ 5711 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0(a) (a) 5712 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG0(a) (a), -1, -1, -1 5713 5714 /** 5715 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecccfg1 5716 * 5717 * DSS Ddrctl Regb Ddrc Ch0 Ecccfg1 Register 5718 * ECC Configuration Register 1 5719 */ 5720 union ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg1 { 5721 uint32_t u; 5722 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg1_s { 5723 uint32_t data_poison_en : 1; 5724 uint32_t data_poison_bit : 1; 5725 uint32_t poison_chip_en : 1; 5726 uint32_t reserved_3_14 : 12; 5727 uint32_t poison_advecc_kbd : 1; 5728 uint32_t poison_num_dfi_beat : 1; 5729 uint32_t reserved_17_31 : 15; 5730 } s; 5731 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg1_s cn; */ 5732 }; 5733 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg1 ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg1_t; 5734 5735 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1(uint64_t a) __attribute__ ((pure, always_inline)); 5736 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1(uint64_t a) 5737 { 5738 if (a <= 19) 5739 return 0x87e1b0210604ll + 0x1000000ll * ((a) & 0x1f); 5740 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1", 1, a, 0, 0, 0, 0, 0); 5741 } 5742 5743 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg1_t 5744 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1(a) CSR_TYPE_RSL32b 5745 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1" 5746 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1(a) 0x0 /* PF_BAR0 */ 5747 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1(a) (a) 5748 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG1(a) (a), -1, -1, -1 5749 5750 /** 5751 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecccfg2 5752 * 5753 * DSS Ddrctl Regb Ddrc Ch0 Ecccfg2 Register 5754 * ECC Configuration Register 2 5755 */ 5756 union ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg2 { 5757 uint32_t u; 5758 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg2_s { 5759 uint32_t bypass_internal_ecc : 1; 5760 uint32_t kbd_en : 1; 5761 uint32_t reserved_2_15 : 14; 5762 uint32_t flip_bit_pos0 : 7; 5763 uint32_t reserved_23 : 1; 5764 uint32_t flip_bit_pos1 : 7; 5765 uint32_t reserved_31 : 1; 5766 } s; 5767 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg2_s cn; */ 5768 }; 5769 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg2 ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg2_t; 5770 5771 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2(uint64_t a) __attribute__ ((pure, always_inline)); 5772 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2(uint64_t a) 5773 { 5774 if (a <= 19) 5775 return 0x87e1b0210668ll + 0x1000000ll * ((a) & 0x1f); 5776 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2", 1, a, 0, 0, 0, 0, 0); 5777 } 5778 5779 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecccfg2_t 5780 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2(a) CSR_TYPE_RSL32b 5781 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2" 5782 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2(a) 0x0 /* PF_BAR0 */ 5783 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2(a) (a) 5784 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCFG2(a) (a), -1, -1, -1 5785 5786 /** 5787 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecccsyn0 5788 * 5789 * DSS Ddrctl Regb Ddrc Ch0 Ecccsyn0 Register 5790 * ECC Corrected Syndrome Register 0 5791 */ 5792 union ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn0 { 5793 uint32_t u; 5794 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn0_s { 5795 uint32_t ecc_corr_syndromes_31_0 : 32; 5796 } s; 5797 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn0_s cn; */ 5798 }; 5799 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn0 ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn0_t; 5800 5801 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0(uint64_t a) __attribute__ ((pure, always_inline)); 5802 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0(uint64_t a) 5803 { 5804 if (a <= 19) 5805 return 0x87e1b021061cll + 0x1000000ll * ((a) & 0x1f); 5806 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0", 1, a, 0, 0, 0, 0, 0); 5807 } 5808 5809 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn0_t 5810 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0(a) CSR_TYPE_RSL32b 5811 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0" 5812 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0(a) 0x0 /* PF_BAR0 */ 5813 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0(a) (a) 5814 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN0(a) (a), -1, -1, -1 5815 5816 /** 5817 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecccsyn1 5818 * 5819 * DSS Ddrctl Regb Ddrc Ch0 Ecccsyn1 Register 5820 * ECC Corrected Syndrome Register 1 5821 */ 5822 union ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn1 { 5823 uint32_t u; 5824 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn1_s { 5825 uint32_t ecc_corr_syndromes_63_32 : 32; 5826 } s; 5827 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn1_s cn; */ 5828 }; 5829 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn1 ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn1_t; 5830 5831 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1(uint64_t a) __attribute__ ((pure, always_inline)); 5832 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1(uint64_t a) 5833 { 5834 if (a <= 19) 5835 return 0x87e1b0210620ll + 0x1000000ll * ((a) & 0x1f); 5836 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1", 1, a, 0, 0, 0, 0, 0); 5837 } 5838 5839 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn1_t 5840 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1(a) CSR_TYPE_RSL32b 5841 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1" 5842 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1(a) 0x0 /* PF_BAR0 */ 5843 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1(a) (a) 5844 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN1(a) (a), -1, -1, -1 5845 5846 /** 5847 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecccsyn2 5848 * 5849 * DSS Ddrctl Regb Ddrc Ch0 Ecccsyn2 Register 5850 * ECC Corrected Syndrome Register 2 5851 */ 5852 union ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn2 { 5853 uint32_t u; 5854 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn2_s { 5855 uint32_t ecc_corr_syndromes_71_64 : 8; 5856 uint32_t reserved_8_15 : 8; 5857 uint32_t cb_corr_syndrome : 8; 5858 uint32_t reserved_24_31 : 8; 5859 } s; 5860 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn2_s cn; */ 5861 }; 5862 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn2 ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn2_t; 5863 5864 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2(uint64_t a) __attribute__ ((pure, always_inline)); 5865 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2(uint64_t a) 5866 { 5867 if (a <= 19) 5868 return 0x87e1b0210624ll + 0x1000000ll * ((a) & 0x1f); 5869 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2", 1, a, 0, 0, 0, 0, 0); 5870 } 5871 5872 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecccsyn2_t 5873 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2(a) CSR_TYPE_RSL32b 5874 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2" 5875 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2(a) 0x0 /* PF_BAR0 */ 5876 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2(a) (a) 5877 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCSYN2(a) (a), -1, -1, -1 5878 5879 /** 5880 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccctl 5881 * 5882 * DSS Ddrctl Regb Ddrc Ch0 Eccctl Register 5883 * ECC Clear Register 5884 */ 5885 union ody_dssx_ddrctl_regb_ddrc_ch0_eccctl { 5886 uint32_t u; 5887 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccctl_s { 5888 uint32_t ecc_corrected_err_clr : 1; 5889 uint32_t ecc_uncorrected_err_clr : 1; 5890 uint32_t ecc_corr_err_cnt_clr : 1; 5891 uint32_t ecc_uncorr_err_cnt_clr : 1; 5892 uint32_t reserved_4_7 : 4; 5893 uint32_t ecc_corrected_err_intr_en : 1; 5894 uint32_t ecc_uncorrected_err_intr_en : 1; 5895 uint32_t reserved_10_15 : 6; 5896 uint32_t ecc_corrected_err_intr_force : 1; 5897 uint32_t ecc_uncorrected_err_intr_force : 1; 5898 uint32_t reserved_18_31 : 14; 5899 } s; 5900 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccctl_s cn; */ 5901 }; 5902 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccctl ody_dssx_ddrctl_regb_ddrc_ch0_eccctl_t; 5903 5904 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL(uint64_t a) __attribute__ ((pure, always_inline)); 5905 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL(uint64_t a) 5906 { 5907 if (a <= 19) 5908 return 0x87e1b021060cll + 0x1000000ll * ((a) & 0x1f); 5909 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL", 1, a, 0, 0, 0, 0, 0); 5910 } 5911 5912 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccctl_t 5913 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL(a) CSR_TYPE_RSL32b 5914 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL" 5915 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL(a) 0x0 /* PF_BAR0 */ 5916 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL(a) (a) 5917 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCCTL(a) (a), -1, -1, -1 5918 5919 /** 5920 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccerrcnt 5921 * 5922 * DSS Ddrctl Regb Ddrc Ch0 Eccerrcnt Register 5923 * ECC Error Counter Register 5924 */ 5925 union ody_dssx_ddrctl_regb_ddrc_ch0_eccerrcnt { 5926 uint32_t u; 5927 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccerrcnt_s { 5928 uint32_t ecc_corr_err_cnt : 16; 5929 uint32_t ecc_uncorr_err_cnt : 16; 5930 } s; 5931 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccerrcnt_s cn; */ 5932 }; 5933 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccerrcnt ody_dssx_ddrctl_regb_ddrc_ch0_eccerrcnt_t; 5934 5935 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT(uint64_t a) __attribute__ ((pure, always_inline)); 5936 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT(uint64_t a) 5937 { 5938 if (a <= 19) 5939 return 0x87e1b0210610ll + 0x1000000ll * ((a) & 0x1f); 5940 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT", 1, a, 0, 0, 0, 0, 0); 5941 } 5942 5943 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccerrcnt_t 5944 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT(a) CSR_TYPE_RSL32b 5945 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT" 5946 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT(a) 0x0 /* PF_BAR0 */ 5947 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT(a) (a) 5948 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCERRCNT(a) (a), -1, -1, -1 5949 5950 /** 5951 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccpoisonaddr0 5952 * 5953 * DSS Ddrctl Regb Ddrc Ch0 Eccpoisonaddr0 Register 5954 * ECC Data Poisoning Address Register 0. 5955 */ 5956 union ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr0 { 5957 uint32_t u; 5958 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr0_s { 5959 uint32_t ecc_poison_col : 12; 5960 uint32_t reserved_12_23 : 12; 5961 uint32_t ecc_poison_rank : 1; 5962 uint32_t reserved_25_31 : 7; 5963 } s; 5964 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr0_s cn; */ 5965 }; 5966 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr0 ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr0_t; 5967 5968 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0(uint64_t a) __attribute__ ((pure, always_inline)); 5969 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0(uint64_t a) 5970 { 5971 if (a <= 19) 5972 return 0x87e1b0210648ll + 0x1000000ll * ((a) & 0x1f); 5973 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0", 1, a, 0, 0, 0, 0, 0); 5974 } 5975 5976 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr0_t 5977 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0(a) CSR_TYPE_RSL32b 5978 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0" 5979 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0(a) 0x0 /* PF_BAR0 */ 5980 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0(a) (a) 5981 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR0(a) (a), -1, -1, -1 5982 5983 /** 5984 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccpoisonaddr1 5985 * 5986 * DSS Ddrctl Regb Ddrc Ch0 Eccpoisonaddr1 Register 5987 * ECC Data Poisoning Address Register 1. 5988 */ 5989 union ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr1 { 5990 uint32_t u; 5991 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr1_s { 5992 uint32_t ecc_poison_row : 18; 5993 uint32_t reserved_18_23 : 6; 5994 uint32_t ecc_poison_bank : 2; 5995 uint32_t reserved_26_27 : 2; 5996 uint32_t ecc_poison_bg : 3; 5997 uint32_t reserved_31 : 1; 5998 } s; 5999 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr1_s cn; */ 6000 }; 6001 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr1 ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr1_t; 6002 6003 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1(uint64_t a) __attribute__ ((pure, always_inline)); 6004 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1(uint64_t a) 6005 { 6006 if (a <= 19) 6007 return 0x87e1b021064cll + 0x1000000ll * ((a) & 0x1f); 6008 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1", 1, a, 0, 0, 0, 0, 0); 6009 } 6010 6011 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonaddr1_t 6012 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1(a) CSR_TYPE_RSL32b 6013 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1" 6014 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1(a) 0x0 /* PF_BAR0 */ 6015 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1(a) (a) 6016 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONADDR1(a) (a), -1, -1, -1 6017 6018 /** 6019 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccpoisonpat0 6020 * 6021 * DSS Ddrctl Regb Ddrc Ch0 Eccpoisonpat0 Register 6022 * ECC Poison Pattern 0 Register 6023 */ 6024 union ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat0 { 6025 uint32_t u; 6026 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat0_s { 6027 uint32_t ecc_poison_data_31_0 : 32; 6028 } s; 6029 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat0_s cn; */ 6030 }; 6031 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat0 ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat0_t; 6032 6033 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0(uint64_t a) __attribute__ ((pure, always_inline)); 6034 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0(uint64_t a) 6035 { 6036 if (a <= 19) 6037 return 0x87e1b0210658ll + 0x1000000ll * ((a) & 0x1f); 6038 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0", 1, a, 0, 0, 0, 0, 0); 6039 } 6040 6041 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat0_t 6042 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0(a) CSR_TYPE_RSL32b 6043 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0" 6044 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0(a) 0x0 /* PF_BAR0 */ 6045 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0(a) (a) 6046 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT0(a) (a), -1, -1, -1 6047 6048 /** 6049 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccpoisonpat2 6050 * 6051 * DSS Ddrctl Regb Ddrc Ch0 Eccpoisonpat2 Register 6052 * ECC Poison Pattern 2 Register 6053 */ 6054 union ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat2 { 6055 uint32_t u; 6056 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat2_s { 6057 uint32_t ecc_poison_data_71_64 : 8; 6058 uint32_t reserved_8_31 : 24; 6059 } s; 6060 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat2_s cn; */ 6061 }; 6062 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat2 ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat2_t; 6063 6064 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2(uint64_t a) __attribute__ ((pure, always_inline)); 6065 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2(uint64_t a) 6066 { 6067 if (a <= 19) 6068 return 0x87e1b0210660ll + 0x1000000ll * ((a) & 0x1f); 6069 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2", 1, a, 0, 0, 0, 0, 0); 6070 } 6071 6072 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccpoisonpat2_t 6073 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2(a) CSR_TYPE_RSL32b 6074 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2" 6075 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2(a) 0x0 /* PF_BAR0 */ 6076 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2(a) (a) 6077 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCPOISONPAT2(a) (a), -1, -1, -1 6078 6079 /** 6080 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccstat 6081 * 6082 * DSS Ddrctl Regb Ddrc Ch0 Eccstat Register 6083 * SECDED ECC Status Register 6084 */ 6085 union ody_dssx_ddrctl_regb_ddrc_ch0_eccstat { 6086 uint32_t u; 6087 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccstat_s { 6088 uint32_t ecc_corrected_bit_num : 7; 6089 uint32_t reserved_7 : 1; 6090 uint32_t ecc_corrected_err : 8; 6091 uint32_t ecc_uncorrected_err : 8; 6092 uint32_t sbr_read_ecc_ce : 1; 6093 uint32_t sbr_read_ecc_ue : 1; 6094 uint32_t reserved_26_31 : 6; 6095 } s; 6096 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccstat_s cn; */ 6097 }; 6098 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccstat ody_dssx_ddrctl_regb_ddrc_ch0_eccstat_t; 6099 6100 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 6101 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT(uint64_t a) 6102 { 6103 if (a <= 19) 6104 return 0x87e1b0210608ll + 0x1000000ll * ((a) & 0x1f); 6105 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT", 1, a, 0, 0, 0, 0, 0); 6106 } 6107 6108 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccstat_t 6109 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT(a) CSR_TYPE_RSL32b 6110 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT" 6111 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT(a) 0x0 /* PF_BAR0 */ 6112 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT(a) (a) 6113 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSTAT(a) (a), -1, -1, -1 6114 6115 /** 6116 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccsymbol 6117 * 6118 * DSS Ddrctl Regb Ddrc Ch0 Eccsymbol Register 6119 * ECC Symbol Register 6120 */ 6121 union ody_dssx_ddrctl_regb_ddrc_ch0_eccsymbol { 6122 uint32_t u; 6123 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccsymbol_s { 6124 uint32_t ecc_corr_sym_71_64 : 8; 6125 uint32_t reserved_8_15 : 8; 6126 uint32_t ecc_uncorr_sym_71_64 : 8; 6127 uint32_t reserved_24_31 : 8; 6128 } s; 6129 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccsymbol_s cn; */ 6130 }; 6131 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccsymbol ody_dssx_ddrctl_regb_ddrc_ch0_eccsymbol_t; 6132 6133 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL(uint64_t a) __attribute__ ((pure, always_inline)); 6134 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL(uint64_t a) 6135 { 6136 if (a <= 19) 6137 return 0x87e1b021067cll + 0x1000000ll * ((a) & 0x1f); 6138 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL", 1, a, 0, 0, 0, 0, 0); 6139 } 6140 6141 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccsymbol_t 6142 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL(a) CSR_TYPE_RSL32b 6143 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL" 6144 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL(a) 0x0 /* PF_BAR0 */ 6145 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL(a) (a) 6146 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCSYMBOL(a) (a), -1, -1, -1 6147 6148 /** 6149 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccuaddr0 6150 * 6151 * DSS Ddrctl Regb Ddrc Ch0 Eccuaddr0 Register 6152 * ECC Uncorrected Error Address Register 0 6153 */ 6154 union ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr0 { 6155 uint32_t u; 6156 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr0_s { 6157 uint32_t ecc_uncorr_row : 18; 6158 uint32_t reserved_18_23 : 6; 6159 uint32_t ecc_uncorr_rank : 1; 6160 uint32_t reserved_25_31 : 7; 6161 } s; 6162 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr0_s cn; */ 6163 }; 6164 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr0 ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr0_t; 6165 6166 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0(uint64_t a) __attribute__ ((pure, always_inline)); 6167 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0(uint64_t a) 6168 { 6169 if (a <= 19) 6170 return 0x87e1b0210634ll + 0x1000000ll * ((a) & 0x1f); 6171 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0", 1, a, 0, 0, 0, 0, 0); 6172 } 6173 6174 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr0_t 6175 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0(a) CSR_TYPE_RSL32b 6176 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0" 6177 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0(a) 0x0 /* PF_BAR0 */ 6178 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0(a) (a) 6179 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR0(a) (a), -1, -1, -1 6180 6181 /** 6182 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccuaddr1 6183 * 6184 * DSS Ddrctl Regb Ddrc Ch0 Eccuaddr1 Register 6185 * ECC Uncorrected Error Address Register 1 6186 */ 6187 union ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr1 { 6188 uint32_t u; 6189 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr1_s { 6190 uint32_t ecc_uncorr_col : 11; 6191 uint32_t reserved_11_15 : 5; 6192 uint32_t ecc_uncorr_bank : 2; 6193 uint32_t reserved_18_23 : 6; 6194 uint32_t ecc_uncorr_bg : 3; 6195 uint32_t reserved_27_31 : 5; 6196 } s; 6197 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr1_s cn; */ 6198 }; 6199 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr1 ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr1_t; 6200 6201 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1(uint64_t a) __attribute__ ((pure, always_inline)); 6202 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1(uint64_t a) 6203 { 6204 if (a <= 19) 6205 return 0x87e1b0210638ll + 0x1000000ll * ((a) & 0x1f); 6206 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1", 1, a, 0, 0, 0, 0, 0); 6207 } 6208 6209 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccuaddr1_t 6210 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1(a) CSR_TYPE_RSL32b 6211 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1" 6212 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1(a) 0x0 /* PF_BAR0 */ 6213 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1(a) (a) 6214 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUADDR1(a) (a), -1, -1, -1 6215 6216 /** 6217 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccudata0 6218 * 6219 * DSS Ddrctl Regb Ddrc Ch0 Eccudata0 Register 6220 * ECC Uncorrected Data Register 0 6221 */ 6222 union ody_dssx_ddrctl_regb_ddrc_ch0_eccudata0 { 6223 uint32_t u; 6224 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccudata0_s { 6225 uint32_t ecc_uncorr_data_31_0 : 32; 6226 } s; 6227 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccudata0_s cn; */ 6228 }; 6229 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccudata0 ody_dssx_ddrctl_regb_ddrc_ch0_eccudata0_t; 6230 6231 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0(uint64_t a) __attribute__ ((pure, always_inline)); 6232 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0(uint64_t a) 6233 { 6234 if (a <= 19) 6235 return 0x87e1b0210674ll + 0x1000000ll * ((a) & 0x1f); 6236 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0", 1, a, 0, 0, 0, 0, 0); 6237 } 6238 6239 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccudata0_t 6240 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0(a) CSR_TYPE_RSL32b 6241 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0" 6242 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0(a) 0x0 /* PF_BAR0 */ 6243 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0(a) (a) 6244 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUDATA0(a) (a), -1, -1, -1 6245 6246 /** 6247 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccusyn0 6248 * 6249 * DSS Ddrctl Regb Ddrc Ch0 Eccusyn0 Register 6250 * ECC Uncorrected Syndrome Register 0 6251 */ 6252 union ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn0 { 6253 uint32_t u; 6254 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn0_s { 6255 uint32_t ecc_uncorr_syndromes_31_0 : 32; 6256 } s; 6257 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn0_s cn; */ 6258 }; 6259 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn0 ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn0_t; 6260 6261 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0(uint64_t a) __attribute__ ((pure, always_inline)); 6262 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0(uint64_t a) 6263 { 6264 if (a <= 19) 6265 return 0x87e1b021063cll + 0x1000000ll * ((a) & 0x1f); 6266 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0", 1, a, 0, 0, 0, 0, 0); 6267 } 6268 6269 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn0_t 6270 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0(a) CSR_TYPE_RSL32b 6271 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0" 6272 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0(a) 0x0 /* PF_BAR0 */ 6273 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0(a) (a) 6274 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN0(a) (a), -1, -1, -1 6275 6276 /** 6277 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccusyn1 6278 * 6279 * DSS Ddrctl Regb Ddrc Ch0 Eccusyn1 Register 6280 * ECC Uncorrected Syndrome Register 1 6281 */ 6282 union ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn1 { 6283 uint32_t u; 6284 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn1_s { 6285 uint32_t ecc_uncorr_syndromes_63_32 : 32; 6286 } s; 6287 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn1_s cn; */ 6288 }; 6289 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn1 ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn1_t; 6290 6291 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1(uint64_t a) __attribute__ ((pure, always_inline)); 6292 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1(uint64_t a) 6293 { 6294 if (a <= 19) 6295 return 0x87e1b0210640ll + 0x1000000ll * ((a) & 0x1f); 6296 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1", 1, a, 0, 0, 0, 0, 0); 6297 } 6298 6299 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn1_t 6300 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1(a) CSR_TYPE_RSL32b 6301 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1" 6302 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1(a) 0x0 /* PF_BAR0 */ 6303 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1(a) (a) 6304 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN1(a) (a), -1, -1, -1 6305 6306 /** 6307 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_eccusyn2 6308 * 6309 * DSS Ddrctl Regb Ddrc Ch0 Eccusyn2 Register 6310 * ECC Uncorrected Syndrome Register 2 6311 */ 6312 union ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn2 { 6313 uint32_t u; 6314 struct ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn2_s { 6315 uint32_t ecc_uncorr_syndromes_71_64 : 8; 6316 uint32_t reserved_8_15 : 8; 6317 uint32_t cb_uncorr_syndrome : 8; 6318 uint32_t reserved_24_31 : 8; 6319 } s; 6320 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn2_s cn; */ 6321 }; 6322 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn2 ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn2_t; 6323 6324 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2(uint64_t a) __attribute__ ((pure, always_inline)); 6325 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2(uint64_t a) 6326 { 6327 if (a <= 19) 6328 return 0x87e1b0210644ll + 0x1000000ll * ((a) & 0x1f); 6329 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2", 1, a, 0, 0, 0, 0, 0); 6330 } 6331 6332 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2(a) ody_dssx_ddrctl_regb_ddrc_ch0_eccusyn2_t 6333 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2(a) CSR_TYPE_RSL32b 6334 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2" 6335 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2(a) 0x0 /* PF_BAR0 */ 6336 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2(a) (a) 6337 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECCUSYN2(a) (a), -1, -1, -1 6338 6339 /** 6340 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecs_stat_dev_sel 6341 * 6342 * DSS Ddrctl Regb Ddrc Ch0 Ecs Stat Dev Sel Register 6343 * ECS Transparency MRR Control Register 6344 */ 6345 union ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_dev_sel { 6346 uint32_t u; 6347 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_dev_sel_s { 6348 uint32_t target_ecs_mrr_device_idx : 5; 6349 uint32_t reserved_5_31 : 27; 6350 } s; 6351 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_dev_sel_s cn; */ 6352 }; 6353 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_dev_sel ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_dev_sel_t; 6354 6355 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL(uint64_t a) __attribute__ ((pure, always_inline)); 6356 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL(uint64_t a) 6357 { 6358 if (a <= 19) 6359 return 0x87e1b0210af4ll + 0x1000000ll * ((a) & 0x1f); 6360 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL", 1, a, 0, 0, 0, 0, 0); 6361 } 6362 6363 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_dev_sel_t 6364 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL(a) CSR_TYPE_RSL32b 6365 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL" 6366 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL(a) 0x0 /* PF_BAR0 */ 6367 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL(a) (a) 6368 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_DEV_SEL(a) (a), -1, -1, -1 6369 6370 /** 6371 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecs_stat_mr0 6372 * 6373 * DSS Ddrctl Regb Ddrc Ch0 Ecs Stat Mr0 Register 6374 * ECS Transparency MRR Data Register 6375 */ 6376 union ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr0 { 6377 uint32_t u; 6378 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr0_s { 6379 uint32_t ecs_mr16 : 8; 6380 uint32_t ecs_mr17 : 8; 6381 uint32_t ecs_mr18 : 8; 6382 uint32_t ecs_mr19 : 8; 6383 } s; 6384 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr0_s cn; */ 6385 }; 6386 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr0 ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr0_t; 6387 6388 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0(uint64_t a) __attribute__ ((pure, always_inline)); 6389 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0(uint64_t a) 6390 { 6391 if (a <= 19) 6392 return 0x87e1b0210af8ll + 0x1000000ll * ((a) & 0x1f); 6393 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0", 1, a, 0, 0, 0, 0, 0); 6394 } 6395 6396 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr0_t 6397 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0(a) CSR_TYPE_RSL32b 6398 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0" 6399 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0(a) 0x0 /* PF_BAR0 */ 6400 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0(a) (a) 6401 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR0(a) (a), -1, -1, -1 6402 6403 /** 6404 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecs_stat_mr1 6405 * 6406 * DSS Ddrctl Regb Ddrc Ch0 Ecs Stat Mr1 Register 6407 * ECS Transparency MRR Data Register 6408 */ 6409 union ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr1 { 6410 uint32_t u; 6411 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr1_s { 6412 uint32_t ecs_mr20 : 8; 6413 uint32_t reserved_8_31 : 24; 6414 } s; 6415 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr1_s cn; */ 6416 }; 6417 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr1 ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr1_t; 6418 6419 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1(uint64_t a) __attribute__ ((pure, always_inline)); 6420 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1(uint64_t a) 6421 { 6422 if (a <= 19) 6423 return 0x87e1b0210afcll + 0x1000000ll * ((a) & 0x1f); 6424 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1", 1, a, 0, 0, 0, 0, 0); 6425 } 6426 6427 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecs_stat_mr1_t 6428 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1(a) CSR_TYPE_RSL32b 6429 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1" 6430 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1(a) 0x0 /* PF_BAR0 */ 6431 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1(a) (a) 6432 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECS_STAT_MR1(a) (a), -1, -1, -1 6433 6434 /** 6435 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_ecsctl 6436 * 6437 * DSS Ddrctl Regb Ddrc Ch0 Ecsctl Register 6438 * ECS Control Register 6439 */ 6440 union ody_dssx_ddrctl_regb_ddrc_ch0_ecsctl { 6441 uint32_t u; 6442 struct ody_dssx_ddrctl_regb_ddrc_ch0_ecsctl_s { 6443 uint32_t auto_ecs_refab_en : 2; 6444 uint32_t reserved_2_31 : 30; 6445 } s; 6446 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_ecsctl_s cn; */ 6447 }; 6448 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_ecsctl ody_dssx_ddrctl_regb_ddrc_ch0_ecsctl_t; 6449 6450 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL(uint64_t a) __attribute__ ((pure, always_inline)); 6451 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL(uint64_t a) 6452 { 6453 if (a <= 19) 6454 return 0x87e1b0210af0ll + 0x1000000ll * ((a) & 0x1f); 6455 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL", 1, a, 0, 0, 0, 0, 0); 6456 } 6457 6458 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_ecsctl_t 6459 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL(a) CSR_TYPE_RSL32b 6460 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL" 6461 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL(a) 0x0 /* PF_BAR0 */ 6462 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL(a) (a) 6463 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ECSCTL(a) (a), -1, -1, -1 6464 6465 /** 6466 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_hwlpctl 6467 * 6468 * DSS Ddrctl Regb Ddrc Ch0 Hwlpctl Register 6469 * Hardware Low Power Control Register 6470 */ 6471 union ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl { 6472 uint32_t u; 6473 struct ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl_s { 6474 uint32_t hw_lp_en : 1; 6475 uint32_t hw_lp_exit_idle_en : 1; 6476 uint32_t hw_lp_ctrl : 1; 6477 uint32_t reserved_3_31 : 29; 6478 } s; 6479 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl_s cn; */ 6480 }; 6481 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl_t; 6482 6483 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL(uint64_t a) __attribute__ ((pure, always_inline)); 6484 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL(uint64_t a) 6485 { 6486 if (a <= 19) 6487 return 0x87e1b0210184ll + 0x1000000ll * ((a) & 0x1f); 6488 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL", 1, a, 0, 0, 0, 0, 0); 6489 } 6490 6491 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl_t 6492 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL(a) CSR_TYPE_RSL32b 6493 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL" 6494 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL(a) 0x0 /* PF_BAR0 */ 6495 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL(a) (a) 6496 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL(a) (a), -1, -1, -1 6497 6498 /** 6499 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_hwlpctl2 6500 * 6501 * DSS Ddrctl Regb Ddrc Ch0 Hwlpctl2 Register 6502 * Hardware Low Power Control Register 2 6503 */ 6504 union ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl2 { 6505 uint32_t u; 6506 struct ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl2_s { 6507 uint32_t cactive_in_mask : 2; 6508 uint32_t reserved_2_31 : 30; 6509 } s; 6510 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl2_s cn; */ 6511 }; 6512 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl2 ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl2_t; 6513 6514 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2(uint64_t a) __attribute__ ((pure, always_inline)); 6515 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2(uint64_t a) 6516 { 6517 if (a <= 19) 6518 return 0x87e1b0210188ll + 0x1000000ll * ((a) & 0x1f); 6519 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2", 1, a, 0, 0, 0, 0, 0); 6520 } 6521 6522 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2(a) ody_dssx_ddrctl_regb_ddrc_ch0_hwlpctl2_t 6523 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2(a) CSR_TYPE_RSL32b 6524 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2" 6525 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2(a) 0x0 /* PF_BAR0 */ 6526 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2(a) (a) 6527 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_HWLPCTL2(a) (a), -1, -1, -1 6528 6529 /** 6530 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_inittmg0 6531 * 6532 * DSS Ddrctl Regb Ddrc Ch0 Inittmg0 Register 6533 * SDRAM Initialization Timing Register 0 6534 */ 6535 union ody_dssx_ddrctl_regb_ddrc_ch0_inittmg0 { 6536 uint32_t u; 6537 struct ody_dssx_ddrctl_regb_ddrc_ch0_inittmg0_s { 6538 uint32_t reserved_0_29 : 30; 6539 uint32_t skip_dram_init : 2; 6540 } s; 6541 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_inittmg0_s cn; */ 6542 }; 6543 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_inittmg0 ody_dssx_ddrctl_regb_ddrc_ch0_inittmg0_t; 6544 6545 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0(uint64_t a) __attribute__ ((pure, always_inline)); 6546 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0(uint64_t a) 6547 { 6548 if (a <= 19) 6549 return 0x87e1b0210d00ll + 0x1000000ll * ((a) & 0x1f); 6550 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0", 1, a, 0, 0, 0, 0, 0); 6551 } 6552 6553 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0(a) ody_dssx_ddrctl_regb_ddrc_ch0_inittmg0_t 6554 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0(a) CSR_TYPE_RSL32b 6555 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0" 6556 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0(a) 0x0 /* PF_BAR0 */ 6557 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0(a) (a) 6558 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_INITTMG0(a) (a), -1, -1, -1 6559 6560 /** 6561 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_lc_dbg_stat0 6562 * 6563 * DSS Ddrctl Regb Ddrc Ch0 Lc Dbg Stat0 Register 6564 * PASLC DEBUG STAT0 Register 6565 */ 6566 union ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat0 { 6567 uint32_t u; 6568 struct ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat0_s { 6569 uint32_t dbg_rank_ctrl_mc_addr_0 : 8; 6570 uint32_t reserved_8_15 : 8; 6571 uint32_t dbg_rank_ctrl_mc_code_0 : 16; 6572 } s; 6573 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat0_s cn; */ 6574 }; 6575 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat0 ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat0_t; 6576 6577 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0(uint64_t a) __attribute__ ((pure, always_inline)); 6578 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0(uint64_t a) 6579 { 6580 if (a <= 19) 6581 return 0x87e1b0210d9cll + 0x1000000ll * ((a) & 0x1f); 6582 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0", 1, a, 0, 0, 0, 0, 0); 6583 } 6584 6585 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat0_t 6586 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0(a) CSR_TYPE_RSL32b 6587 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0" 6588 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0(a) 0x0 /* PF_BAR0 */ 6589 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0(a) (a) 6590 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT0(a) (a), -1, -1, -1 6591 6592 /** 6593 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_lc_dbg_stat1 6594 * 6595 * DSS Ddrctl Regb Ddrc Ch0 Lc Dbg Stat1 Register 6596 * PASLC DEBUG STAT1 Register 6597 */ 6598 union ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat1 { 6599 uint32_t u; 6600 struct ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat1_s { 6601 uint32_t dbg_rank_ctrl_mc_addr_1 : 8; 6602 uint32_t reserved_8_15 : 8; 6603 uint32_t dbg_rank_ctrl_mc_code_1 : 16; 6604 } s; 6605 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat1_s cn; */ 6606 }; 6607 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat1 ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat1_t; 6608 6609 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1(uint64_t a) __attribute__ ((pure, always_inline)); 6610 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1(uint64_t a) 6611 { 6612 if (a <= 19) 6613 return 0x87e1b0210da0ll + 0x1000000ll * ((a) & 0x1f); 6614 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1", 1, a, 0, 0, 0, 0, 0); 6615 } 6616 6617 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1(a) ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat1_t 6618 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1(a) CSR_TYPE_RSL32b 6619 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1" 6620 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1(a) 0x0 /* PF_BAR0 */ 6621 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1(a) (a) 6622 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT1(a) (a), -1, -1, -1 6623 6624 /** 6625 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_lc_dbg_stat4 6626 * 6627 * DSS Ddrctl Regb Ddrc Ch0 Lc Dbg Stat4 Register 6628 * PASLC DEBUG STAT4 Register 6629 */ 6630 union ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat4 { 6631 uint32_t u; 6632 struct ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat4_s { 6633 uint32_t dbg_sceu_ctrl_state_sceu_0 : 3; 6634 uint32_t reserved_3 : 1; 6635 uint32_t dbg_mceu_ctrl_state_mceu_0 : 3; 6636 uint32_t reserved_7 : 1; 6637 uint32_t dbg_rank_ctrl_state_rsm_0 : 4; 6638 uint32_t reserved_12_15 : 4; 6639 uint32_t dbg_sceu_ctrl_state_sceu_1 : 3; 6640 uint32_t reserved_19 : 1; 6641 uint32_t dbg_mceu_ctrl_state_mceu_1 : 3; 6642 uint32_t reserved_23 : 1; 6643 uint32_t dbg_rank_ctrl_state_rsm_1 : 4; 6644 uint32_t reserved_28_31 : 4; 6645 } s; 6646 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat4_s cn; */ 6647 }; 6648 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat4 ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat4_t; 6649 6650 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4(uint64_t a) __attribute__ ((pure, always_inline)); 6651 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4(uint64_t a) 6652 { 6653 if (a <= 19) 6654 return 0x87e1b0210dacll + 0x1000000ll * ((a) & 0x1f); 6655 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4", 1, a, 0, 0, 0, 0, 0); 6656 } 6657 6658 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4(a) ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat4_t 6659 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4(a) CSR_TYPE_RSL32b 6660 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4(a) "DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4" 6661 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4(a) 0x0 /* PF_BAR0 */ 6662 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4(a) (a) 6663 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT4(a) (a), -1, -1, -1 6664 6665 /** 6666 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_lc_dbg_stat6 6667 * 6668 * DSS Ddrctl Regb Ddrc Ch0 Lc Dbg Stat6 Register 6669 * PASLC DEBUG STAT6 Register 6670 */ 6671 union ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat6 { 6672 uint32_t u; 6673 struct ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat6_s { 6674 uint32_t dbg_dfi_lp_state_dsm : 3; 6675 uint32_t reserved_3 : 1; 6676 uint32_t dbg_dfi_lp_data_ack : 1; 6677 uint32_t dbg_dfi_lp_ctrl_ack : 1; 6678 uint32_t reserved_6_7 : 2; 6679 uint32_t dbg_hw_lp_state_hsm : 3; 6680 uint32_t reserved_11_31 : 21; 6681 } s; 6682 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat6_s cn; */ 6683 }; 6684 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat6 ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat6_t; 6685 6686 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6(uint64_t a) __attribute__ ((pure, always_inline)); 6687 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6(uint64_t a) 6688 { 6689 if (a <= 19) 6690 return 0x87e1b0210db4ll + 0x1000000ll * ((a) & 0x1f); 6691 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6", 1, a, 0, 0, 0, 0, 0); 6692 } 6693 6694 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6(a) ody_dssx_ddrctl_regb_ddrc_ch0_lc_dbg_stat6_t 6695 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6(a) CSR_TYPE_RSL32b 6696 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6(a) "DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6" 6697 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6(a) 0x0 /* PF_BAR0 */ 6698 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6(a) (a) 6699 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LC_DBG_STAT6(a) (a), -1, -1, -1 6700 6701 /** 6702 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_lp_cmdbuf_ctrl 6703 * 6704 * DSS Ddrctl Regb Ddrc Ch0 Lp Cmdbuf Ctrl Register 6705 * Low Power Control command buffer control register 6706 */ 6707 union ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_ctrl { 6708 uint32_t u; 6709 struct ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_ctrl_s { 6710 uint32_t lp_cmdbuf_wdata : 16; 6711 uint32_t lp_cmdbuf_addr : 8; 6712 uint32_t reserved_24_28 : 5; 6713 uint32_t lp_cmdbuf_op_mode : 1; 6714 uint32_t lp_cmdbuf_rw_type : 1; 6715 uint32_t lp_cmdbuf_rw_start : 1; 6716 } s; 6717 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_ctrl_s cn; */ 6718 }; 6719 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_ctrl ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_ctrl_t; 6720 6721 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 6722 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL(uint64_t a) 6723 { 6724 if (a <= 19) 6725 return 0x87e1b0210b34ll + 0x1000000ll * ((a) & 0x1f); 6726 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL", 1, a, 0, 0, 0, 0, 0); 6727 } 6728 6729 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL(a) ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_ctrl_t 6730 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL(a) CSR_TYPE_RSL32b 6731 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL" 6732 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL(a) 0x0 /* PF_BAR0 */ 6733 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL(a) (a) 6734 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_CTRL(a) (a), -1, -1, -1 6735 6736 /** 6737 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_lp_cmdbuf_stat 6738 * 6739 * DSS Ddrctl Regb Ddrc Ch0 Lp Cmdbuf Stat Register 6740 * Low Power Control command buffer status register. 6741 */ 6742 union ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_stat { 6743 uint32_t u; 6744 struct ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_stat_s { 6745 uint32_t lp_cmdbuf_rdata : 16; 6746 uint32_t reserved_16_31 : 16; 6747 } s; 6748 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_stat_s cn; */ 6749 }; 6750 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_stat ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_stat_t; 6751 6752 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT(uint64_t a) __attribute__ ((pure, always_inline)); 6753 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT(uint64_t a) 6754 { 6755 if (a <= 19) 6756 return 0x87e1b0210b38ll + 0x1000000ll * ((a) & 0x1f); 6757 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT", 1, a, 0, 0, 0, 0, 0); 6758 } 6759 6760 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_lp_cmdbuf_stat_t 6761 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT(a) CSR_TYPE_RSL32b 6762 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT" 6763 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT(a) 0x0 /* PF_BAR0 */ 6764 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT(a) (a) 6765 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_LP_CMDBUF_STAT(a) (a), -1, -1, -1 6766 6767 /** 6768 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_mstr0 6769 * 6770 * DSS Ddrctl Regb Ddrc Ch0 Mstr0 Register 6771 * Master Register0 6772 */ 6773 union ody_dssx_ddrctl_regb_ddrc_ch0_mstr0 { 6774 uint32_t u; 6775 struct ody_dssx_ddrctl_regb_ddrc_ch0_mstr0_s { 6776 uint32_t ddr4 : 1; 6777 uint32_t reserved_1 : 1; 6778 uint32_t ddr5 : 1; 6779 uint32_t reserved_3 : 1; 6780 uint32_t bank_config : 2; 6781 uint32_t bg_config : 2; 6782 uint32_t burst_mode : 1; 6783 uint32_t burstchop : 1; 6784 uint32_t en_2t_timing_mode : 1; 6785 uint32_t reserved_11 : 1; 6786 uint32_t data_bus_width : 2; 6787 uint32_t reserved_14_15 : 2; 6788 uint32_t burst_rdwr : 5; 6789 uint32_t reserved_21_23 : 3; 6790 uint32_t active_ranks : 2; 6791 uint32_t reserved_26_29 : 4; 6792 uint32_t device_config : 2; 6793 } s; 6794 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_mstr0_s cn; */ 6795 }; 6796 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_mstr0 ody_dssx_ddrctl_regb_ddrc_ch0_mstr0_t; 6797 6798 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0(uint64_t a) __attribute__ ((pure, always_inline)); 6799 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0(uint64_t a) 6800 { 6801 if (a <= 19) 6802 return 0x87e1b0210000ll + 0x1000000ll * ((a) & 0x1f); 6803 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0", 1, a, 0, 0, 0, 0, 0); 6804 } 6805 6806 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0(a) ody_dssx_ddrctl_regb_ddrc_ch0_mstr0_t 6807 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0(a) CSR_TYPE_RSL32b 6808 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0" 6809 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0(a) 0x0 /* PF_BAR0 */ 6810 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0(a) (a) 6811 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_MSTR0(a) (a), -1, -1, -1 6812 6813 /** 6814 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_odtmap 6815 * 6816 * DSS Ddrctl Regb Ddrc Ch0 Odtmap Register 6817 * ODT/Rank Map Register 6818 */ 6819 union ody_dssx_ddrctl_regb_ddrc_ch0_odtmap { 6820 uint32_t u; 6821 struct ody_dssx_ddrctl_regb_ddrc_ch0_odtmap_s { 6822 uint32_t rank0_wr_odt : 2; 6823 uint32_t reserved_2_3 : 2; 6824 uint32_t rank0_rd_odt : 2; 6825 uint32_t reserved_6_7 : 2; 6826 uint32_t rank1_wr_odt : 2; 6827 uint32_t reserved_10_11 : 2; 6828 uint32_t rank1_rd_odt : 2; 6829 uint32_t reserved_14_31 : 18; 6830 } s; 6831 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_odtmap_s cn; */ 6832 }; 6833 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_odtmap ody_dssx_ddrctl_regb_ddrc_ch0_odtmap_t; 6834 6835 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP(uint64_t a) __attribute__ ((pure, always_inline)); 6836 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP(uint64_t a) 6837 { 6838 if (a <= 19) 6839 return 0x87e1b0210c9cll + 0x1000000ll * ((a) & 0x1f); 6840 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP", 1, a, 0, 0, 0, 0, 0); 6841 } 6842 6843 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP(a) ody_dssx_ddrctl_regb_ddrc_ch0_odtmap_t 6844 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP(a) CSR_TYPE_RSL32b 6845 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP" 6846 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP(a) 0x0 /* PF_BAR0 */ 6847 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP(a) (a) 6848 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ODTMAP(a) (a), -1, -1, -1 6849 6850 /** 6851 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_opctrl0 6852 * 6853 * DSS Ddrctl Regb Ddrc Ch0 Opctrl0 Register 6854 * Operation Control Register 0 6855 */ 6856 union ody_dssx_ddrctl_regb_ddrc_ch0_opctrl0 { 6857 uint32_t u; 6858 struct ody_dssx_ddrctl_regb_ddrc_ch0_opctrl0_s { 6859 uint32_t dis_wc : 1; 6860 uint32_t reserved_1_31 : 31; 6861 } s; 6862 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_opctrl0_s cn; */ 6863 }; 6864 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_opctrl0 ody_dssx_ddrctl_regb_ddrc_ch0_opctrl0_t; 6865 6866 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0(uint64_t a) __attribute__ ((pure, always_inline)); 6867 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0(uint64_t a) 6868 { 6869 if (a <= 19) 6870 return 0x87e1b0210b80ll + 0x1000000ll * ((a) & 0x1f); 6871 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0", 1, a, 0, 0, 0, 0, 0); 6872 } 6873 6874 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0(a) ody_dssx_ddrctl_regb_ddrc_ch0_opctrl0_t 6875 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0(a) CSR_TYPE_RSL32b 6876 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0" 6877 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0(a) 0x0 /* PF_BAR0 */ 6878 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0(a) (a) 6879 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL0(a) (a), -1, -1, -1 6880 6881 /** 6882 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_opctrl1 6883 * 6884 * DSS Ddrctl Regb Ddrc Ch0 Opctrl1 Register 6885 * Operation Control Register 1 6886 */ 6887 union ody_dssx_ddrctl_regb_ddrc_ch0_opctrl1 { 6888 uint32_t u; 6889 struct ody_dssx_ddrctl_regb_ddrc_ch0_opctrl1_s { 6890 uint32_t reserved_0 : 1; 6891 uint32_t dis_hif : 1; 6892 uint32_t reserved_2_31 : 30; 6893 } s; 6894 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_opctrl1_s cn; */ 6895 }; 6896 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_opctrl1 ody_dssx_ddrctl_regb_ddrc_ch0_opctrl1_t; 6897 6898 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1(uint64_t a) __attribute__ ((pure, always_inline)); 6899 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1(uint64_t a) 6900 { 6901 if (a <= 19) 6902 return 0x87e1b0210b84ll + 0x1000000ll * ((a) & 0x1f); 6903 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1", 1, a, 0, 0, 0, 0, 0); 6904 } 6905 6906 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1(a) ody_dssx_ddrctl_regb_ddrc_ch0_opctrl1_t 6907 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1(a) CSR_TYPE_RSL32b 6908 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1" 6909 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1(a) 0x0 /* PF_BAR0 */ 6910 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1(a) (a) 6911 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRL1(a) (a), -1, -1, -1 6912 6913 /** 6914 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_opctrlcam 6915 * 6916 * DSS Ddrctl Regb Ddrc Ch0 Opctrlcam Register 6917 * CAM Operation Control Register 6918 */ 6919 union ody_dssx_ddrctl_regb_ddrc_ch0_opctrlcam { 6920 uint32_t u; 6921 struct ody_dssx_ddrctl_regb_ddrc_ch0_opctrlcam_s { 6922 uint32_t dbg_hpr_q_depth : 7; 6923 uint32_t reserved_7 : 1; 6924 uint32_t dbg_lpr_q_depth : 7; 6925 uint32_t reserved_15 : 1; 6926 uint32_t dbg_w_q_depth : 7; 6927 uint32_t reserved_23 : 1; 6928 uint32_t dbg_stall : 1; 6929 uint32_t dbg_rd_q_empty : 1; 6930 uint32_t dbg_wr_q_empty : 1; 6931 uint32_t reserved_27 : 1; 6932 uint32_t rd_data_pipeline_empty : 1; 6933 uint32_t wr_data_pipeline_empty : 1; 6934 uint32_t reserved_30_31 : 2; 6935 } s; 6936 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_opctrlcam_s cn; */ 6937 }; 6938 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_opctrlcam ody_dssx_ddrctl_regb_ddrc_ch0_opctrlcam_t; 6939 6940 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM(uint64_t a) __attribute__ ((pure, always_inline)); 6941 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM(uint64_t a) 6942 { 6943 if (a <= 19) 6944 return 0x87e1b0210b88ll + 0x1000000ll * ((a) & 0x1f); 6945 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM", 1, a, 0, 0, 0, 0, 0); 6946 } 6947 6948 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM(a) ody_dssx_ddrctl_regb_ddrc_ch0_opctrlcam_t 6949 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM(a) CSR_TYPE_RSL32b 6950 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM(a) "DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM" 6951 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM(a) 0x0 /* PF_BAR0 */ 6952 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM(a) (a) 6953 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPCTRLCAM(a) (a), -1, -1, -1 6954 6955 /** 6956 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_oprefctrl0 6957 * 6958 * DSS Ddrctl Regb Ddrc Ch0 Oprefctrl0 Register 6959 * Refresh Operation Control Register 0 6960 */ 6961 union ody_dssx_ddrctl_regb_ddrc_ch0_oprefctrl0 { 6962 uint32_t u; 6963 struct ody_dssx_ddrctl_regb_ddrc_ch0_oprefctrl0_s { 6964 uint32_t rank0_refresh : 1; 6965 uint32_t rank1_refresh : 1; 6966 uint32_t reserved_2_31 : 30; 6967 } s; 6968 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_oprefctrl0_s cn; */ 6969 }; 6970 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_oprefctrl0 ody_dssx_ddrctl_regb_ddrc_ch0_oprefctrl0_t; 6971 6972 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0(uint64_t a) __attribute__ ((pure, always_inline)); 6973 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0(uint64_t a) 6974 { 6975 if (a <= 19) 6976 return 0x87e1b0210b98ll + 0x1000000ll * ((a) & 0x1f); 6977 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0", 1, a, 0, 0, 0, 0, 0); 6978 } 6979 6980 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0(a) ody_dssx_ddrctl_regb_ddrc_ch0_oprefctrl0_t 6981 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0(a) CSR_TYPE_RSL32b 6982 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0" 6983 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0(a) 0x0 /* PF_BAR0 */ 6984 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0(a) (a) 6985 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFCTRL0(a) (a), -1, -1, -1 6986 6987 /** 6988 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_oprefstat0 6989 * 6990 * DSS Ddrctl Regb Ddrc Ch0 Oprefstat0 Register 6991 * Refresh Operation Status Register 0 6992 */ 6993 union ody_dssx_ddrctl_regb_ddrc_ch0_oprefstat0 { 6994 uint32_t u; 6995 struct ody_dssx_ddrctl_regb_ddrc_ch0_oprefstat0_s { 6996 uint32_t rank0_refresh_busy : 1; 6997 uint32_t rank1_refresh_busy : 1; 6998 uint32_t reserved_2_31 : 30; 6999 } s; 7000 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_oprefstat0_s cn; */ 7001 }; 7002 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_oprefstat0 ody_dssx_ddrctl_regb_ddrc_ch0_oprefstat0_t; 7003 7004 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0(uint64_t a) __attribute__ ((pure, always_inline)); 7005 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0(uint64_t a) 7006 { 7007 if (a <= 19) 7008 return 0x87e1b0210ba0ll + 0x1000000ll * ((a) & 0x1f); 7009 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0", 1, a, 0, 0, 0, 0, 0); 7010 } 7011 7012 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_oprefstat0_t 7013 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0(a) CSR_TYPE_RSL32b 7014 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0" 7015 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0(a) 0x0 /* PF_BAR0 */ 7016 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0(a) (a) 7017 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_OPREFSTAT0(a) (a), -1, -1, -1 7018 7019 /** 7020 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl0 7021 * 7022 * DSS Ddrctl Regb Ddrc Ch0 Pasctl0 Register 7023 * Phase Aware Schedule Control Register 0 7024 */ 7025 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl0 { 7026 uint32_t u; 7027 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl0_s { 7028 uint32_t init_done : 1; 7029 uint32_t dbg_st_en : 1; 7030 uint32_t bist_st_en : 1; 7031 uint32_t reserved_3_31 : 29; 7032 } s; 7033 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl0_s cn; */ 7034 }; 7035 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl0 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl0_t; 7036 7037 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0(uint64_t a) __attribute__ ((pure, always_inline)); 7038 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0(uint64_t a) 7039 { 7040 if (a <= 19) 7041 return 0x87e1b0210a00ll + 0x1000000ll * ((a) & 0x1f); 7042 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0", 1, a, 0, 0, 0, 0, 0); 7043 } 7044 7045 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl0_t 7046 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0(a) CSR_TYPE_RSL32b 7047 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0" 7048 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0(a) 0x0 /* PF_BAR0 */ 7049 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0(a) (a) 7050 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL0(a) (a), -1, -1, -1 7051 7052 /** 7053 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl1 7054 * 7055 * DSS Ddrctl Regb Ddrc Ch0 Pasctl1 Register 7056 * Phase Aware Schedule Control Register 1 7057 */ 7058 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl1 { 7059 uint32_t u; 7060 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl1_s { 7061 uint32_t pre_sb_enable : 1; 7062 uint32_t pre_ab_enable : 1; 7063 uint32_t pre_slot_config : 2; 7064 uint32_t reserved_4_11 : 8; 7065 uint32_t rank_switch_gap_unit_sel : 1; 7066 uint32_t mrr_des_timing_unit_sel : 2; 7067 uint32_t reserved_15_17 : 3; 7068 uint32_t selfref_wo_ref_pending : 1; 7069 uint32_t dfi_alert_assertion_mode : 1; 7070 uint32_t speculative_ref_pri_sel : 1; 7071 uint32_t dyn_pre_pri_dis : 1; 7072 uint32_t fixed_pre_pri_sel : 1; 7073 uint32_t reserved_23 : 1; 7074 uint32_t act2rda_cnt_mask : 1; 7075 uint32_t reserved_25_31 : 7; 7076 } s; 7077 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl1_s cn; */ 7078 }; 7079 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl1 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl1_t; 7080 7081 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1(uint64_t a) __attribute__ ((pure, always_inline)); 7082 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1(uint64_t a) 7083 { 7084 if (a <= 19) 7085 return 0x87e1b0210a04ll + 0x1000000ll * ((a) & 0x1f); 7086 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1", 1, a, 0, 0, 0, 0, 0); 7087 } 7088 7089 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl1_t 7090 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1(a) CSR_TYPE_RSL32b 7091 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1" 7092 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1(a) 0x0 /* PF_BAR0 */ 7093 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1(a) (a) 7094 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL1(a) (a), -1, -1, -1 7095 7096 /** 7097 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl10 7098 * 7099 * DSS Ddrctl Regb Ddrc Ch0 Pasctl10 Register 7100 * Phase Aware Schedule Control Register 10 7101 */ 7102 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl10 { 7103 uint32_t u; 7104 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl10_s { 7105 uint32_t rank_blk0_trig : 1; 7106 uint32_t rank_blk1_trig : 1; 7107 uint32_t rank_blk2_trig : 1; 7108 uint32_t rank_blk3_trig : 1; 7109 uint32_t rank_blk4_trig : 1; 7110 uint32_t rank_blk5_trig : 1; 7111 uint32_t rank_blk6_trig : 1; 7112 uint32_t rank_blk7_trig : 1; 7113 uint32_t rank_blk8_trig : 1; 7114 uint32_t rank_blk9_trig : 1; 7115 uint32_t rank_blk10_trig : 1; 7116 uint32_t rank_blk11_trig : 1; 7117 uint32_t rank_blk12_trig : 1; 7118 uint32_t rank_blk13_trig : 1; 7119 uint32_t rank_blk14_trig : 1; 7120 uint32_t rank_blk15_trig : 1; 7121 uint32_t reserved_16_31 : 16; 7122 } s; 7123 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl10_s cn; */ 7124 }; 7125 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl10 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl10_t; 7126 7127 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10(uint64_t a) __attribute__ ((pure, always_inline)); 7128 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10(uint64_t a) 7129 { 7130 if (a <= 19) 7131 return 0x87e1b0210a28ll + 0x1000000ll * ((a) & 0x1f); 7132 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10", 1, a, 0, 0, 0, 0, 0); 7133 } 7134 7135 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl10_t 7136 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10(a) CSR_TYPE_RSL32b 7137 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10" 7138 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10(a) 0x0 /* PF_BAR0 */ 7139 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10(a) (a) 7140 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL10(a) (a), -1, -1, -1 7141 7142 /** 7143 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl11 7144 * 7145 * DSS Ddrctl Regb Ddrc Ch0 Pasctl11 Register 7146 * Phase Aware Schedule Control Register 11 7147 */ 7148 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl11 { 7149 uint32_t u; 7150 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl11_s { 7151 uint32_t powerdown_entry_ba_0 : 8; 7152 uint32_t reserved_8_15 : 8; 7153 uint32_t powerdown_entry_size_0 : 8; 7154 uint32_t reserved_24_31 : 8; 7155 } s; 7156 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl11_s cn; */ 7157 }; 7158 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl11 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl11_t; 7159 7160 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11(uint64_t a) __attribute__ ((pure, always_inline)); 7161 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11(uint64_t a) 7162 { 7163 if (a <= 19) 7164 return 0x87e1b0210a2cll + 0x1000000ll * ((a) & 0x1f); 7165 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11", 1, a, 0, 0, 0, 0, 0); 7166 } 7167 7168 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl11_t 7169 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11(a) CSR_TYPE_RSL32b 7170 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11" 7171 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11(a) 0x0 /* PF_BAR0 */ 7172 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11(a) (a) 7173 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL11(a) (a), -1, -1, -1 7174 7175 /** 7176 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl12 7177 * 7178 * DSS Ddrctl Regb Ddrc Ch0 Pasctl12 Register 7179 * Phase Aware Schedule Control Register 12 7180 */ 7181 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl12 { 7182 uint32_t u; 7183 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl12_s { 7184 uint32_t powerdown_exit_ba_0 : 8; 7185 uint32_t reserved_8_15 : 8; 7186 uint32_t powerdown_exit_size_0 : 8; 7187 uint32_t reserved_24_31 : 8; 7188 } s; 7189 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl12_s cn; */ 7190 }; 7191 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl12 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl12_t; 7192 7193 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12(uint64_t a) __attribute__ ((pure, always_inline)); 7194 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12(uint64_t a) 7195 { 7196 if (a <= 19) 7197 return 0x87e1b0210a30ll + 0x1000000ll * ((a) & 0x1f); 7198 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12", 1, a, 0, 0, 0, 0, 0); 7199 } 7200 7201 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl12_t 7202 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12(a) CSR_TYPE_RSL32b 7203 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12" 7204 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12(a) 0x0 /* PF_BAR0 */ 7205 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12(a) (a) 7206 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL12(a) (a), -1, -1, -1 7207 7208 /** 7209 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl13 7210 * 7211 * DSS Ddrctl Regb Ddrc Ch0 Pasctl13 Register 7212 * Phase Aware Schedule Control Register 13 7213 */ 7214 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl13 { 7215 uint32_t u; 7216 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl13_s { 7217 uint32_t powerdown_entry_ba_1 : 8; 7218 uint32_t reserved_8_15 : 8; 7219 uint32_t powerdown_entry_size_1 : 8; 7220 uint32_t reserved_24_31 : 8; 7221 } s; 7222 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl13_s cn; */ 7223 }; 7224 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl13 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl13_t; 7225 7226 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13(uint64_t a) __attribute__ ((pure, always_inline)); 7227 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13(uint64_t a) 7228 { 7229 if (a <= 19) 7230 return 0x87e1b0210a34ll + 0x1000000ll * ((a) & 0x1f); 7231 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13", 1, a, 0, 0, 0, 0, 0); 7232 } 7233 7234 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl13_t 7235 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13(a) CSR_TYPE_RSL32b 7236 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13" 7237 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13(a) 0x0 /* PF_BAR0 */ 7238 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13(a) (a) 7239 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL13(a) (a), -1, -1, -1 7240 7241 /** 7242 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl14 7243 * 7244 * DSS Ddrctl Regb Ddrc Ch0 Pasctl14 Register 7245 * Phase Aware Schedule Control Register 14 7246 */ 7247 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl14 { 7248 uint32_t u; 7249 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl14_s { 7250 uint32_t powerdown_exit_ba_1 : 8; 7251 uint32_t reserved_8_15 : 8; 7252 uint32_t powerdown_exit_size_1 : 8; 7253 uint32_t reserved_24_31 : 8; 7254 } s; 7255 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl14_s cn; */ 7256 }; 7257 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl14 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl14_t; 7258 7259 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14(uint64_t a) __attribute__ ((pure, always_inline)); 7260 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14(uint64_t a) 7261 { 7262 if (a <= 19) 7263 return 0x87e1b0210a38ll + 0x1000000ll * ((a) & 0x1f); 7264 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14", 1, a, 0, 0, 0, 0, 0); 7265 } 7266 7267 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl14_t 7268 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14(a) CSR_TYPE_RSL32b 7269 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14" 7270 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14(a) 0x0 /* PF_BAR0 */ 7271 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14(a) (a) 7272 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL14(a) (a), -1, -1, -1 7273 7274 /** 7275 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl19 7276 * 7277 * DSS Ddrctl Regb Ddrc Ch0 Pasctl19 Register 7278 * Phase Aware Schedule Control Register 19 7279 */ 7280 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl19 { 7281 uint32_t u; 7282 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl19_s { 7283 uint32_t prank0_mode : 8; 7284 uint32_t prank1_mode : 8; 7285 uint32_t reserved_16_31 : 16; 7286 } s; 7287 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl19_s cn; */ 7288 }; 7289 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl19 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl19_t; 7290 7291 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19(uint64_t a) __attribute__ ((pure, always_inline)); 7292 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19(uint64_t a) 7293 { 7294 if (a <= 19) 7295 return 0x87e1b0210a4cll + 0x1000000ll * ((a) & 0x1f); 7296 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19", 1, a, 0, 0, 0, 0, 0); 7297 } 7298 7299 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl19_t 7300 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19(a) CSR_TYPE_RSL32b 7301 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19" 7302 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19(a) 0x0 /* PF_BAR0 */ 7303 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19(a) (a) 7304 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL19(a) (a), -1, -1, -1 7305 7306 /** 7307 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl2 7308 * 7309 * DSS Ddrctl Regb Ddrc Ch0 Pasctl2 Register 7310 * Phase Aware Schedule Control Register 2 7311 */ 7312 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl2 { 7313 uint32_t u; 7314 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl2_s { 7315 uint32_t dyn_pre_pri_hi_win_size : 8; 7316 uint32_t dyn_pre_pri_lo_wait_thr : 8; 7317 uint32_t lrank_rd2rd_gap : 3; 7318 uint32_t lrank_wr2wr_gap : 3; 7319 uint32_t reserved_22_23 : 2; 7320 uint32_t refsb_hi_wait_thr : 6; 7321 uint32_t t_ppd_cnt_en : 1; 7322 uint32_t reserved_31 : 1; 7323 } s; 7324 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl2_s cn; */ 7325 }; 7326 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl2 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl2_t; 7327 7328 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2(uint64_t a) __attribute__ ((pure, always_inline)); 7329 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2(uint64_t a) 7330 { 7331 if (a <= 19) 7332 return 0x87e1b0210a08ll + 0x1000000ll * ((a) & 0x1f); 7333 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2", 1, a, 0, 0, 0, 0, 0); 7334 } 7335 7336 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl2_t 7337 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2(a) CSR_TYPE_RSL32b 7338 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2" 7339 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2(a) 0x0 /* PF_BAR0 */ 7340 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2(a) (a) 7341 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL2(a) (a), -1, -1, -1 7342 7343 /** 7344 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl20 7345 * 7346 * DSS Ddrctl Regb Ddrc Ch0 Pasctl20 Register 7347 * Phase Aware Schedule Control Register 20 7348 */ 7349 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl20 { 7350 uint32_t u; 7351 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl20_s { 7352 uint32_t selfref_entry1_ba_0 : 8; 7353 uint32_t reserved_8_15 : 8; 7354 uint32_t selfref_entry1_size_0 : 8; 7355 uint32_t reserved_24_31 : 8; 7356 } s; 7357 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl20_s cn; */ 7358 }; 7359 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl20 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl20_t; 7360 7361 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20(uint64_t a) __attribute__ ((pure, always_inline)); 7362 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20(uint64_t a) 7363 { 7364 if (a <= 19) 7365 return 0x87e1b0210a50ll + 0x1000000ll * ((a) & 0x1f); 7366 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20", 1, a, 0, 0, 0, 0, 0); 7367 } 7368 7369 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl20_t 7370 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20(a) CSR_TYPE_RSL32b 7371 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20" 7372 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20(a) 0x0 /* PF_BAR0 */ 7373 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20(a) (a) 7374 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL20(a) (a), -1, -1, -1 7375 7376 /** 7377 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl21 7378 * 7379 * DSS Ddrctl Regb Ddrc Ch0 Pasctl21 Register 7380 * Phase Aware Schedule Control Register 21 7381 */ 7382 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl21 { 7383 uint32_t u; 7384 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl21_s { 7385 uint32_t selfref_entry2_ba_0 : 8; 7386 uint32_t reserved_8_15 : 8; 7387 uint32_t selfref_entry2_size_0 : 8; 7388 uint32_t reserved_24_31 : 8; 7389 } s; 7390 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl21_s cn; */ 7391 }; 7392 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl21 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl21_t; 7393 7394 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21(uint64_t a) __attribute__ ((pure, always_inline)); 7395 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21(uint64_t a) 7396 { 7397 if (a <= 19) 7398 return 0x87e1b0210a54ll + 0x1000000ll * ((a) & 0x1f); 7399 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21", 1, a, 0, 0, 0, 0, 0); 7400 } 7401 7402 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl21_t 7403 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21(a) CSR_TYPE_RSL32b 7404 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21" 7405 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21(a) 0x0 /* PF_BAR0 */ 7406 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21(a) (a) 7407 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL21(a) (a), -1, -1, -1 7408 7409 /** 7410 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl22 7411 * 7412 * DSS Ddrctl Regb Ddrc Ch0 Pasctl22 Register 7413 * Phase Aware Schedule Control Register 22 7414 */ 7415 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl22 { 7416 uint32_t u; 7417 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl22_s { 7418 uint32_t selfref_exit1_ba_0 : 8; 7419 uint32_t reserved_8_15 : 8; 7420 uint32_t selfref_exit1_size_0 : 8; 7421 uint32_t reserved_24_31 : 8; 7422 } s; 7423 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl22_s cn; */ 7424 }; 7425 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl22 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl22_t; 7426 7427 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22(uint64_t a) __attribute__ ((pure, always_inline)); 7428 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22(uint64_t a) 7429 { 7430 if (a <= 19) 7431 return 0x87e1b0210a58ll + 0x1000000ll * ((a) & 0x1f); 7432 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22", 1, a, 0, 0, 0, 0, 0); 7433 } 7434 7435 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl22_t 7436 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22(a) CSR_TYPE_RSL32b 7437 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22" 7438 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22(a) 0x0 /* PF_BAR0 */ 7439 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22(a) (a) 7440 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL22(a) (a), -1, -1, -1 7441 7442 /** 7443 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl23 7444 * 7445 * DSS Ddrctl Regb Ddrc Ch0 Pasctl23 Register 7446 * Phase Aware Schedule Control Register 23 7447 */ 7448 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl23 { 7449 uint32_t u; 7450 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl23_s { 7451 uint32_t selfref_exit2_ba_0 : 8; 7452 uint32_t reserved_8_15 : 8; 7453 uint32_t selfref_exit2_size_0 : 8; 7454 uint32_t reserved_24_31 : 8; 7455 } s; 7456 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl23_s cn; */ 7457 }; 7458 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl23 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl23_t; 7459 7460 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23(uint64_t a) __attribute__ ((pure, always_inline)); 7461 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23(uint64_t a) 7462 { 7463 if (a <= 19) 7464 return 0x87e1b0210a5cll + 0x1000000ll * ((a) & 0x1f); 7465 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23", 1, a, 0, 0, 0, 0, 0); 7466 } 7467 7468 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl23_t 7469 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23(a) CSR_TYPE_RSL32b 7470 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23" 7471 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23(a) 0x0 /* PF_BAR0 */ 7472 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23(a) (a) 7473 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL23(a) (a), -1, -1, -1 7474 7475 /** 7476 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl24 7477 * 7478 * DSS Ddrctl Regb Ddrc Ch0 Pasctl24 Register 7479 * Phase Aware Schedule Control Register 24 7480 */ 7481 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl24 { 7482 uint32_t u; 7483 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl24_s { 7484 uint32_t rfm_raa_en : 2; 7485 uint32_t reserved_2_3 : 2; 7486 uint32_t rfm_raa_reset : 2; 7487 uint32_t reserved_6_7 : 2; 7488 uint32_t rfm_raa_use_ecs_refab : 1; 7489 uint32_t reserved_9_15 : 7; 7490 uint32_t rfm_alert_thr : 16; 7491 } s; 7492 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl24_s cn; */ 7493 }; 7494 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl24 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl24_t; 7495 7496 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24(uint64_t a) __attribute__ ((pure, always_inline)); 7497 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24(uint64_t a) 7498 { 7499 if (a <= 19) 7500 return 0x87e1b0210a60ll + 0x1000000ll * ((a) & 0x1f); 7501 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24", 1, a, 0, 0, 0, 0, 0); 7502 } 7503 7504 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl24_t 7505 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24(a) CSR_TYPE_RSL32b 7506 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24" 7507 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24(a) 0x0 /* PF_BAR0 */ 7508 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24(a) (a) 7509 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL24(a) (a), -1, -1, -1 7510 7511 /** 7512 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl25 7513 * 7514 * DSS Ddrctl Regb Ddrc Ch0 Pasctl25 Register 7515 * Phase Aware Schedule Control Register 25 7516 */ 7517 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl25 { 7518 uint32_t u; 7519 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl25_s { 7520 uint32_t rfm_cmd_log : 32; 7521 } s; 7522 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl25_s cn; */ 7523 }; 7524 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl25 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl25_t; 7525 7526 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25(uint64_t a) __attribute__ ((pure, always_inline)); 7527 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25(uint64_t a) 7528 { 7529 if (a <= 19) 7530 return 0x87e1b0210a64ll + 0x1000000ll * ((a) & 0x1f); 7531 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25", 1, a, 0, 0, 0, 0, 0); 7532 } 7533 7534 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl25_t 7535 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25(a) CSR_TYPE_RSL32b 7536 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25" 7537 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25(a) 0x0 /* PF_BAR0 */ 7538 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25(a) (a) 7539 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL25(a) (a), -1, -1, -1 7540 7541 /** 7542 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl26 7543 * 7544 * DSS Ddrctl Regb Ddrc Ch0 Pasctl26 Register 7545 * Phase Aware Schedule Control Register 26 7546 */ 7547 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl26 { 7548 uint32_t u; 7549 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl26_s { 7550 uint32_t reserved_0_15 : 16; 7551 uint32_t capar_retry_size : 6; 7552 uint32_t reserved_22_31 : 10; 7553 } s; 7554 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl26_s cn; */ 7555 }; 7556 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl26 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl26_t; 7557 7558 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26(uint64_t a) __attribute__ ((pure, always_inline)); 7559 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26(uint64_t a) 7560 { 7561 if (a <= 19) 7562 return 0x87e1b0210a68ll + 0x1000000ll * ((a) & 0x1f); 7563 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26", 1, a, 0, 0, 0, 0, 0); 7564 } 7565 7566 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl26_t 7567 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26(a) CSR_TYPE_RSL32b 7568 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26" 7569 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26(a) 0x0 /* PF_BAR0 */ 7570 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26(a) (a) 7571 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL26(a) (a), -1, -1, -1 7572 7573 /** 7574 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl3 7575 * 7576 * DSS Ddrctl Regb Ddrc Ch0 Pasctl3 Register 7577 * Phase Aware Schedule Control Register 3 7578 */ 7579 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl3 { 7580 uint32_t u; 7581 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl3_s { 7582 uint32_t dimm_t_dcaw : 8; 7583 uint32_t dimm_n_dcac_m1 : 5; 7584 uint32_t reserved_13 : 1; 7585 uint32_t dimm_dcaw_en : 2; 7586 uint32_t reserved_16_31 : 16; 7587 } s; 7588 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl3_s cn; */ 7589 }; 7590 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl3 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl3_t; 7591 7592 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3(uint64_t a) __attribute__ ((pure, always_inline)); 7593 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3(uint64_t a) 7594 { 7595 if (a <= 19) 7596 return 0x87e1b0210a0cll + 0x1000000ll * ((a) & 0x1f); 7597 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3", 1, a, 0, 0, 0, 0, 0); 7598 } 7599 7600 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl3_t 7601 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3(a) CSR_TYPE_RSL32b 7602 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3" 7603 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3(a) 0x0 /* PF_BAR0 */ 7604 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3(a) (a) 7605 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL3(a) (a), -1, -1, -1 7606 7607 /** 7608 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl36 7609 * 7610 * DSS Ddrctl Regb Ddrc Ch0 Pasctl36 Register 7611 * Phase Aware Schedule Control Register 36 7612 */ 7613 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl36 { 7614 uint32_t u; 7615 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl36_s { 7616 uint32_t powerdown_idle_ctrl_0 : 2; 7617 uint32_t powerdown_idle_ctrl_1 : 1; 7618 uint32_t reserved_3_31 : 29; 7619 } s; 7620 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl36_s cn; */ 7621 }; 7622 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl36 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl36_t; 7623 7624 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36(uint64_t a) __attribute__ ((pure, always_inline)); 7625 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36(uint64_t a) 7626 { 7627 if (a <= 19) 7628 return 0x87e1b0210a90ll + 0x1000000ll * ((a) & 0x1f); 7629 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36", 1, a, 0, 0, 0, 0, 0); 7630 } 7631 7632 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl36_t 7633 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36(a) CSR_TYPE_RSL32b 7634 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36" 7635 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36(a) 0x0 /* PF_BAR0 */ 7636 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36(a) (a) 7637 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL36(a) (a), -1, -1, -1 7638 7639 /** 7640 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl37 7641 * 7642 * DSS Ddrctl Regb Ddrc Ch0 Pasctl37 Register 7643 * Phase Aware Schedule Control Register 37 7644 */ 7645 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl37 { 7646 uint32_t u; 7647 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl37_s { 7648 uint32_t dch_sync_mode : 1; 7649 uint32_t dch_ch0_mask : 1; 7650 uint32_t reserved_2_15 : 14; 7651 uint32_t t_selfref_exit_stagger : 5; 7652 uint32_t reserved_21_31 : 11; 7653 } s; 7654 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl37_s cn; */ 7655 }; 7656 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl37 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl37_t; 7657 7658 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37(uint64_t a) __attribute__ ((pure, always_inline)); 7659 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37(uint64_t a) 7660 { 7661 if (a <= 19) 7662 return 0x87e1b0210a94ll + 0x1000000ll * ((a) & 0x1f); 7663 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37", 1, a, 0, 0, 0, 0, 0); 7664 } 7665 7666 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl37_t 7667 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37(a) CSR_TYPE_RSL32b 7668 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37" 7669 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37(a) 0x0 /* PF_BAR0 */ 7670 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37(a) (a) 7671 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL37(a) (a), -1, -1, -1 7672 7673 /** 7674 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl38 7675 * 7676 * DSS Ddrctl Regb Ddrc Ch0 Pasctl38 Register 7677 * Phase Aware Schedule Control Register 38 7678 */ 7679 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl38 { 7680 uint32_t u; 7681 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl38_s { 7682 uint32_t bwl_win_len : 10; 7683 uint32_t bwl_en_len : 10; 7684 uint32_t reserved_20_29 : 10; 7685 uint32_t bwl_ctrl : 1; 7686 uint32_t bwl_en : 1; 7687 } s; 7688 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl38_s cn; */ 7689 }; 7690 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl38 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl38_t; 7691 7692 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38(uint64_t a) __attribute__ ((pure, always_inline)); 7693 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38(uint64_t a) 7694 { 7695 if (a <= 19) 7696 return 0x87e1b0210a98ll + 0x1000000ll * ((a) & 0x1f); 7697 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38", 1, a, 0, 0, 0, 0, 0); 7698 } 7699 7700 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl38_t 7701 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38(a) CSR_TYPE_RSL32b 7702 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38" 7703 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38(a) 0x0 /* PF_BAR0 */ 7704 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38(a) (a) 7705 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL38(a) (a), -1, -1, -1 7706 7707 /** 7708 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl4 7709 * 7710 * DSS Ddrctl Regb Ddrc Ch0 Pasctl4 Register 7711 * Phase Aware Schedule Control Register 4 7712 */ 7713 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl4 { 7714 uint32_t u; 7715 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl4_s { 7716 uint32_t ci_mrr_des1 : 4; 7717 uint32_t ci_mrr_des2 : 4; 7718 uint32_t ci_mrw_des1 : 4; 7719 uint32_t ci_mrw_des2 : 4; 7720 uint32_t ci_mpc_des1 : 4; 7721 uint32_t ci_mpc_des2 : 4; 7722 uint32_t reserved_24_31 : 8; 7723 } s; 7724 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl4_s cn; */ 7725 }; 7726 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl4 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl4_t; 7727 7728 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4(uint64_t a) __attribute__ ((pure, always_inline)); 7729 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4(uint64_t a) 7730 { 7731 if (a <= 19) 7732 return 0x87e1b0210a10ll + 0x1000000ll * ((a) & 0x1f); 7733 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4", 1, a, 0, 0, 0, 0, 0); 7734 } 7735 7736 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl4_t 7737 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4(a) CSR_TYPE_RSL32b 7738 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4" 7739 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4(a) 0x0 /* PF_BAR0 */ 7740 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4(a) (a) 7741 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL4(a) (a), -1, -1, -1 7742 7743 /** 7744 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl5 7745 * 7746 * DSS Ddrctl Regb Ddrc Ch0 Pasctl5 Register 7747 * Phase Aware Schedule Control Register 5 7748 */ 7749 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl5 { 7750 uint32_t u; 7751 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl5_s { 7752 uint32_t base_timer_en : 1; 7753 uint32_t reserved_1_31 : 31; 7754 } s; 7755 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl5_s cn; */ 7756 }; 7757 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl5 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl5_t; 7758 7759 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5(uint64_t a) __attribute__ ((pure, always_inline)); 7760 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5(uint64_t a) 7761 { 7762 if (a <= 19) 7763 return 0x87e1b0210a14ll + 0x1000000ll * ((a) & 0x1f); 7764 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5", 1, a, 0, 0, 0, 0, 0); 7765 } 7766 7767 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl5_t 7768 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5(a) CSR_TYPE_RSL32b 7769 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5" 7770 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5(a) 0x0 /* PF_BAR0 */ 7771 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5(a) (a) 7772 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL5(a) (a), -1, -1, -1 7773 7774 /** 7775 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl6 7776 * 7777 * DSS Ddrctl Regb Ddrc Ch0 Pasctl6 Register 7778 * Phase Aware Schedule Control Register 6 7779 */ 7780 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl6 { 7781 uint32_t u; 7782 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl6_s { 7783 uint32_t base_timer : 32; 7784 } s; 7785 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl6_s cn; */ 7786 }; 7787 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl6 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl6_t; 7788 7789 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6(uint64_t a) __attribute__ ((pure, always_inline)); 7790 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6(uint64_t a) 7791 { 7792 if (a <= 19) 7793 return 0x87e1b0210a18ll + 0x1000000ll * ((a) & 0x1f); 7794 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6", 1, a, 0, 0, 0, 0, 0); 7795 } 7796 7797 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl6_t 7798 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6(a) CSR_TYPE_RSL32b 7799 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6" 7800 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6(a) 0x0 /* PF_BAR0 */ 7801 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6(a) (a) 7802 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL6(a) (a), -1, -1, -1 7803 7804 /** 7805 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl7 7806 * 7807 * DSS Ddrctl Regb Ddrc Ch0 Pasctl7 Register 7808 * Phase Aware Schedule Control Register 7 7809 */ 7810 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl7 { 7811 uint32_t u; 7812 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl7_s { 7813 uint32_t glb_blk0_en : 1; 7814 uint32_t glb_blk1_en : 1; 7815 uint32_t glb_blk2_en : 1; 7816 uint32_t glb_blk3_en : 1; 7817 uint32_t glb_blk4_en : 1; 7818 uint32_t glb_blk5_en : 1; 7819 uint32_t glb_blk6_en : 1; 7820 uint32_t glb_blk7_en : 1; 7821 uint32_t reserved_8_31 : 24; 7822 } s; 7823 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl7_s cn; */ 7824 }; 7825 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl7 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl7_t; 7826 7827 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7(uint64_t a) __attribute__ ((pure, always_inline)); 7828 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7(uint64_t a) 7829 { 7830 if (a <= 19) 7831 return 0x87e1b0210a1cll + 0x1000000ll * ((a) & 0x1f); 7832 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7", 1, a, 0, 0, 0, 0, 0); 7833 } 7834 7835 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl7_t 7836 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7(a) CSR_TYPE_RSL32b 7837 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7" 7838 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7(a) 0x0 /* PF_BAR0 */ 7839 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7(a) (a) 7840 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL7(a) (a), -1, -1, -1 7841 7842 /** 7843 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl8 7844 * 7845 * DSS Ddrctl Regb Ddrc Ch0 Pasctl8 Register 7846 * Phase Aware Schedule Control Register 8 7847 */ 7848 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl8 { 7849 uint32_t u; 7850 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl8_s { 7851 uint32_t rank_blk0_en : 1; 7852 uint32_t rank_blk1_en : 1; 7853 uint32_t rank_blk2_en : 1; 7854 uint32_t rank_blk3_en : 1; 7855 uint32_t rank_blk4_en : 1; 7856 uint32_t rank_blk5_en : 1; 7857 uint32_t rank_blk6_en : 1; 7858 uint32_t rank_blk7_en : 1; 7859 uint32_t rank_blk8_en : 1; 7860 uint32_t rank_blk9_en : 1; 7861 uint32_t rank_blk10_en : 1; 7862 uint32_t rank_blk11_en : 1; 7863 uint32_t rank_blk12_en : 1; 7864 uint32_t rank_blk13_en : 1; 7865 uint32_t rank_blk14_en : 1; 7866 uint32_t rank_blk15_en : 1; 7867 uint32_t reserved_16_31 : 16; 7868 } s; 7869 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl8_s cn; */ 7870 }; 7871 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl8 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl8_t; 7872 7873 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8(uint64_t a) __attribute__ ((pure, always_inline)); 7874 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8(uint64_t a) 7875 { 7876 if (a <= 19) 7877 return 0x87e1b0210a20ll + 0x1000000ll * ((a) & 0x1f); 7878 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8", 1, a, 0, 0, 0, 0, 0); 7879 } 7880 7881 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl8_t 7882 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8(a) CSR_TYPE_RSL32b 7883 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8" 7884 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8(a) 0x0 /* PF_BAR0 */ 7885 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8(a) (a) 7886 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL8(a) (a), -1, -1, -1 7887 7888 /** 7889 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasctl9 7890 * 7891 * DSS Ddrctl Regb Ddrc Ch0 Pasctl9 Register 7892 * Phase Aware Schedule Control Register 9 7893 */ 7894 union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl9 { 7895 uint32_t u; 7896 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl9_s { 7897 uint32_t glb_blk0_trig : 1; 7898 uint32_t glb_blk1_trig : 1; 7899 uint32_t glb_blk2_trig : 1; 7900 uint32_t glb_blk3_trig : 1; 7901 uint32_t glb_blk4_trig : 1; 7902 uint32_t glb_blk5_trig : 1; 7903 uint32_t glb_blk6_trig : 1; 7904 uint32_t glb_blk7_trig : 1; 7905 uint32_t reserved_8_31 : 24; 7906 } s; 7907 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasctl9_s cn; */ 7908 }; 7909 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasctl9 ody_dssx_ddrctl_regb_ddrc_ch0_pasctl9_t; 7910 7911 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9(uint64_t a) __attribute__ ((pure, always_inline)); 7912 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9(uint64_t a) 7913 { 7914 if (a <= 19) 7915 return 0x87e1b0210a24ll + 0x1000000ll * ((a) & 0x1f); 7916 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9", 1, a, 0, 0, 0, 0, 0); 7917 } 7918 7919 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasctl9_t 7920 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9(a) CSR_TYPE_RSL32b 7921 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9" 7922 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9(a) 0x0 /* PF_BAR0 */ 7923 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9(a) (a) 7924 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASCTL9(a) (a), -1, -1, -1 7925 7926 /** 7927 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_paserrsts 7928 * 7929 * DSS Ddrctl Regb Ddrc Ch0 Paserrsts Register 7930 * Phase Aware Schedule Error Status Register 7931 */ 7932 union ody_dssx_ddrctl_regb_ddrc_ch0_paserrsts { 7933 uint32_t u; 7934 struct ody_dssx_ddrctl_regb_ddrc_ch0_paserrsts_s { 7935 uint32_t swcmd_err_sts : 3; 7936 uint32_t reserved_3 : 1; 7937 uint32_t ducmd_err_sts : 3; 7938 uint32_t reserved_7 : 1; 7939 uint32_t lccmd_err_sts : 3; 7940 uint32_t reserved_11 : 1; 7941 uint32_t caparcmd_err_sts : 3; 7942 uint32_t reserved_15_31 : 17; 7943 } s; 7944 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_paserrsts_s cn; */ 7945 }; 7946 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_paserrsts ody_dssx_ddrctl_regb_ddrc_ch0_paserrsts_t; 7947 7948 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS(uint64_t a) __attribute__ ((pure, always_inline)); 7949 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS(uint64_t a) 7950 { 7951 if (a <= 19) 7952 return 0x87e1b0210b20ll + 0x1000000ll * ((a) & 0x1f); 7953 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS", 1, a, 0, 0, 0, 0, 0); 7954 } 7955 7956 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS(a) ody_dssx_ddrctl_regb_ddrc_ch0_paserrsts_t 7957 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS(a) CSR_TYPE_RSL32b 7958 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS" 7959 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS(a) 0x0 /* PF_BAR0 */ 7960 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS(a) (a) 7961 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASERRSTS(a) (a), -1, -1, -1 7962 7963 /** 7964 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasint 7965 * 7966 * DSS Ddrctl Regb Ddrc Ch0 Pasint Register 7967 * Phase Aware Schedule Interrupt register 7968 */ 7969 union ody_dssx_ddrctl_regb_ddrc_ch0_pasint { 7970 uint32_t u; 7971 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasint_s { 7972 uint32_t swcmd_err_intr : 1; 7973 uint32_t ducmd_err_intr : 1; 7974 uint32_t lccmd_err_intr : 1; 7975 uint32_t ctrlupd_err_intr : 1; 7976 uint32_t rfm_alert_intr : 1; 7977 uint32_t caparcmd_err_intr : 1; 7978 uint32_t reserved_6_31 : 26; 7979 } s; 7980 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasint_s cn; */ 7981 }; 7982 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasint ody_dssx_ddrctl_regb_ddrc_ch0_pasint_t; 7983 7984 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINT(uint64_t a) __attribute__ ((pure, always_inline)); 7985 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINT(uint64_t a) 7986 { 7987 if (a <= 19) 7988 return 0x87e1b0210b18ll + 0x1000000ll * ((a) & 0x1f); 7989 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASINT", 1, a, 0, 0, 0, 0, 0); 7990 } 7991 7992 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINT(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasint_t 7993 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINT(a) CSR_TYPE_RSL32b 7994 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASINT" 7995 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINT(a) 0x0 /* PF_BAR0 */ 7996 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINT(a) (a) 7997 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINT(a) (a), -1, -1, -1 7998 7999 /** 8000 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pasintctl 8001 * 8002 * DSS Ddrctl Regb Ddrc Ch0 Pasintctl Register 8003 * Phase Aware Schedule Interrupt Control Register 8004 */ 8005 union ody_dssx_ddrctl_regb_ddrc_ch0_pasintctl { 8006 uint32_t u; 8007 struct ody_dssx_ddrctl_regb_ddrc_ch0_pasintctl_s { 8008 uint32_t swcmd_err_intr_en : 1; 8009 uint32_t swcmd_err_intr_clr : 1; 8010 uint32_t swcmd_err_intr_force : 1; 8011 uint32_t reserved_3 : 1; 8012 uint32_t ducmd_err_intr_en : 1; 8013 uint32_t ducmd_err_intr_clr : 1; 8014 uint32_t ducmd_err_intr_force : 1; 8015 uint32_t reserved_7 : 1; 8016 uint32_t lccmd_err_intr_en : 1; 8017 uint32_t lccmd_err_intr_clr : 1; 8018 uint32_t lccmd_err_intr_force : 1; 8019 uint32_t reserved_11 : 1; 8020 uint32_t ctrlupd_err_intr_en : 1; 8021 uint32_t ctrlupd_err_intr_clr : 1; 8022 uint32_t ctrlupd_err_intr_force : 1; 8023 uint32_t reserved_15 : 1; 8024 uint32_t rfm_alert_intr_en : 1; 8025 uint32_t rfm_alert_intr_clr : 1; 8026 uint32_t rfm_alert_intr_force : 1; 8027 uint32_t reserved_19 : 1; 8028 uint32_t caparcmd_err_intr_en : 1; 8029 uint32_t caparcmd_err_intr_clr : 1; 8030 uint32_t caparcmd_err_intr_force : 1; 8031 uint32_t reserved_23_31 : 9; 8032 } s; 8033 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pasintctl_s cn; */ 8034 }; 8035 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pasintctl ody_dssx_ddrctl_regb_ddrc_ch0_pasintctl_t; 8036 8037 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL(uint64_t a) __attribute__ ((pure, always_inline)); 8038 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL(uint64_t a) 8039 { 8040 if (a <= 19) 8041 return 0x87e1b0210b1cll + 0x1000000ll * ((a) & 0x1f); 8042 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL", 1, a, 0, 0, 0, 0, 0); 8043 } 8044 8045 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_pasintctl_t 8046 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL(a) CSR_TYPE_RSL32b 8047 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL" 8048 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL(a) 0x0 /* PF_BAR0 */ 8049 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL(a) (a) 8050 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PASINTCTL(a) (a), -1, -1, -1 8051 8052 /** 8053 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_pwrctl 8054 * 8055 * DSS Ddrctl Regb Ddrc Ch0 Pwrctl Register 8056 * Low Power Control Register 8057 */ 8058 union ody_dssx_ddrctl_regb_ddrc_ch0_pwrctl { 8059 uint32_t u; 8060 struct ody_dssx_ddrctl_regb_ddrc_ch0_pwrctl_s { 8061 uint32_t selfref_en : 2; 8062 uint32_t reserved_2_3 : 2; 8063 uint32_t powerdown_en : 2; 8064 uint32_t reserved_6_7 : 2; 8065 uint32_t actv_pd_en : 1; 8066 uint32_t en_dfi_dram_clk_disable : 1; 8067 uint32_t reserved_10 : 1; 8068 uint32_t selfref_sw : 1; 8069 uint32_t reserved_12_19 : 8; 8070 uint32_t mpsm_pd_en : 2; 8071 uint32_t reserved_22_23 : 2; 8072 uint32_t mpsm_deep_pd_en : 2; 8073 uint32_t reserved_26_31 : 6; 8074 } s; 8075 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_pwrctl_s cn; */ 8076 }; 8077 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_pwrctl ody_dssx_ddrctl_regb_ddrc_ch0_pwrctl_t; 8078 8079 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL(uint64_t a) __attribute__ ((pure, always_inline)); 8080 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL(uint64_t a) 8081 { 8082 if (a <= 19) 8083 return 0x87e1b0210180ll + 0x1000000ll * ((a) & 0x1f); 8084 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL", 1, a, 0, 0, 0, 0, 0); 8085 } 8086 8087 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_pwrctl_t 8088 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL(a) CSR_TYPE_RSL32b 8089 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL" 8090 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL(a) 0x0 /* PF_BAR0 */ 8091 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL(a) (a) 8092 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_PWRCTL(a) (a), -1, -1, -1 8093 8094 /** 8095 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rankctl 8096 * 8097 * DSS Ddrctl Regb Ddrc Ch0 Rankctl Register 8098 * Rank Control Register 8099 */ 8100 union ody_dssx_ddrctl_regb_ddrc_ch0_rankctl { 8101 uint32_t u; 8102 struct ody_dssx_ddrctl_regb_ddrc_ch0_rankctl_s { 8103 uint32_t max_rank_rd : 4; 8104 uint32_t reserved_4_11 : 8; 8105 uint32_t max_rank_wr : 4; 8106 uint32_t reserved_16_31 : 16; 8107 } s; 8108 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rankctl_s cn; */ 8109 }; 8110 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rankctl ody_dssx_ddrctl_regb_ddrc_ch0_rankctl_t; 8111 8112 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL(uint64_t a) __attribute__ ((pure, always_inline)); 8113 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL(uint64_t a) 8114 { 8115 if (a <= 19) 8116 return 0x87e1b0210c90ll + 0x1000000ll * ((a) & 0x1f); 8117 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL", 1, a, 0, 0, 0, 0, 0); 8118 } 8119 8120 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_rankctl_t 8121 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL(a) CSR_TYPE_RSL32b 8122 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL" 8123 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL(a) 0x0 /* PF_BAR0 */ 8124 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL(a) (a) 8125 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RANKCTL(a) (a), -1, -1, -1 8126 8127 /** 8128 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rdcrcerraddr0 8129 * 8130 * DSS Ddrctl Regb Ddrc Ch0 Rdcrcerraddr0 Register 8131 * Read CRC Error Address Register 0 8132 */ 8133 union ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr0 { 8134 uint32_t u; 8135 struct ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr0_s { 8136 uint32_t rd_crc_err_row : 18; 8137 uint32_t reserved_18_23 : 6; 8138 uint32_t rd_crc_err_rank : 1; 8139 uint32_t reserved_25_31 : 7; 8140 } s; 8141 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr0_s cn; */ 8142 }; 8143 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr0 ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr0_t; 8144 8145 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0(uint64_t a) __attribute__ ((pure, always_inline)); 8146 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0(uint64_t a) 8147 { 8148 if (a <= 19) 8149 return 0x87e1b0210830ll + 0x1000000ll * ((a) & 0x1f); 8150 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0", 1, a, 0, 0, 0, 0, 0); 8151 } 8152 8153 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0(a) ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr0_t 8154 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0(a) CSR_TYPE_RSL32b 8155 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0" 8156 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0(a) 0x0 /* PF_BAR0 */ 8157 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0(a) (a) 8158 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR0(a) (a), -1, -1, -1 8159 8160 /** 8161 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rdcrcerraddr1 8162 * 8163 * DSS Ddrctl Regb Ddrc Ch0 Rdcrcerraddr1 Register 8164 * Read CRC Error Address Register 1 8165 */ 8166 union ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr1 { 8167 uint32_t u; 8168 struct ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr1_s { 8169 uint32_t rd_crc_err_col : 11; 8170 uint32_t reserved_11_15 : 5; 8171 uint32_t rd_crc_err_bank : 2; 8172 uint32_t reserved_18_23 : 6; 8173 uint32_t rd_crc_err_bg : 3; 8174 uint32_t reserved_27_31 : 5; 8175 } s; 8176 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr1_s cn; */ 8177 }; 8178 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr1 ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr1_t; 8179 8180 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1(uint64_t a) __attribute__ ((pure, always_inline)); 8181 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1(uint64_t a) 8182 { 8183 if (a <= 19) 8184 return 0x87e1b0210834ll + 0x1000000ll * ((a) & 0x1f); 8185 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1", 1, a, 0, 0, 0, 0, 0); 8186 } 8187 8188 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1(a) ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerraddr1_t 8189 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1(a) CSR_TYPE_RSL32b 8190 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1" 8191 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1(a) 0x0 /* PF_BAR0 */ 8192 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1(a) (a) 8193 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRADDR1(a) (a), -1, -1, -1 8194 8195 /** 8196 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rdcrcerrstat0 8197 * 8198 * DSS Ddrctl Regb Ddrc Ch0 Rdcrcerrstat0 Register 8199 * Read CRC Error Status Register 0 8200 */ 8201 union ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerrstat0 { 8202 uint32_t u; 8203 struct ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerrstat0_s { 8204 uint32_t rd_crc_err_max_reached_int_nibble : 20; 8205 uint32_t reserved_20_30 : 11; 8206 uint32_t rd_crc_err_max_reached_int : 1; 8207 } s; 8208 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerrstat0_s cn; */ 8209 }; 8210 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerrstat0 ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerrstat0_t; 8211 8212 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0(uint64_t a) __attribute__ ((pure, always_inline)); 8213 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0(uint64_t a) 8214 { 8215 if (a <= 19) 8216 return 0x87e1b0210840ll + 0x1000000ll * ((a) & 0x1f); 8217 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0", 1, a, 0, 0, 0, 0, 0); 8218 } 8219 8220 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_rdcrcerrstat0_t 8221 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0(a) CSR_TYPE_RSL32b 8222 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0" 8223 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0(a) 0x0 /* PF_BAR0 */ 8224 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0(a) (a) 8225 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RDCRCERRSTAT0(a) (a), -1, -1, -1 8226 8227 /** 8228 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_retryctl0 8229 * 8230 * DSS Ddrctl Regb Ddrc Ch0 Retryctl0 Register 8231 * Retry Control Register 0 8232 */ 8233 union ody_dssx_ddrctl_regb_ddrc_ch0_retryctl0 { 8234 uint32_t u; 8235 struct ody_dssx_ddrctl_regb_ddrc_ch0_retryctl0_s { 8236 uint32_t capar_retry_enable : 1; 8237 uint32_t rd_ue_retry_enable : 1; 8238 uint32_t rd_crc_retry_enable : 1; 8239 uint32_t wr_crc_retry_enable : 1; 8240 uint32_t reserved_4_7 : 4; 8241 uint32_t wr_crc_retry_limiter : 3; 8242 uint32_t rd_crc_retry_limiter : 3; 8243 uint32_t rd_ue_retry_limiter : 3; 8244 uint32_t capar_retry_limiter : 3; 8245 uint32_t wr_crc_retry_limit_intr_en : 1; 8246 uint32_t wr_crc_retry_limit_intr_clr : 1; 8247 uint32_t wr_crc_retry_limit_intr_force : 1; 8248 uint32_t rd_retry_limit_intr_en : 1; 8249 uint32_t rd_retry_limit_intr_clr : 1; 8250 uint32_t rd_retry_limit_intr_force : 1; 8251 uint32_t capar_retry_limit_intr_en : 1; 8252 uint32_t capar_retry_limit_intr_clr : 1; 8253 uint32_t capar_retry_limit_intr_force : 1; 8254 uint32_t reserved_29_31 : 3; 8255 } s; 8256 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_retryctl0_s cn; */ 8257 }; 8258 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_retryctl0 ody_dssx_ddrctl_regb_ddrc_ch0_retryctl0_t; 8259 8260 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0(uint64_t a) __attribute__ ((pure, always_inline)); 8261 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0(uint64_t a) 8262 { 8263 if (a <= 19) 8264 return 0x87e1b0210890ll + 0x1000000ll * ((a) & 0x1f); 8265 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0", 1, a, 0, 0, 0, 0, 0); 8266 } 8267 8268 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0(a) ody_dssx_ddrctl_regb_ddrc_ch0_retryctl0_t 8269 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0(a) CSR_TYPE_RSL32b 8270 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0" 8271 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0(a) 0x0 /* PF_BAR0 */ 8272 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0(a) (a) 8273 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL0(a) (a), -1, -1, -1 8274 8275 /** 8276 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_retryctl1 8277 * 8278 * DSS Ddrctl Regb Ddrc Ch0 Retryctl1 Register 8279 * Retry Control Register 1 8280 */ 8281 union ody_dssx_ddrctl_regb_ddrc_ch0_retryctl1 { 8282 uint32_t u; 8283 struct ody_dssx_ddrctl_regb_ddrc_ch0_retryctl1_s { 8284 uint32_t reserved_0_28 : 29; 8285 uint32_t make_multi_retry_fatl_err : 1; 8286 uint32_t dis_capar_selfref_retry : 1; 8287 uint32_t dis_capar_powerdown_retry : 1; 8288 } s; 8289 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_retryctl1_s cn; */ 8290 }; 8291 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_retryctl1 ody_dssx_ddrctl_regb_ddrc_ch0_retryctl1_t; 8292 8293 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1(uint64_t a) __attribute__ ((pure, always_inline)); 8294 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1(uint64_t a) 8295 { 8296 if (a <= 19) 8297 return 0x87e1b0210894ll + 0x1000000ll * ((a) & 0x1f); 8298 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1", 1, a, 0, 0, 0, 0, 0); 8299 } 8300 8301 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1(a) ody_dssx_ddrctl_regb_ddrc_ch0_retryctl1_t 8302 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1(a) CSR_TYPE_RSL32b 8303 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1" 8304 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1(a) 0x0 /* PF_BAR0 */ 8305 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1(a) (a) 8306 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYCTL1(a) (a), -1, -1, -1 8307 8308 /** 8309 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_retrystat0 8310 * 8311 * DSS Ddrctl Regb Ddrc Ch0 Retrystat0 Register 8312 * CRC retry State register 8313 */ 8314 union ody_dssx_ddrctl_regb_ddrc_ch0_retrystat0 { 8315 uint32_t u; 8316 struct ody_dssx_ddrctl_regb_ddrc_ch0_retrystat0_s { 8317 uint32_t retry_stat : 2; 8318 uint32_t reserved_2_6 : 5; 8319 uint32_t retry_fifo_fill_level : 8; 8320 uint32_t reserved_15 : 1; 8321 uint32_t rd_ue_retry_limit_reached : 1; 8322 uint32_t rd_crc_retry_limit_reached : 1; 8323 uint32_t reserved_18_23 : 6; 8324 uint32_t capar_fatl_err_code : 6; 8325 uint32_t reserved_30_31 : 2; 8326 } s; 8327 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_retrystat0_s cn; */ 8328 }; 8329 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_retrystat0 ody_dssx_ddrctl_regb_ddrc_ch0_retrystat0_t; 8330 8331 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0(uint64_t a) __attribute__ ((pure, always_inline)); 8332 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0(uint64_t a) 8333 { 8334 if (a <= 19) 8335 return 0x87e1b02108a0ll + 0x1000000ll * ((a) & 0x1f); 8336 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0", 1, a, 0, 0, 0, 0, 0); 8337 } 8338 8339 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0(a) ody_dssx_ddrctl_regb_ddrc_ch0_retrystat0_t 8340 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0(a) CSR_TYPE_RSL32b 8341 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0" 8342 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0(a) 0x0 /* PF_BAR0 */ 8343 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0(a) (a) 8344 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RETRYSTAT0(a) (a), -1, -1, -1 8345 8346 /** 8347 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rfshctl0 8348 * 8349 * DSS Ddrctl Regb Ddrc Ch0 Rfshctl0 Register 8350 * Refresh Control Register 0 8351 */ 8352 union ody_dssx_ddrctl_regb_ddrc_ch0_rfshctl0 { 8353 uint32_t u; 8354 struct ody_dssx_ddrctl_regb_ddrc_ch0_rfshctl0_s { 8355 uint32_t dis_auto_refresh : 1; 8356 uint32_t reserved_1_3 : 3; 8357 uint32_t refresh_update_level : 1; 8358 uint32_t reserved_5_31 : 27; 8359 } s; 8360 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rfshctl0_s cn; */ 8361 }; 8362 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rfshctl0 ody_dssx_ddrctl_regb_ddrc_ch0_rfshctl0_t; 8363 8364 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0(uint64_t a) __attribute__ ((pure, always_inline)); 8365 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0(uint64_t a) 8366 { 8367 if (a <= 19) 8368 return 0x87e1b0210208ll + 0x1000000ll * ((a) & 0x1f); 8369 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0", 1, a, 0, 0, 0, 0, 0); 8370 } 8371 8372 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0(a) ody_dssx_ddrctl_regb_ddrc_ch0_rfshctl0_t 8373 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0(a) CSR_TYPE_RSL32b 8374 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0" 8375 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0(a) 0x0 /* PF_BAR0 */ 8376 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0(a) (a) 8377 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHCTL0(a) (a), -1, -1, -1 8378 8379 /** 8380 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rfshmod0 8381 * 8382 * DSS Ddrctl Regb Ddrc Ch0 Rfshmod0 Register 8383 * Refresh Mode Register 0 8384 */ 8385 union ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod0 { 8386 uint32_t u; 8387 struct ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod0_s { 8388 uint32_t refresh_burst : 6; 8389 uint32_t reserved_6_15 : 10; 8390 uint32_t mixed_refsb_hi_thr : 4; 8391 uint32_t reserved_20_31 : 12; 8392 } s; 8393 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod0_s cn; */ 8394 }; 8395 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod0 ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod0_t; 8396 8397 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0(uint64_t a) __attribute__ ((pure, always_inline)); 8398 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0(uint64_t a) 8399 { 8400 if (a <= 19) 8401 return 0x87e1b0210200ll + 0x1000000ll * ((a) & 0x1f); 8402 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0", 1, a, 0, 0, 0, 0, 0); 8403 } 8404 8405 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0(a) ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod0_t 8406 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0(a) CSR_TYPE_RSL32b 8407 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0" 8408 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0(a) 0x0 /* PF_BAR0 */ 8409 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0(a) (a) 8410 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD0(a) (a), -1, -1, -1 8411 8412 /** 8413 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rfshmod1 8414 * 8415 * DSS Ddrctl Regb Ddrc Ch0 Rfshmod1 Register 8416 * Refresh Mode Register 1 8417 */ 8418 union ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod1 { 8419 uint32_t u; 8420 struct ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod1_s { 8421 uint32_t same_bank_refresh : 2; 8422 uint32_t reserved_2_3 : 2; 8423 uint32_t tcr_refab_thr : 3; 8424 uint32_t reserved_7 : 1; 8425 uint32_t fgr_mode : 3; 8426 uint32_t reserved_11_31 : 21; 8427 } s; 8428 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod1_s cn; */ 8429 }; 8430 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod1 ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod1_t; 8431 8432 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1(uint64_t a) __attribute__ ((pure, always_inline)); 8433 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1(uint64_t a) 8434 { 8435 if (a <= 19) 8436 return 0x87e1b0210204ll + 0x1000000ll * ((a) & 0x1f); 8437 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1", 1, a, 0, 0, 0, 0, 0); 8438 } 8439 8440 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1(a) ody_dssx_ddrctl_regb_ddrc_ch0_rfshmod1_t 8441 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1(a) CSR_TYPE_RSL32b 8442 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1" 8443 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1(a) 0x0 /* PF_BAR0 */ 8444 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1(a) (a) 8445 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RFSHMOD1(a) (a), -1, -1, -1 8446 8447 /** 8448 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rw_cmd_ctrl 8449 * 8450 * DSS Ddrctl Regb Ddrc Ch0 Rw Cmd Ctrl Register 8451 * Software Read Write Buffer Command Control 8452 */ 8453 union ody_dssx_ddrctl_regb_ddrc_ch0_rw_cmd_ctrl { 8454 uint32_t u; 8455 struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_cmd_ctrl_s { 8456 uint32_t wr_data_cb : 8; 8457 uint32_t wr_data_dq_mask : 8; 8458 uint32_t reserved_16_19 : 4; 8459 uint32_t wr_data_cb_mask : 1; 8460 uint32_t data_ecc_sel : 1; 8461 uint32_t rw_ecc_en : 1; 8462 uint32_t wr_data_sel : 1; 8463 uint32_t buf_addr : 4; 8464 uint32_t reserved_28_29 : 2; 8465 uint32_t buf_rw_op_type : 1; 8466 uint32_t buf_rw_start : 1; 8467 } s; 8468 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_cmd_ctrl_s cn; */ 8469 }; 8470 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rw_cmd_ctrl ody_dssx_ddrctl_regb_ddrc_ch0_rw_cmd_ctrl_t; 8471 8472 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 8473 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL(uint64_t a) 8474 { 8475 if (a <= 19) 8476 return 0x87e1b0210b3cll + 0x1000000ll * ((a) & 0x1f); 8477 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL", 1, a, 0, 0, 0, 0, 0); 8478 } 8479 8480 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL(a) ody_dssx_ddrctl_regb_ddrc_ch0_rw_cmd_ctrl_t 8481 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL(a) CSR_TYPE_RSL32b 8482 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL" 8483 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL(a) 0x0 /* PF_BAR0 */ 8484 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL(a) (a) 8485 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_CMD_CTRL(a) (a), -1, -1, -1 8486 8487 /** 8488 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rw_rd_data0 8489 * 8490 * DSS Ddrctl Regb Ddrc Ch0 Rw Rd Data0 Register 8491 * Software Read Command RD Data Register mapped to DQ[31:0] 8492 */ 8493 union ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data0 { 8494 uint32_t u; 8495 struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data0_s { 8496 uint32_t rd_data_dq0 : 32; 8497 } s; 8498 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data0_s cn; */ 8499 }; 8500 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data0 ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data0_t; 8501 8502 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0(uint64_t a) __attribute__ ((pure, always_inline)); 8503 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0(uint64_t a) 8504 { 8505 if (a <= 19) 8506 return 0x87e1b0210b48ll + 0x1000000ll * ((a) & 0x1f); 8507 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0", 1, a, 0, 0, 0, 0, 0); 8508 } 8509 8510 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0(a) ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data0_t 8511 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0(a) CSR_TYPE_RSL32b 8512 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0" 8513 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0(a) 0x0 /* PF_BAR0 */ 8514 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0(a) (a) 8515 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA0(a) (a), -1, -1, -1 8516 8517 /** 8518 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rw_rd_data1 8519 * 8520 * DSS Ddrctl Regb Ddrc Ch0 Rw Rd Data1 Register 8521 * Software Read Command RD Data Register mapped to DQ[63:32] 8522 */ 8523 union ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data1 { 8524 uint32_t u; 8525 struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data1_s { 8526 uint32_t rd_data_dq1 : 32; 8527 } s; 8528 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data1_s cn; */ 8529 }; 8530 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data1 ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data1_t; 8531 8532 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1(uint64_t a) __attribute__ ((pure, always_inline)); 8533 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1(uint64_t a) 8534 { 8535 if (a <= 19) 8536 return 0x87e1b0210b4cll + 0x1000000ll * ((a) & 0x1f); 8537 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1", 1, a, 0, 0, 0, 0, 0); 8538 } 8539 8540 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1(a) ody_dssx_ddrctl_regb_ddrc_ch0_rw_rd_data1_t 8541 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1(a) CSR_TYPE_RSL32b 8542 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1" 8543 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1(a) 0x0 /* PF_BAR0 */ 8544 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1(a) (a) 8545 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_RD_DATA1(a) (a), -1, -1, -1 8546 8547 /** 8548 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rw_wr_data0 8549 * 8550 * DSS Ddrctl Regb Ddrc Ch0 Rw Wr Data0 Register 8551 * Software Write Command WR Data Register mapped to DQ[31:0] 8552 */ 8553 union ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data0 { 8554 uint32_t u; 8555 struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data0_s { 8556 uint32_t wr_data_dq0 : 32; 8557 } s; 8558 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data0_s cn; */ 8559 }; 8560 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data0 ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data0_t; 8561 8562 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0(uint64_t a) __attribute__ ((pure, always_inline)); 8563 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0(uint64_t a) 8564 { 8565 if (a <= 19) 8566 return 0x87e1b0210b40ll + 0x1000000ll * ((a) & 0x1f); 8567 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0", 1, a, 0, 0, 0, 0, 0); 8568 } 8569 8570 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0(a) ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data0_t 8571 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0(a) CSR_TYPE_RSL32b 8572 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0" 8573 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0(a) 0x0 /* PF_BAR0 */ 8574 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0(a) (a) 8575 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA0(a) (a), -1, -1, -1 8576 8577 /** 8578 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_rw_wr_data1 8579 * 8580 * DSS Ddrctl Regb Ddrc Ch0 Rw Wr Data1 Register 8581 * Software Write Command WR Data Register mapped to DQ[63:32] 8582 */ 8583 union ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data1 { 8584 uint32_t u; 8585 struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data1_s { 8586 uint32_t wr_data_dq1 : 32; 8587 } s; 8588 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data1_s cn; */ 8589 }; 8590 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data1 ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data1_t; 8591 8592 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1(uint64_t a) __attribute__ ((pure, always_inline)); 8593 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1(uint64_t a) 8594 { 8595 if (a <= 19) 8596 return 0x87e1b0210b44ll + 0x1000000ll * ((a) & 0x1f); 8597 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1", 1, a, 0, 0, 0, 0, 0); 8598 } 8599 8600 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1(a) ody_dssx_ddrctl_regb_ddrc_ch0_rw_wr_data1_t 8601 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1(a) CSR_TYPE_RSL32b 8602 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1" 8603 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1(a) 0x0 /* PF_BAR0 */ 8604 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1(a) (a) 8605 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_RW_WR_DATA1(a) (a), -1, -1, -1 8606 8607 /** 8608 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_sched0 8609 * 8610 * DSS Ddrctl Regb Ddrc Ch0 Sched0 Register 8611 * Scheduler Control Register 0 8612 */ 8613 union ody_dssx_ddrctl_regb_ddrc_ch0_sched0 { 8614 uint32_t u; 8615 struct ody_dssx_ddrctl_regb_ddrc_ch0_sched0_s { 8616 uint32_t reserved_0 : 1; 8617 uint32_t prefer_write : 1; 8618 uint32_t pageclose : 1; 8619 uint32_t reserved_3 : 1; 8620 uint32_t opt_wrcam_fill_level : 1; 8621 uint32_t dis_opt_ntt_by_act : 1; 8622 uint32_t dis_opt_ntt_by_pre : 1; 8623 uint32_t autopre_rmw : 1; 8624 uint32_t lpr_num_entries : 6; 8625 uint32_t reserved_14_26 : 13; 8626 uint32_t opt_act_lat : 1; 8627 uint32_t reserved_28_30 : 3; 8628 uint32_t opt_vprw_sch : 1; 8629 } s; 8630 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_sched0_s cn; */ 8631 }; 8632 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_sched0 ody_dssx_ddrctl_regb_ddrc_ch0_sched0_t; 8633 8634 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0(uint64_t a) __attribute__ ((pure, always_inline)); 8635 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0(uint64_t a) 8636 { 8637 if (a <= 19) 8638 return 0x87e1b0210380ll + 0x1000000ll * ((a) & 0x1f); 8639 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0", 1, a, 0, 0, 0, 0, 0); 8640 } 8641 8642 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0(a) ody_dssx_ddrctl_regb_ddrc_ch0_sched0_t 8643 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0(a) CSR_TYPE_RSL32b 8644 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0" 8645 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0(a) 0x0 /* PF_BAR0 */ 8646 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0(a) (a) 8647 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED0(a) (a), -1, -1, -1 8648 8649 /** 8650 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_sched1 8651 * 8652 * DSS Ddrctl Regb Ddrc Ch0 Sched1 Register 8653 * Scheduler Control Register 1 8654 */ 8655 union ody_dssx_ddrctl_regb_ddrc_ch0_sched1 { 8656 uint32_t u; 8657 struct ody_dssx_ddrctl_regb_ddrc_ch0_sched1_s { 8658 uint32_t reserved_0_11 : 12; 8659 uint32_t delay_switch_write : 4; 8660 uint32_t visible_window_limit_wr : 3; 8661 uint32_t reserved_19 : 1; 8662 uint32_t visible_window_limit_rd : 3; 8663 uint32_t reserved_23 : 1; 8664 uint32_t page_hit_limit_wr : 3; 8665 uint32_t reserved_27 : 1; 8666 uint32_t page_hit_limit_rd : 3; 8667 uint32_t opt_hit_gt_hpr : 1; 8668 } s; 8669 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_sched1_s cn; */ 8670 }; 8671 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_sched1 ody_dssx_ddrctl_regb_ddrc_ch0_sched1_t; 8672 8673 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1(uint64_t a) __attribute__ ((pure, always_inline)); 8674 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1(uint64_t a) 8675 { 8676 if (a <= 19) 8677 return 0x87e1b0210384ll + 0x1000000ll * ((a) & 0x1f); 8678 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1", 1, a, 0, 0, 0, 0, 0); 8679 } 8680 8681 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1(a) ody_dssx_ddrctl_regb_ddrc_ch0_sched1_t 8682 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1(a) CSR_TYPE_RSL32b 8683 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1(a) "DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1" 8684 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1(a) 0x0 /* PF_BAR0 */ 8685 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1(a) (a) 8686 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED1(a) (a), -1, -1, -1 8687 8688 /** 8689 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_sched3 8690 * 8691 * DSS Ddrctl Regb Ddrc Ch0 Sched3 Register 8692 * Scheduler Control Register 3 8693 */ 8694 union ody_dssx_ddrctl_regb_ddrc_ch0_sched3 { 8695 uint32_t u; 8696 struct ody_dssx_ddrctl_regb_ddrc_ch0_sched3_s { 8697 uint32_t wrcam_lowthresh : 6; 8698 uint32_t reserved_6_7 : 2; 8699 uint32_t wrcam_highthresh : 6; 8700 uint32_t reserved_14_15 : 2; 8701 uint32_t wr_pghit_num_thresh : 6; 8702 uint32_t reserved_22_23 : 2; 8703 uint32_t rd_pghit_num_thresh : 6; 8704 uint32_t reserved_30_31 : 2; 8705 } s; 8706 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_sched3_s cn; */ 8707 }; 8708 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_sched3 ody_dssx_ddrctl_regb_ddrc_ch0_sched3_t; 8709 8710 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3(uint64_t a) __attribute__ ((pure, always_inline)); 8711 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3(uint64_t a) 8712 { 8713 if (a <= 19) 8714 return 0x87e1b021038cll + 0x1000000ll * ((a) & 0x1f); 8715 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3", 1, a, 0, 0, 0, 0, 0); 8716 } 8717 8718 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3(a) ody_dssx_ddrctl_regb_ddrc_ch0_sched3_t 8719 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3(a) CSR_TYPE_RSL32b 8720 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3(a) "DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3" 8721 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3(a) 0x0 /* PF_BAR0 */ 8722 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3(a) (a) 8723 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED3(a) (a), -1, -1, -1 8724 8725 /** 8726 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_sched4 8727 * 8728 * DSS Ddrctl Regb Ddrc Ch0 Sched4 Register 8729 * Scheduler Control Register 4 8730 */ 8731 union ody_dssx_ddrctl_regb_ddrc_ch0_sched4 { 8732 uint32_t u; 8733 struct ody_dssx_ddrctl_regb_ddrc_ch0_sched4_s { 8734 uint32_t rd_act_idle_gap : 8; 8735 uint32_t wr_act_idle_gap : 8; 8736 uint32_t rd_page_exp_cycles : 8; 8737 uint32_t wr_page_exp_cycles : 8; 8738 } s; 8739 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_sched4_s cn; */ 8740 }; 8741 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_sched4 ody_dssx_ddrctl_regb_ddrc_ch0_sched4_t; 8742 8743 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4(uint64_t a) __attribute__ ((pure, always_inline)); 8744 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4(uint64_t a) 8745 { 8746 if (a <= 19) 8747 return 0x87e1b0210390ll + 0x1000000ll * ((a) & 0x1f); 8748 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4", 1, a, 0, 0, 0, 0, 0); 8749 } 8750 8751 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4(a) ody_dssx_ddrctl_regb_ddrc_ch0_sched4_t 8752 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4(a) CSR_TYPE_RSL32b 8753 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4(a) "DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4" 8754 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4(a) 0x0 /* PF_BAR0 */ 8755 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4(a) (a) 8756 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SCHED4(a) (a), -1, -1, -1 8757 8758 /** 8759 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_stat 8760 * 8761 * DSS Ddrctl Regb Ddrc Ch0 Stat Register 8762 * Operating Mode Status Register 8763 */ 8764 union ody_dssx_ddrctl_regb_ddrc_ch0_stat { 8765 uint32_t u; 8766 struct ody_dssx_ddrctl_regb_ddrc_ch0_stat_s { 8767 uint32_t operating_mode : 3; 8768 uint32_t reserved_3 : 1; 8769 uint32_t selfref_type : 4; 8770 uint32_t reserved_8_19 : 12; 8771 uint32_t powerdown_state : 2; 8772 uint32_t reserved_22_23 : 2; 8773 uint32_t mpsm_state : 2; 8774 uint32_t reserved_26_29 : 4; 8775 uint32_t dfi_lp_state : 1; 8776 uint32_t reserved_31 : 1; 8777 } s; 8778 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_stat_s cn; */ 8779 }; 8780 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_stat ody_dssx_ddrctl_regb_ddrc_ch0_stat_t; 8781 8782 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT(uint64_t a) __attribute__ ((pure, always_inline)); 8783 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT(uint64_t a) 8784 { 8785 if (a <= 19) 8786 return 0x87e1b0210014ll + 0x1000000ll * ((a) & 0x1f); 8787 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_STAT", 1, a, 0, 0, 0, 0, 0); 8788 } 8789 8790 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_stat_t 8791 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT(a) CSR_TYPE_RSL32b 8792 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_STAT" 8793 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT(a) 0x0 /* PF_BAR0 */ 8794 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT(a) (a) 8795 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT(a) (a), -1, -1, -1 8796 8797 /** 8798 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_stat2 8799 * 8800 * DSS Ddrctl Regb Ddrc Ch0 Stat2 Register 8801 * Operating Mode Status Register2 8802 */ 8803 union ody_dssx_ddrctl_regb_ddrc_ch0_stat2 { 8804 uint32_t u; 8805 struct ody_dssx_ddrctl_regb_ddrc_ch0_stat2_s { 8806 uint32_t glb_blk_events_ongoing : 8; 8807 uint32_t reserved_8_23 : 16; 8808 uint32_t selfref_ongoing : 2; 8809 uint32_t reserved_26_27 : 2; 8810 uint32_t powerdown_ongoing : 2; 8811 uint32_t reserved_30_31 : 2; 8812 } s; 8813 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_stat2_s cn; */ 8814 }; 8815 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_stat2 ody_dssx_ddrctl_regb_ddrc_ch0_stat2_t; 8816 8817 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT2(uint64_t a) __attribute__ ((pure, always_inline)); 8818 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT2(uint64_t a) 8819 { 8820 if (a <= 19) 8821 return 0x87e1b0210018ll + 0x1000000ll * ((a) & 0x1f); 8822 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_STAT2", 1, a, 0, 0, 0, 0, 0); 8823 } 8824 8825 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT2(a) ody_dssx_ddrctl_regb_ddrc_ch0_stat2_t 8826 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT2(a) CSR_TYPE_RSL32b 8827 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_STAT2" 8828 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT2(a) 0x0 /* PF_BAR0 */ 8829 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT2(a) (a) 8830 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT2(a) (a), -1, -1, -1 8831 8832 /** 8833 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_stat3 8834 * 8835 * DSS Ddrctl Regb Ddrc Ch0 Stat3 Register 8836 * Operating Mode Status Register3 8837 */ 8838 union ody_dssx_ddrctl_regb_ddrc_ch0_stat3 { 8839 uint32_t u; 8840 struct ody_dssx_ddrctl_regb_ddrc_ch0_stat3_s { 8841 uint32_t rank_blk_events_ongoing : 16; 8842 uint32_t reserved_16_31 : 16; 8843 } s; 8844 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_stat3_s cn; */ 8845 }; 8846 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_stat3 ody_dssx_ddrctl_regb_ddrc_ch0_stat3_t; 8847 8848 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT3(uint64_t a) __attribute__ ((pure, always_inline)); 8849 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT3(uint64_t a) 8850 { 8851 if (a <= 19) 8852 return 0x87e1b021001cll + 0x1000000ll * ((a) & 0x1f); 8853 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_STAT3", 1, a, 0, 0, 0, 0, 0); 8854 } 8855 8856 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT3(a) ody_dssx_ddrctl_regb_ddrc_ch0_stat3_t 8857 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT3(a) CSR_TYPE_RSL32b 8858 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT3(a) "DSSX_DDRCTL_REGB_DDRC_CH0_STAT3" 8859 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT3(a) 0x0 /* PF_BAR0 */ 8860 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT3(a) (a) 8861 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_STAT3(a) (a), -1, -1, -1 8862 8863 /** 8864 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_swctl 8865 * 8866 * DSS Ddrctl Regb Ddrc Ch0 Swctl Register 8867 * Software Register Programming Control Enable 8868 */ 8869 union ody_dssx_ddrctl_regb_ddrc_ch0_swctl { 8870 uint32_t u; 8871 struct ody_dssx_ddrctl_regb_ddrc_ch0_swctl_s { 8872 uint32_t sw_done : 1; 8873 uint32_t reserved_1_31 : 31; 8874 } s; 8875 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_swctl_s cn; */ 8876 }; 8877 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_swctl ody_dssx_ddrctl_regb_ddrc_ch0_swctl_t; 8878 8879 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL(uint64_t a) __attribute__ ((pure, always_inline)); 8880 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL(uint64_t a) 8881 { 8882 if (a <= 19) 8883 return 0x87e1b0210c80ll + 0x1000000ll * ((a) & 0x1f); 8884 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL", 1, a, 0, 0, 0, 0, 0); 8885 } 8886 8887 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL(a) ody_dssx_ddrctl_regb_ddrc_ch0_swctl_t 8888 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL(a) CSR_TYPE_RSL32b 8889 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL(a) "DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL" 8890 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL(a) 0x0 /* PF_BAR0 */ 8891 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL(a) (a) 8892 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTL(a) (a), -1, -1, -1 8893 8894 /** 8895 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_swctlstatic 8896 * 8897 * DSS Ddrctl Regb Ddrc Ch0 Swctlstatic Register 8898 * Static Registers Write Enable 8899 */ 8900 union ody_dssx_ddrctl_regb_ddrc_ch0_swctlstatic { 8901 uint32_t u; 8902 struct ody_dssx_ddrctl_regb_ddrc_ch0_swctlstatic_s { 8903 uint32_t sw_static_unlock : 1; 8904 uint32_t reserved_1_31 : 31; 8905 } s; 8906 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_swctlstatic_s cn; */ 8907 }; 8908 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_swctlstatic ody_dssx_ddrctl_regb_ddrc_ch0_swctlstatic_t; 8909 8910 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC(uint64_t a) __attribute__ ((pure, always_inline)); 8911 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC(uint64_t a) 8912 { 8913 if (a <= 19) 8914 return 0x87e1b0210ca4ll + 0x1000000ll * ((a) & 0x1f); 8915 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC", 1, a, 0, 0, 0, 0, 0); 8916 } 8917 8918 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC(a) ody_dssx_ddrctl_regb_ddrc_ch0_swctlstatic_t 8919 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC(a) CSR_TYPE_RSL32b 8920 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC(a) "DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC" 8921 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC(a) 0x0 /* PF_BAR0 */ 8922 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC(a) (a) 8923 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWCTLSTATIC(a) (a), -1, -1, -1 8924 8925 /** 8926 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_swstat 8927 * 8928 * DSS Ddrctl Regb Ddrc Ch0 Swstat Register 8929 * Software Register Programming Control Status 8930 */ 8931 union ody_dssx_ddrctl_regb_ddrc_ch0_swstat { 8932 uint32_t u; 8933 struct ody_dssx_ddrctl_regb_ddrc_ch0_swstat_s { 8934 uint32_t sw_done_ack : 1; 8935 uint32_t reserved_1_31 : 31; 8936 } s; 8937 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_swstat_s cn; */ 8938 }; 8939 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_swstat ody_dssx_ddrctl_regb_ddrc_ch0_swstat_t; 8940 8941 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT(uint64_t a) __attribute__ ((pure, always_inline)); 8942 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT(uint64_t a) 8943 { 8944 if (a <= 19) 8945 return 0x87e1b0210c84ll + 0x1000000ll * ((a) & 0x1f); 8946 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT", 1, a, 0, 0, 0, 0, 0); 8947 } 8948 8949 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT(a) ody_dssx_ddrctl_regb_ddrc_ch0_swstat_t 8950 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT(a) CSR_TYPE_RSL32b 8951 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT(a) "DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT" 8952 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT(a) 0x0 /* PF_BAR0 */ 8953 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT(a) (a) 8954 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_SWSTAT(a) (a), -1, -1, -1 8955 8956 /** 8957 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_zqctl0 8958 * 8959 * DSS Ddrctl Regb Ddrc Ch0 Zqctl0 Register 8960 * ZQ Control Register 0 8961 */ 8962 union ody_dssx_ddrctl_regb_ddrc_ch0_zqctl0 { 8963 uint32_t u; 8964 struct ody_dssx_ddrctl_regb_ddrc_ch0_zqctl0_s { 8965 uint32_t reserved_0_28 : 29; 8966 uint32_t zq_resistor_shared : 1; 8967 uint32_t reserved_30_31 : 2; 8968 } s; 8969 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_zqctl0_s cn; */ 8970 }; 8971 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_zqctl0 ody_dssx_ddrctl_regb_ddrc_ch0_zqctl0_t; 8972 8973 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0(uint64_t a) __attribute__ ((pure, always_inline)); 8974 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0(uint64_t a) 8975 { 8976 if (a <= 19) 8977 return 0x87e1b0210280ll + 0x1000000ll * ((a) & 0x1f); 8978 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0", 1, a, 0, 0, 0, 0, 0); 8979 } 8980 8981 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0(a) ody_dssx_ddrctl_regb_ddrc_ch0_zqctl0_t 8982 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0(a) CSR_TYPE_RSL32b 8983 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0" 8984 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0(a) 0x0 /* PF_BAR0 */ 8985 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0(a) (a) 8986 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL0(a) (a), -1, -1, -1 8987 8988 /** 8989 * Register (RSL32b) dss#_ddrctl_regb_ddrc_ch0_zqctl2 8990 * 8991 * DSS Ddrctl Regb Ddrc Ch0 Zqctl2 Register 8992 * ZQ Control Register 2 8993 */ 8994 union ody_dssx_ddrctl_regb_ddrc_ch0_zqctl2 { 8995 uint32_t u; 8996 struct ody_dssx_ddrctl_regb_ddrc_ch0_zqctl2_s { 8997 uint32_t dis_srx_zqcl : 1; 8998 uint32_t reserved_1_31 : 31; 8999 } s; 9000 /* struct ody_dssx_ddrctl_regb_ddrc_ch0_zqctl2_s cn; */ 9001 }; 9002 typedef union ody_dssx_ddrctl_regb_ddrc_ch0_zqctl2 ody_dssx_ddrctl_regb_ddrc_ch0_zqctl2_t; 9003 9004 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2(uint64_t a) __attribute__ ((pure, always_inline)); 9005 static inline uint64_t ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2(uint64_t a) 9006 { 9007 if (a <= 19) 9008 return 0x87e1b0210288ll + 0x1000000ll * ((a) & 0x1f); 9009 __ody_csr_fatal("DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2", 1, a, 0, 0, 0, 0, 0); 9010 } 9011 9012 #define typedef_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2(a) ody_dssx_ddrctl_regb_ddrc_ch0_zqctl2_t 9013 #define bustype_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2(a) CSR_TYPE_RSL32b 9014 #define basename_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2(a) "DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2" 9015 #define device_bar_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2(a) 0x0 /* PF_BAR0 */ 9016 #define busnum_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2(a) (a) 9017 #define arguments_ODY_DSSX_DDRCTL_REGB_DDRC_CH0_ZQCTL2(a) (a), -1, -1, -1 9018 9019 /** 9020 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_crcpartmg0 9021 * 9022 * DSS Ddrctl Regb Freq0 Ch0 Crcpartmg0 Register 9023 * CRC Parity Timing 0. The register is defined in term of DRAM clock cycles 9024 */ 9025 union ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg0 { 9026 uint32_t u; 9027 struct ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg0_s { 9028 uint32_t reserved_0_15 : 16; 9029 uint32_t t_wr_crc_alert_pw_max : 10; 9030 uint32_t reserved_26_27 : 2; 9031 uint32_t t_wr_crc_alert_pw_min : 4; 9032 } s; 9033 /* struct ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg0_s cn; */ 9034 }; 9035 typedef union ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg0 ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg0_t; 9036 9037 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0(uint64_t a) __attribute__ ((pure, always_inline)); 9038 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0(uint64_t a) 9039 { 9040 if (a <= 19) 9041 return 0x87e1b0200d14ll + 0x1000000ll * ((a) & 0x1f); 9042 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0", 1, a, 0, 0, 0, 0, 0); 9043 } 9044 9045 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg0_t 9046 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0(a) CSR_TYPE_RSL32b 9047 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0" 9048 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0(a) 0x0 /* PF_BAR0 */ 9049 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0(a) (a) 9050 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG0(a) (a), -1, -1, -1 9051 9052 /** 9053 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_crcpartmg1 9054 * 9055 * DSS Ddrctl Regb Freq0 Ch0 Crcpartmg1 Register 9056 * CRC Parity Timing 1 9057 */ 9058 union ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg1 { 9059 uint32_t u; 9060 struct ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg1_s { 9061 uint32_t t_csalt : 5; 9062 uint32_t reserved_5_31 : 27; 9063 } s; 9064 /* struct ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg1_s cn; */ 9065 }; 9066 typedef union ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg1 ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg1_t; 9067 9068 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1(uint64_t a) __attribute__ ((pure, always_inline)); 9069 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1(uint64_t a) 9070 { 9071 if (a <= 19) 9072 return 0x87e1b0200d18ll + 0x1000000ll * ((a) & 0x1f); 9073 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1", 1, a, 0, 0, 0, 0, 0); 9074 } 9075 9076 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1(a) ody_dssx_ddrctl_regb_freq0_ch0_crcpartmg1_t 9077 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1(a) CSR_TYPE_RSL32b 9078 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1" 9079 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1(a) 0x0 /* PF_BAR0 */ 9080 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1(a) (a) 9081 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_CRCPARTMG1(a) (a), -1, -1, -1 9082 9083 /** 9084 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dfilptmg0 9085 * 9086 * DSS Ddrctl Regb Freq0 Ch0 Dfilptmg0 Register 9087 * DFI Low Power Timing Register 0 9088 */ 9089 union ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg0 { 9090 uint32_t u; 9091 struct ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg0_s { 9092 uint32_t dfi_lp_wakeup_pd : 5; 9093 uint32_t reserved_5_7 : 3; 9094 uint32_t dfi_lp_wakeup_sr : 5; 9095 uint32_t reserved_13_31 : 19; 9096 } s; 9097 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg0_s cn; */ 9098 }; 9099 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg0 ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg0_t; 9100 9101 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0(uint64_t a) __attribute__ ((pure, always_inline)); 9102 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0(uint64_t a) 9103 { 9104 if (a <= 19) 9105 return 0x87e1b02005a0ll + 0x1000000ll * ((a) & 0x1f); 9106 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0", 1, a, 0, 0, 0, 0, 0); 9107 } 9108 9109 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg0_t 9110 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0(a) CSR_TYPE_RSL32b 9111 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0" 9112 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0(a) 0x0 /* PF_BAR0 */ 9113 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0(a) (a) 9114 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG0(a) (a), -1, -1, -1 9115 9116 /** 9117 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dfilptmg1 9118 * 9119 * DSS Ddrctl Regb Freq0 Ch0 Dfilptmg1 Register 9120 * DFI Low Power Timing Register 1 9121 */ 9122 union ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg1 { 9123 uint32_t u; 9124 struct ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg1_s { 9125 uint32_t reserved_0_7 : 8; 9126 uint32_t dfi_tlp_resp : 5; 9127 uint32_t reserved_13_31 : 19; 9128 } s; 9129 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg1_s cn; */ 9130 }; 9131 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg1 ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg1_t; 9132 9133 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1(uint64_t a) __attribute__ ((pure, always_inline)); 9134 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1(uint64_t a) 9135 { 9136 if (a <= 19) 9137 return 0x87e1b02005a4ll + 0x1000000ll * ((a) & 0x1f); 9138 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1", 1, a, 0, 0, 0, 0, 0); 9139 } 9140 9141 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1(a) ody_dssx_ddrctl_regb_freq0_ch0_dfilptmg1_t 9142 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1(a) CSR_TYPE_RSL32b 9143 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1" 9144 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1(a) 0x0 /* PF_BAR0 */ 9145 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1(a) (a) 9146 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFILPTMG1(a) (a), -1, -1, -1 9147 9148 /** 9149 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dfitmg0 9150 * 9151 * DSS Ddrctl Regb Freq0 Ch0 Dfitmg0 Register 9152 * DFI Timing Register 0 9153 */ 9154 union ody_dssx_ddrctl_regb_freq0_ch0_dfitmg0 { 9155 uint32_t u; 9156 struct ody_dssx_ddrctl_regb_freq0_ch0_dfitmg0_s { 9157 uint32_t dfi_tphy_wrlat : 7; 9158 uint32_t reserved_7 : 1; 9159 uint32_t dfi_tphy_wrdata : 6; 9160 uint32_t reserved_14_15 : 2; 9161 uint32_t dfi_t_rddata_en : 7; 9162 uint32_t reserved_23 : 1; 9163 uint32_t dfi_t_ctrl_delay : 5; 9164 uint32_t reserved_29_31 : 3; 9165 } s; 9166 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dfitmg0_s cn; */ 9167 }; 9168 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dfitmg0 ody_dssx_ddrctl_regb_freq0_ch0_dfitmg0_t; 9169 9170 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0(uint64_t a) __attribute__ ((pure, always_inline)); 9171 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0(uint64_t a) 9172 { 9173 if (a <= 19) 9174 return 0x87e1b0200580ll + 0x1000000ll * ((a) & 0x1f); 9175 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0", 1, a, 0, 0, 0, 0, 0); 9176 } 9177 9178 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_dfitmg0_t 9179 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0(a) CSR_TYPE_RSL32b 9180 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0" 9181 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0(a) 0x0 /* PF_BAR0 */ 9182 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0(a) (a) 9183 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG0(a) (a), -1, -1, -1 9184 9185 /** 9186 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dfitmg1 9187 * 9188 * DSS Ddrctl Regb Freq0 Ch0 Dfitmg1 Register 9189 * DFI Timing Register 1 9190 */ 9191 union ody_dssx_ddrctl_regb_freq0_ch0_dfitmg1 { 9192 uint32_t u; 9193 struct ody_dssx_ddrctl_regb_freq0_ch0_dfitmg1_s { 9194 uint32_t dfi_t_dram_clk_enable : 5; 9195 uint32_t reserved_5_7 : 3; 9196 uint32_t dfi_t_dram_clk_disable : 5; 9197 uint32_t reserved_13_15 : 3; 9198 uint32_t dfi_t_wrdata_delay : 5; 9199 uint32_t reserved_21_31 : 11; 9200 } s; 9201 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dfitmg1_s cn; */ 9202 }; 9203 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dfitmg1 ody_dssx_ddrctl_regb_freq0_ch0_dfitmg1_t; 9204 9205 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1(uint64_t a) __attribute__ ((pure, always_inline)); 9206 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1(uint64_t a) 9207 { 9208 if (a <= 19) 9209 return 0x87e1b0200584ll + 0x1000000ll * ((a) & 0x1f); 9210 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1", 1, a, 0, 0, 0, 0, 0); 9211 } 9212 9213 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1(a) ody_dssx_ddrctl_regb_freq0_ch0_dfitmg1_t 9214 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1(a) CSR_TYPE_RSL32b 9215 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1" 9216 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1(a) 0x0 /* PF_BAR0 */ 9217 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1(a) (a) 9218 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG1(a) (a), -1, -1, -1 9219 9220 /** 9221 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dfitmg2 9222 * 9223 * DSS Ddrctl Regb Freq0 Ch0 Dfitmg2 Register 9224 * DFI Timing Register 2 9225 */ 9226 union ody_dssx_ddrctl_regb_freq0_ch0_dfitmg2 { 9227 uint32_t u; 9228 struct ody_dssx_ddrctl_regb_freq0_ch0_dfitmg2_s { 9229 uint32_t dfi_tphy_wrcslat : 7; 9230 uint32_t reserved_7 : 1; 9231 uint32_t dfi_tphy_rdcslat : 7; 9232 uint32_t reserved_15_31 : 17; 9233 } s; 9234 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dfitmg2_s cn; */ 9235 }; 9236 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dfitmg2 ody_dssx_ddrctl_regb_freq0_ch0_dfitmg2_t; 9237 9238 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2(uint64_t a) __attribute__ ((pure, always_inline)); 9239 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2(uint64_t a) 9240 { 9241 if (a <= 19) 9242 return 0x87e1b0200588ll + 0x1000000ll * ((a) & 0x1f); 9243 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2", 1, a, 0, 0, 0, 0, 0); 9244 } 9245 9246 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2(a) ody_dssx_ddrctl_regb_freq0_ch0_dfitmg2_t 9247 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2(a) CSR_TYPE_RSL32b 9248 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2" 9249 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2(a) 0x0 /* PF_BAR0 */ 9250 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2(a) (a) 9251 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG2(a) (a), -1, -1, -1 9252 9253 /** 9254 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dfitmg7 9255 * 9256 * DSS Ddrctl Regb Freq0 Ch0 Dfitmg7 Register 9257 * DFI Timing Register 7 9258 */ 9259 union ody_dssx_ddrctl_regb_freq0_ch0_dfitmg7 { 9260 uint32_t u; 9261 struct ody_dssx_ddrctl_regb_freq0_ch0_dfitmg7_s { 9262 uint32_t dfi_t_2n_mode_delay : 5; 9263 uint32_t dfi_t_init_start : 12; 9264 uint32_t dfi_t_init_complete : 15; 9265 } s; 9266 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dfitmg7_s cn; */ 9267 }; 9268 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dfitmg7 ody_dssx_ddrctl_regb_freq0_ch0_dfitmg7_t; 9269 9270 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7(uint64_t a) __attribute__ ((pure, always_inline)); 9271 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7(uint64_t a) 9272 { 9273 if (a <= 19) 9274 return 0x87e1b020059cll + 0x1000000ll * ((a) & 0x1f); 9275 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7", 1, a, 0, 0, 0, 0, 0); 9276 } 9277 9278 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7(a) ody_dssx_ddrctl_regb_freq0_ch0_dfitmg7_t 9279 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7(a) CSR_TYPE_RSL32b 9280 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7" 9281 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7(a) 0x0 /* PF_BAR0 */ 9282 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7(a) (a) 9283 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFITMG7(a) (a), -1, -1, -1 9284 9285 /** 9286 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dfiupdtmg0 9287 * 9288 * DSS Ddrctl Regb Freq0 Ch0 Dfiupdtmg0 Register 9289 * DFI Update Timing Register 0 9290 */ 9291 union ody_dssx_ddrctl_regb_freq0_ch0_dfiupdtmg0 { 9292 uint32_t u; 9293 struct ody_dssx_ddrctl_regb_freq0_ch0_dfiupdtmg0_s { 9294 uint32_t dfi_t_ctrlup_min : 10; 9295 uint32_t reserved_10_15 : 6; 9296 uint32_t dfi_t_ctrlup_max : 10; 9297 uint32_t reserved_26_31 : 6; 9298 } s; 9299 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dfiupdtmg0_s cn; */ 9300 }; 9301 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dfiupdtmg0 ody_dssx_ddrctl_regb_freq0_ch0_dfiupdtmg0_t; 9302 9303 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0(uint64_t a) __attribute__ ((pure, always_inline)); 9304 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0(uint64_t a) 9305 { 9306 if (a <= 19) 9307 return 0x87e1b02005a8ll + 0x1000000ll * ((a) & 0x1f); 9308 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0", 1, a, 0, 0, 0, 0, 0); 9309 } 9310 9311 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_dfiupdtmg0_t 9312 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0(a) CSR_TYPE_RSL32b 9313 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0" 9314 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0(a) 0x0 /* PF_BAR0 */ 9315 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0(a) (a) 9316 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DFIUPDTMG0(a) (a), -1, -1, -1 9317 9318 /** 9319 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg0 9320 * 9321 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg0 Register 9322 * SDRAM Timing Register 0 belonging to Timing Set 1 9323 */ 9324 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg0 { 9325 uint32_t u; 9326 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg0_s { 9327 uint32_t t_ras_min : 8; 9328 uint32_t reserved_8_15 : 8; 9329 uint32_t t_faw : 8; 9330 uint32_t wr2pre : 8; 9331 } s; 9332 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg0_s cn; */ 9333 }; 9334 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg0 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg0_t; 9335 9336 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0(uint64_t a) __attribute__ ((pure, always_inline)); 9337 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0(uint64_t a) 9338 { 9339 if (a <= 19) 9340 return 0x87e1b0200000ll + 0x1000000ll * ((a) & 0x1f); 9341 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0", 1, a, 0, 0, 0, 0, 0); 9342 } 9343 9344 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg0_t 9345 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0(a) CSR_TYPE_RSL32b 9346 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0" 9347 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0(a) 0x0 /* PF_BAR0 */ 9348 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0(a) (a) 9349 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG0(a) (a), -1, -1, -1 9350 9351 /** 9352 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg1 9353 * 9354 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg1 Register 9355 * SDRAM Timing Register 1 belonging to Timing Set 1 9356 */ 9357 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg1 { 9358 uint32_t u; 9359 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg1_s { 9360 uint32_t t_rc : 8; 9361 uint32_t rd2pre : 8; 9362 uint32_t t_xp : 6; 9363 uint32_t reserved_22_31 : 10; 9364 } s; 9365 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg1_s cn; */ 9366 }; 9367 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg1 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg1_t; 9368 9369 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1(uint64_t a) __attribute__ ((pure, always_inline)); 9370 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1(uint64_t a) 9371 { 9372 if (a <= 19) 9373 return 0x87e1b0200004ll + 0x1000000ll * ((a) & 0x1f); 9374 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1", 1, a, 0, 0, 0, 0, 0); 9375 } 9376 9377 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg1_t 9378 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1(a) CSR_TYPE_RSL32b 9379 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1" 9380 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1(a) 0x0 /* PF_BAR0 */ 9381 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1(a) (a) 9382 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG1(a) (a), -1, -1, -1 9383 9384 /** 9385 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg13 9386 * 9387 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg13 Register 9388 * SDRAM Timing Register 13 belonging to Timing Set 1 9389 */ 9390 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg13 { 9391 uint32_t u; 9392 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg13_s { 9393 uint32_t t_ppd : 4; 9394 uint32_t t_ccd_w2 : 8; 9395 uint32_t reserved_12_31 : 20; 9396 } s; 9397 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg13_s cn; */ 9398 }; 9399 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg13 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg13_t; 9400 9401 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13(uint64_t a) __attribute__ ((pure, always_inline)); 9402 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13(uint64_t a) 9403 { 9404 if (a <= 19) 9405 return 0x87e1b0200034ll + 0x1000000ll * ((a) & 0x1f); 9406 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13", 1, a, 0, 0, 0, 0, 0); 9407 } 9408 9409 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg13_t 9410 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13(a) CSR_TYPE_RSL32b 9411 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13" 9412 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13(a) 0x0 /* PF_BAR0 */ 9413 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13(a) (a) 9414 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG13(a) (a), -1, -1, -1 9415 9416 /** 9417 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg15 9418 * 9419 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg15 Register 9420 * SDRAM Timing Register 15 belonging to Timing Set 1 9421 */ 9422 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg15 { 9423 uint32_t u; 9424 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg15_s { 9425 uint32_t t_stab_x32 : 10; 9426 uint32_t reserved_10_31 : 22; 9427 } s; 9428 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg15_s cn; */ 9429 }; 9430 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg15 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg15_t; 9431 9432 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15(uint64_t a) __attribute__ ((pure, always_inline)); 9433 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15(uint64_t a) 9434 { 9435 if (a <= 19) 9436 return 0x87e1b020003cll + 0x1000000ll * ((a) & 0x1f); 9437 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15", 1, a, 0, 0, 0, 0, 0); 9438 } 9439 9440 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg15_t 9441 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15(a) CSR_TYPE_RSL32b 9442 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15" 9443 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15(a) 0x0 /* PF_BAR0 */ 9444 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15(a) (a) 9445 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG15(a) (a), -1, -1, -1 9446 9447 /** 9448 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg18 9449 * 9450 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg18 Register 9451 * SDRAM Timing Register 18 belonging to Timing Set 1 9452 */ 9453 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg18 { 9454 uint32_t u; 9455 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg18_s { 9456 uint32_t reserved_0_15 : 16; 9457 uint32_t t_mpsmx : 7; 9458 uint32_t reserved_23 : 1; 9459 uint32_t t_pd : 7; 9460 uint32_t reserved_31 : 1; 9461 } s; 9462 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg18_s cn; */ 9463 }; 9464 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg18 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg18_t; 9465 9466 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18(uint64_t a) __attribute__ ((pure, always_inline)); 9467 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18(uint64_t a) 9468 { 9469 if (a <= 19) 9470 return 0x87e1b0200048ll + 0x1000000ll * ((a) & 0x1f); 9471 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18", 1, a, 0, 0, 0, 0, 0); 9472 } 9473 9474 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg18_t 9475 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18(a) CSR_TYPE_RSL32b 9476 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18" 9477 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18(a) 0x0 /* PF_BAR0 */ 9478 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18(a) (a) 9479 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG18(a) (a), -1, -1, -1 9480 9481 /** 9482 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg2 9483 * 9484 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg2 Register 9485 * SDRAM Timing Register 2 belonging to Timing Set 1 9486 */ 9487 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg2 { 9488 uint32_t u; 9489 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg2_s { 9490 uint32_t wr2rd : 8; 9491 uint32_t rd2wr : 8; 9492 uint32_t read_latency : 7; 9493 uint32_t reserved_23_31 : 9; 9494 } s; 9495 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg2_s cn; */ 9496 }; 9497 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg2 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg2_t; 9498 9499 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2(uint64_t a) __attribute__ ((pure, always_inline)); 9500 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2(uint64_t a) 9501 { 9502 if (a <= 19) 9503 return 0x87e1b0200008ll + 0x1000000ll * ((a) & 0x1f); 9504 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2", 1, a, 0, 0, 0, 0, 0); 9505 } 9506 9507 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg2_t 9508 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2(a) CSR_TYPE_RSL32b 9509 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2" 9510 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2(a) 0x0 /* PF_BAR0 */ 9511 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2(a) (a) 9512 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG2(a) (a), -1, -1, -1 9513 9514 /** 9515 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg20 9516 * 9517 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg20 Register 9518 * SDRAM Timing Register 20 belonging to Timing Set 1 9519 */ 9520 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg20 { 9521 uint32_t u; 9522 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg20_s { 9523 uint32_t t_csl_srexit : 5; 9524 uint32_t reserved_5_7 : 3; 9525 uint32_t t_csh_srexit : 7; 9526 uint32_t reserved_15 : 1; 9527 uint32_t t_casrx : 5; 9528 uint32_t reserved_21_23 : 3; 9529 uint32_t t_cpded : 6; 9530 uint32_t reserved_30_31 : 2; 9531 } s; 9532 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg20_s cn; */ 9533 }; 9534 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg20 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg20_t; 9535 9536 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20(uint64_t a) __attribute__ ((pure, always_inline)); 9537 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20(uint64_t a) 9538 { 9539 if (a <= 19) 9540 return 0x87e1b0200050ll + 0x1000000ll * ((a) & 0x1f); 9541 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20", 1, a, 0, 0, 0, 0, 0); 9542 } 9543 9544 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg20_t 9545 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20(a) CSR_TYPE_RSL32b 9546 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20" 9547 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20(a) 0x0 /* PF_BAR0 */ 9548 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20(a) (a) 9549 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG20(a) (a), -1, -1, -1 9550 9551 /** 9552 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg21 9553 * 9554 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg21 Register 9555 * SDRAM Timing Register 21 belonging to Timing Set 1 9556 */ 9557 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg21 { 9558 uint32_t u; 9559 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg21_s { 9560 uint32_t reserved_0_13 : 14; 9561 uint32_t t_mpc_hold : 3; 9562 uint32_t t_mpc_setup : 3; 9563 uint32_t t_mpc_cs : 5; 9564 uint32_t t_csl : 7; 9565 } s; 9566 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg21_s cn; */ 9567 }; 9568 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg21 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg21_t; 9569 9570 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21(uint64_t a) __attribute__ ((pure, always_inline)); 9571 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21(uint64_t a) 9572 { 9573 if (a <= 19) 9574 return 0x87e1b0200054ll + 0x1000000ll * ((a) & 0x1f); 9575 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21", 1, a, 0, 0, 0, 0, 0); 9576 } 9577 9578 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg21_t 9579 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21(a) CSR_TYPE_RSL32b 9580 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21" 9581 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21(a) 0x0 /* PF_BAR0 */ 9582 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21(a) (a) 9583 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG21(a) (a), -1, -1, -1 9584 9585 /** 9586 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg22 9587 * 9588 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg22 Register 9589 * SDRAM Timing Register 22 belonging to Timing Set 1 9590 */ 9591 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg22 { 9592 uint32_t u; 9593 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg22_s { 9594 uint32_t t_rd2wr_dpr : 7; 9595 uint32_t t_rd2wr_dlr : 7; 9596 uint32_t t_wr2rd_dpr : 8; 9597 uint32_t t_wr2rd_dlr : 8; 9598 uint32_t reserved_30_31 : 2; 9599 } s; 9600 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg22_s cn; */ 9601 }; 9602 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg22 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg22_t; 9603 9604 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22(uint64_t a) __attribute__ ((pure, always_inline)); 9605 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22(uint64_t a) 9606 { 9607 if (a <= 19) 9608 return 0x87e1b0200058ll + 0x1000000ll * ((a) & 0x1f); 9609 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22", 1, a, 0, 0, 0, 0, 0); 9610 } 9611 9612 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg22_t 9613 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22(a) CSR_TYPE_RSL32b 9614 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22" 9615 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22(a) 0x0 /* PF_BAR0 */ 9616 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22(a) (a) 9617 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG22(a) (a), -1, -1, -1 9618 9619 /** 9620 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg26 9621 * 9622 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg26 Register 9623 * SDRAM Timing Register 26 belonging to Timing Set 1 9624 */ 9625 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg26 { 9626 uint32_t u; 9627 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg26_s { 9628 uint32_t t_ccd_r : 8; 9629 uint32_t t_ccd_w : 8; 9630 uint32_t t_ccd_r_s : 8; 9631 uint32_t t_ccd_w_s : 8; 9632 } s; 9633 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg26_s cn; */ 9634 }; 9635 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg26 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg26_t; 9636 9637 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26(uint64_t a) __attribute__ ((pure, always_inline)); 9638 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26(uint64_t a) 9639 { 9640 if (a <= 19) 9641 return 0x87e1b0200068ll + 0x1000000ll * ((a) & 0x1f); 9642 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26", 1, a, 0, 0, 0, 0, 0); 9643 } 9644 9645 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg26_t 9646 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26(a) CSR_TYPE_RSL32b 9647 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26" 9648 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26(a) 0x0 /* PF_BAR0 */ 9649 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26(a) (a) 9650 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG26(a) (a), -1, -1, -1 9651 9652 /** 9653 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg27 9654 * 9655 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg27 Register 9656 * SDRAM Timing Register 27 belonging to Timing Set 1 9657 */ 9658 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg27 { 9659 uint32_t u; 9660 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg27_s { 9661 uint32_t t_mrr2mpc : 8; 9662 uint32_t reserved_8_15 : 8; 9663 uint32_t t_ecsc : 9; 9664 uint32_t reserved_25_31 : 7; 9665 } s; 9666 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg27_s cn; */ 9667 }; 9668 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg27 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg27_t; 9669 9670 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27(uint64_t a) __attribute__ ((pure, always_inline)); 9671 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27(uint64_t a) 9672 { 9673 if (a <= 19) 9674 return 0x87e1b020006cll + 0x1000000ll * ((a) & 0x1f); 9675 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27", 1, a, 0, 0, 0, 0, 0); 9676 } 9677 9678 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg27_t 9679 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27(a) CSR_TYPE_RSL32b 9680 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27" 9681 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27(a) 0x0 /* PF_BAR0 */ 9682 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27(a) (a) 9683 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG27(a) (a), -1, -1, -1 9684 9685 /** 9686 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg28 9687 * 9688 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg28 Register 9689 * SDRAM Timing Register 28 belonging to Timing Set 1 9690 */ 9691 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg28 { 9692 uint32_t u; 9693 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg28_s { 9694 uint32_t t_srx2srx : 7; 9695 uint32_t reserved_7 : 1; 9696 uint32_t t_cpded2srx : 7; 9697 uint32_t reserved_15 : 1; 9698 uint32_t t_cssr : 7; 9699 uint32_t reserved_23_31 : 9; 9700 } s; 9701 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg28_s cn; */ 9702 }; 9703 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg28 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg28_t; 9704 9705 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28(uint64_t a) __attribute__ ((pure, always_inline)); 9706 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28(uint64_t a) 9707 { 9708 if (a <= 19) 9709 return 0x87e1b0200070ll + 0x1000000ll * ((a) & 0x1f); 9710 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28", 1, a, 0, 0, 0, 0, 0); 9711 } 9712 9713 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg28_t 9714 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28(a) CSR_TYPE_RSL32b 9715 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28" 9716 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28(a) 0x0 /* PF_BAR0 */ 9717 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28(a) (a) 9718 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG28(a) (a), -1, -1, -1 9719 9720 /** 9721 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg29 9722 * 9723 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg29 Register 9724 * SDRAM Timing Register 29 belonging to Timing Set 1 9725 */ 9726 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg29 { 9727 uint32_t u; 9728 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg29_s { 9729 uint32_t reserved_0_15 : 16; 9730 uint32_t t_ckact : 6; 9731 uint32_t reserved_22_23 : 2; 9732 uint32_t t_ckoff : 7; 9733 uint32_t reserved_31 : 1; 9734 } s; 9735 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg29_s cn; */ 9736 }; 9737 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg29 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg29_t; 9738 9739 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29(uint64_t a) __attribute__ ((pure, always_inline)); 9740 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29(uint64_t a) 9741 { 9742 if (a <= 19) 9743 return 0x87e1b0200074ll + 0x1000000ll * ((a) & 0x1f); 9744 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29", 1, a, 0, 0, 0, 0, 0); 9745 } 9746 9747 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg29_t 9748 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29(a) CSR_TYPE_RSL32b 9749 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29" 9750 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29(a) 0x0 /* PF_BAR0 */ 9751 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29(a) (a) 9752 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG29(a) (a), -1, -1, -1 9753 9754 /** 9755 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg3 9756 * 9757 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg3 Register 9758 * SDRAM Timing Register 3 belonging to Timing Set 1 9759 */ 9760 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg3 { 9761 uint32_t u; 9762 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg3_s { 9763 uint32_t reserved_0_15 : 16; 9764 uint32_t t_mr : 7; 9765 uint32_t reserved_23_31 : 9; 9766 } s; 9767 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg3_s cn; */ 9768 }; 9769 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg3 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg3_t; 9770 9771 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3(uint64_t a) __attribute__ ((pure, always_inline)); 9772 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3(uint64_t a) 9773 { 9774 if (a <= 19) 9775 return 0x87e1b020000cll + 0x1000000ll * ((a) & 0x1f); 9776 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3", 1, a, 0, 0, 0, 0, 0); 9777 } 9778 9779 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg3_t 9780 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3(a) CSR_TYPE_RSL32b 9781 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3" 9782 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3(a) 0x0 /* PF_BAR0 */ 9783 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3(a) (a) 9784 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG3(a) (a), -1, -1, -1 9785 9786 /** 9787 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg31 9788 * 9789 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg31 Register 9790 * SDRAM Timing Register 31 belonging to Timing Set 1 9791 */ 9792 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg31 { 9793 uint32_t u; 9794 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg31_s { 9795 uint32_t rfm_raaimt : 7; 9796 uint32_t reserved_7_8 : 2; 9797 uint32_t rfm_raa_thr : 9; 9798 uint32_t reserved_18 : 1; 9799 uint32_t rfm_raa_ref_decr : 2; 9800 uint32_t reserved_21_31 : 11; 9801 } s; 9802 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg31_s cn; */ 9803 }; 9804 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg31 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg31_t; 9805 9806 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31(uint64_t a) __attribute__ ((pure, always_inline)); 9807 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31(uint64_t a) 9808 { 9809 if (a <= 19) 9810 return 0x87e1b020007cll + 0x1000000ll * ((a) & 0x1f); 9811 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31", 1, a, 0, 0, 0, 0, 0); 9812 } 9813 9814 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg31_t 9815 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31(a) CSR_TYPE_RSL32b 9816 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31" 9817 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31(a) 0x0 /* PF_BAR0 */ 9818 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31(a) (a) 9819 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG31(a) (a), -1, -1, -1 9820 9821 /** 9822 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg4 9823 * 9824 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg4 Register 9825 * SDRAM Timing Register 4 belonging to Timing Set 1 9826 */ 9827 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg4 { 9828 uint32_t u; 9829 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg4_s { 9830 uint32_t t_rp : 7; 9831 uint32_t reserved_7 : 1; 9832 uint32_t t_rrd : 6; 9833 uint32_t reserved_14_23 : 10; 9834 uint32_t t_rcd : 8; 9835 } s; 9836 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg4_s cn; */ 9837 }; 9838 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg4 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg4_t; 9839 9840 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4(uint64_t a) __attribute__ ((pure, always_inline)); 9841 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4(uint64_t a) 9842 { 9843 if (a <= 19) 9844 return 0x87e1b0200010ll + 0x1000000ll * ((a) & 0x1f); 9845 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4", 1, a, 0, 0, 0, 0, 0); 9846 } 9847 9848 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg4_t 9849 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4(a) CSR_TYPE_RSL32b 9850 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4" 9851 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4(a) 0x0 /* PF_BAR0 */ 9852 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4(a) (a) 9853 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG4(a) (a), -1, -1, -1 9854 9855 /** 9856 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg5 9857 * 9858 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg5 Register 9859 * SDRAM Timing Register 5 belonging to Timing Set 1 9860 */ 9861 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg5 { 9862 uint32_t u; 9863 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg5_s { 9864 uint32_t reserved_0_15 : 16; 9865 uint32_t t_cksre : 7; 9866 uint32_t reserved_23 : 1; 9867 uint32_t t_cksrx : 6; 9868 uint32_t reserved_30_31 : 2; 9869 } s; 9870 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg5_s cn; */ 9871 }; 9872 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg5 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg5_t; 9873 9874 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5(uint64_t a) __attribute__ ((pure, always_inline)); 9875 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5(uint64_t a) 9876 { 9877 if (a <= 19) 9878 return 0x87e1b0200014ll + 0x1000000ll * ((a) & 0x1f); 9879 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5", 1, a, 0, 0, 0, 0, 0); 9880 } 9881 9882 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg5_t 9883 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5(a) CSR_TYPE_RSL32b 9884 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5" 9885 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5(a) 0x0 /* PF_BAR0 */ 9886 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5(a) (a) 9887 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG5(a) (a), -1, -1, -1 9888 9889 /** 9890 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg8 9891 * 9892 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg8 Register 9893 * SDRAM Timing Register 8 belonging to Timing Set 1 9894 */ 9895 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg8 { 9896 uint32_t u; 9897 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg8_s { 9898 uint32_t t_xs_x32 : 7; 9899 uint32_t reserved_7 : 1; 9900 uint32_t t_xs_dll_x32 : 7; 9901 uint32_t reserved_15_31 : 17; 9902 } s; 9903 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg8_s cn; */ 9904 }; 9905 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg8 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg8_t; 9906 9907 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8(uint64_t a) __attribute__ ((pure, always_inline)); 9908 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8(uint64_t a) 9909 { 9910 if (a <= 19) 9911 return 0x87e1b0200020ll + 0x1000000ll * ((a) & 0x1f); 9912 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8", 1, a, 0, 0, 0, 0, 0); 9913 } 9914 9915 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg8_t 9916 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8(a) CSR_TYPE_RSL32b 9917 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8" 9918 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8(a) 0x0 /* PF_BAR0 */ 9919 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8(a) (a) 9920 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG8(a) (a), -1, -1, -1 9921 9922 /** 9923 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_dramset1tmg9 9924 * 9925 * DSS Ddrctl Regb Freq0 Ch0 Dramset1tmg9 Register 9926 * SDRAM Timing Register 9 belonging to Timing Set 1 9927 */ 9928 union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg9 { 9929 uint32_t u; 9930 struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg9_s { 9931 uint32_t wr2rd_s : 8; 9932 uint32_t t_rrd_s : 6; 9933 uint32_t reserved_14_31 : 18; 9934 } s; 9935 /* struct ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg9_s cn; */ 9936 }; 9937 typedef union ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg9 ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg9_t; 9938 9939 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9(uint64_t a) __attribute__ ((pure, always_inline)); 9940 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9(uint64_t a) 9941 { 9942 if (a <= 19) 9943 return 0x87e1b0200024ll + 0x1000000ll * ((a) & 0x1f); 9944 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9", 1, a, 0, 0, 0, 0, 0); 9945 } 9946 9947 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9(a) ody_dssx_ddrctl_regb_freq0_ch0_dramset1tmg9_t 9948 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9(a) CSR_TYPE_RSL32b 9949 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9" 9950 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9(a) 0x0 /* PF_BAR0 */ 9951 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9(a) (a) 9952 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_DRAMSET1TMG9(a) (a), -1, -1, -1 9953 9954 /** 9955 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_ecsset1tmg0 9956 * 9957 * DSS Ddrctl Regb Freq0 Ch0 Ecsset1tmg0 Register 9958 * ECS Timing Register 0 belonging to Timing Set 1 9959 */ 9960 union ody_dssx_ddrctl_regb_freq0_ch0_ecsset1tmg0 { 9961 uint32_t u; 9962 struct ody_dssx_ddrctl_regb_freq0_ch0_ecsset1tmg0_s { 9963 uint32_t t_ecs_int_x1024 : 12; 9964 uint32_t reserved_12_15 : 4; 9965 uint32_t t_refi_ecs_offset_x1_x32 : 8; 9966 uint32_t reserved_24_31 : 8; 9967 } s; 9968 /* struct ody_dssx_ddrctl_regb_freq0_ch0_ecsset1tmg0_s cn; */ 9969 }; 9970 typedef union ody_dssx_ddrctl_regb_freq0_ch0_ecsset1tmg0 ody_dssx_ddrctl_regb_freq0_ch0_ecsset1tmg0_t; 9971 9972 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0(uint64_t a) __attribute__ ((pure, always_inline)); 9973 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0(uint64_t a) 9974 { 9975 if (a <= 19) 9976 return 0x87e1b0200640ll + 0x1000000ll * ((a) & 0x1f); 9977 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0", 1, a, 0, 0, 0, 0, 0); 9978 } 9979 9980 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_ecsset1tmg0_t 9981 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0(a) CSR_TYPE_RSL32b 9982 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0" 9983 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0(a) 0x0 /* PF_BAR0 */ 9984 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0(a) (a) 9985 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ECSSET1TMG0(a) (a), -1, -1, -1 9986 9987 /** 9988 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_hwlptmg0 9989 * 9990 * DSS Ddrctl Regb Freq0 Ch0 Hwlptmg0 Register 9991 * Hardware Low Power Control Register 9992 */ 9993 union ody_dssx_ddrctl_regb_freq0_ch0_hwlptmg0 { 9994 uint32_t u; 9995 struct ody_dssx_ddrctl_regb_freq0_ch0_hwlptmg0_s { 9996 uint32_t reserved_0_15 : 16; 9997 uint32_t hw_lp_idle_x32 : 12; 9998 uint32_t reserved_28_31 : 4; 9999 } s; 10000 /* struct ody_dssx_ddrctl_regb_freq0_ch0_hwlptmg0_s cn; */ 10001 }; 10002 typedef union ody_dssx_ddrctl_regb_freq0_ch0_hwlptmg0 ody_dssx_ddrctl_regb_freq0_ch0_hwlptmg0_t; 10003 10004 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0(uint64_t a) __attribute__ ((pure, always_inline)); 10005 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0(uint64_t a) 10006 { 10007 if (a <= 19) 10008 return 0x87e1b0200b80ll + 0x1000000ll * ((a) & 0x1f); 10009 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0", 1, a, 0, 0, 0, 0, 0); 10010 } 10011 10012 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_hwlptmg0_t 10013 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0(a) CSR_TYPE_RSL32b 10014 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0" 10015 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0(a) 0x0 /* PF_BAR0 */ 10016 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0(a) (a) 10017 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_HWLPTMG0(a) (a), -1, -1, -1 10018 10019 /** 10020 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_perfhpr1 10021 * 10022 * DSS Ddrctl Regb Freq0 Ch0 Perfhpr1 Register 10023 * High Priority Read CAM Register 1 10024 */ 10025 union ody_dssx_ddrctl_regb_freq0_ch0_perfhpr1 { 10026 uint32_t u; 10027 struct ody_dssx_ddrctl_regb_freq0_ch0_perfhpr1_s { 10028 uint32_t hpr_max_starve : 16; 10029 uint32_t reserved_16_23 : 8; 10030 uint32_t hpr_xact_run_length : 8; 10031 } s; 10032 /* struct ody_dssx_ddrctl_regb_freq0_ch0_perfhpr1_s cn; */ 10033 }; 10034 typedef union ody_dssx_ddrctl_regb_freq0_ch0_perfhpr1 ody_dssx_ddrctl_regb_freq0_ch0_perfhpr1_t; 10035 10036 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1(uint64_t a) __attribute__ ((pure, always_inline)); 10037 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1(uint64_t a) 10038 { 10039 if (a <= 19) 10040 return 0x87e1b0200c80ll + 0x1000000ll * ((a) & 0x1f); 10041 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1", 1, a, 0, 0, 0, 0, 0); 10042 } 10043 10044 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1(a) ody_dssx_ddrctl_regb_freq0_ch0_perfhpr1_t 10045 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1(a) CSR_TYPE_RSL32b 10046 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1" 10047 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1(a) 0x0 /* PF_BAR0 */ 10048 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1(a) (a) 10049 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFHPR1(a) (a), -1, -1, -1 10050 10051 /** 10052 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_perflpr1 10053 * 10054 * DSS Ddrctl Regb Freq0 Ch0 Perflpr1 Register 10055 * Low Priority Read CAM Register 1 10056 */ 10057 union ody_dssx_ddrctl_regb_freq0_ch0_perflpr1 { 10058 uint32_t u; 10059 struct ody_dssx_ddrctl_regb_freq0_ch0_perflpr1_s { 10060 uint32_t lpr_max_starve : 16; 10061 uint32_t reserved_16_23 : 8; 10062 uint32_t lpr_xact_run_length : 8; 10063 } s; 10064 /* struct ody_dssx_ddrctl_regb_freq0_ch0_perflpr1_s cn; */ 10065 }; 10066 typedef union ody_dssx_ddrctl_regb_freq0_ch0_perflpr1 ody_dssx_ddrctl_regb_freq0_ch0_perflpr1_t; 10067 10068 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1(uint64_t a) __attribute__ ((pure, always_inline)); 10069 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1(uint64_t a) 10070 { 10071 if (a <= 19) 10072 return 0x87e1b0200c84ll + 0x1000000ll * ((a) & 0x1f); 10073 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1", 1, a, 0, 0, 0, 0, 0); 10074 } 10075 10076 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1(a) ody_dssx_ddrctl_regb_freq0_ch0_perflpr1_t 10077 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1(a) CSR_TYPE_RSL32b 10078 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1" 10079 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1(a) 0x0 /* PF_BAR0 */ 10080 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1(a) (a) 10081 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFLPR1(a) (a), -1, -1, -1 10082 10083 /** 10084 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_perfwr1 10085 * 10086 * DSS Ddrctl Regb Freq0 Ch0 Perfwr1 Register 10087 * Write CAM Register 1 10088 */ 10089 union ody_dssx_ddrctl_regb_freq0_ch0_perfwr1 { 10090 uint32_t u; 10091 struct ody_dssx_ddrctl_regb_freq0_ch0_perfwr1_s { 10092 uint32_t w_max_starve : 16; 10093 uint32_t reserved_16_23 : 8; 10094 uint32_t w_xact_run_length : 8; 10095 } s; 10096 /* struct ody_dssx_ddrctl_regb_freq0_ch0_perfwr1_s cn; */ 10097 }; 10098 typedef union ody_dssx_ddrctl_regb_freq0_ch0_perfwr1 ody_dssx_ddrctl_regb_freq0_ch0_perfwr1_t; 10099 10100 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1(uint64_t a) __attribute__ ((pure, always_inline)); 10101 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1(uint64_t a) 10102 { 10103 if (a <= 19) 10104 return 0x87e1b0200c88ll + 0x1000000ll * ((a) & 0x1f); 10105 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1", 1, a, 0, 0, 0, 0, 0); 10106 } 10107 10108 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1(a) ody_dssx_ddrctl_regb_freq0_ch0_perfwr1_t 10109 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1(a) CSR_TYPE_RSL32b 10110 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1" 10111 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1(a) 0x0 /* PF_BAR0 */ 10112 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1(a) (a) 10113 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PERFWR1(a) (a), -1, -1, -1 10114 10115 /** 10116 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_pwrtmg 10117 * 10118 * DSS Ddrctl Regb Freq0 Ch0 Pwrtmg Register 10119 * Low Power Timing Register 10120 */ 10121 union ody_dssx_ddrctl_regb_freq0_ch0_pwrtmg { 10122 uint32_t u; 10123 struct ody_dssx_ddrctl_regb_freq0_ch0_pwrtmg_s { 10124 uint32_t powerdown_to_x32 : 7; 10125 uint32_t reserved_7_15 : 9; 10126 uint32_t selfref_to_x32 : 10; 10127 uint32_t reserved_26_31 : 6; 10128 } s; 10129 /* struct ody_dssx_ddrctl_regb_freq0_ch0_pwrtmg_s cn; */ 10130 }; 10131 typedef union ody_dssx_ddrctl_regb_freq0_ch0_pwrtmg ody_dssx_ddrctl_regb_freq0_ch0_pwrtmg_t; 10132 10133 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG(uint64_t a) __attribute__ ((pure, always_inline)); 10134 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG(uint64_t a) 10135 { 10136 if (a <= 19) 10137 return 0x87e1b0200d0cll + 0x1000000ll * ((a) & 0x1f); 10138 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG", 1, a, 0, 0, 0, 0, 0); 10139 } 10140 10141 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG(a) ody_dssx_ddrctl_regb_freq0_ch0_pwrtmg_t 10142 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG(a) CSR_TYPE_RSL32b 10143 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG" 10144 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG(a) 0x0 /* PF_BAR0 */ 10145 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG(a) (a) 10146 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_PWRTMG(a) (a), -1, -1, -1 10147 10148 /** 10149 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_rank_switch_timing_control0 10150 * 10151 * DSS Ddrctl Regb Freq0 Ch0 Rank Switch Timing Control0 Register 10152 * Rank Switching Timing Control 0. 10153 */ 10154 union ody_dssx_ddrctl_regb_freq0_ch0_rank_switch_timing_control0 { 10155 uint32_t u; 10156 struct ody_dssx_ddrctl_regb_freq0_ch0_rank_switch_timing_control0_s { 10157 uint32_t t_rd2rd_gap_r0r1 : 4; 10158 uint32_t t_rd2rd_gap_r1r0 : 4; 10159 uint32_t t_wr2rd_gap_r0r1 : 4; 10160 uint32_t t_wr2rd_gap_r1r0 : 4; 10161 uint32_t t_rd2wr_gap_r0r1 : 4; 10162 uint32_t t_rd2wr_gap_r1r0 : 4; 10163 uint32_t t_wr2wr_gap_r0r1 : 4; 10164 uint32_t t_wr2wr_gap_r1r0 : 4; 10165 } s; 10166 /* struct ody_dssx_ddrctl_regb_freq0_ch0_rank_switch_timing_control0_s cn; */ 10167 }; 10168 typedef union ody_dssx_ddrctl_regb_freq0_ch0_rank_switch_timing_control0 ody_dssx_ddrctl_regb_freq0_ch0_rank_switch_timing_control0_t; 10169 10170 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0(uint64_t a) __attribute__ ((pure, always_inline)); 10171 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0(uint64_t a) 10172 { 10173 if (a <= 19) 10174 return 0x87e1b0200400ll + 0x1000000ll * ((a) & 0x1f); 10175 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0", 1, a, 0, 0, 0, 0, 0); 10176 } 10177 10178 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0(a) ody_dssx_ddrctl_regb_freq0_ch0_rank_switch_timing_control0_t 10179 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0(a) CSR_TYPE_RSL32b 10180 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0" 10181 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0(a) 0x0 /* PF_BAR0 */ 10182 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0(a) (a) 10183 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RANK_SWITCH_TIMING_CONTROL0(a) (a), -1, -1, -1 10184 10185 /** 10186 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_retrytmg0 10187 * 10188 * DSS Ddrctl Regb Freq0 Ch0 Retrytmg0 Register 10189 * RETRY Timing 0 10190 */ 10191 union ody_dssx_ddrctl_regb_freq0_ch0_retrytmg0 { 10192 uint32_t u; 10193 struct ody_dssx_ddrctl_regb_freq0_ch0_retrytmg0_s { 10194 uint32_t capar_retry_window : 6; 10195 uint32_t reserved_6_15 : 10; 10196 uint32_t t_wr_crc_retry_window : 9; 10197 uint32_t reserved_25_31 : 7; 10198 } s; 10199 /* struct ody_dssx_ddrctl_regb_freq0_ch0_retrytmg0_s cn; */ 10200 }; 10201 typedef union ody_dssx_ddrctl_regb_freq0_ch0_retrytmg0 ody_dssx_ddrctl_regb_freq0_ch0_retrytmg0_t; 10202 10203 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0(uint64_t a) __attribute__ ((pure, always_inline)); 10204 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0(uint64_t a) 10205 { 10206 if (a <= 19) 10207 return 0x87e1b0200d20ll + 0x1000000ll * ((a) & 0x1f); 10208 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0", 1, a, 0, 0, 0, 0, 0); 10209 } 10210 10211 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_retrytmg0_t 10212 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0(a) CSR_TYPE_RSL32b 10213 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0" 10214 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0(a) 0x0 /* PF_BAR0 */ 10215 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0(a) (a) 10216 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG0(a) (a), -1, -1, -1 10217 10218 /** 10219 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_retrytmg1 10220 * 10221 * DSS Ddrctl Regb Freq0 Ch0 Retrytmg1 Register 10222 * RETRY Timing 1 10223 */ 10224 union ody_dssx_ddrctl_regb_freq0_ch0_retrytmg1 { 10225 uint32_t u; 10226 struct ody_dssx_ddrctl_regb_freq0_ch0_retrytmg1_s { 10227 uint32_t dfi_t_phy_rdlat : 8; 10228 uint32_t extra_rd_retry_window : 6; 10229 uint32_t reserved_14_15 : 2; 10230 uint32_t retry_add_rd_lat : 5; 10231 uint32_t reserved_21_23 : 3; 10232 uint32_t retry_add_rd_lat_en : 1; 10233 uint32_t reserved_25_31 : 7; 10234 } s; 10235 /* struct ody_dssx_ddrctl_regb_freq0_ch0_retrytmg1_s cn; */ 10236 }; 10237 typedef union ody_dssx_ddrctl_regb_freq0_ch0_retrytmg1 ody_dssx_ddrctl_regb_freq0_ch0_retrytmg1_t; 10238 10239 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1(uint64_t a) __attribute__ ((pure, always_inline)); 10240 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1(uint64_t a) 10241 { 10242 if (a <= 19) 10243 return 0x87e1b0200d24ll + 0x1000000ll * ((a) & 0x1f); 10244 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1", 1, a, 0, 0, 0, 0, 0); 10245 } 10246 10247 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1(a) ody_dssx_ddrctl_regb_freq0_ch0_retrytmg1_t 10248 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1(a) CSR_TYPE_RSL32b 10249 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1" 10250 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1(a) 0x0 /* PF_BAR0 */ 10251 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1(a) (a) 10252 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RETRYTMG1(a) (a), -1, -1, -1 10253 10254 /** 10255 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_rfshset1tmg0 10256 * 10257 * DSS Ddrctl Regb Freq0 Ch0 Rfshset1tmg0 Register 10258 * Refresh Timing Register 0 belonging to Timing Set 1 10259 */ 10260 union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg0 { 10261 uint32_t u; 10262 struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg0_s { 10263 uint32_t t_refi_x1_x32 : 12; 10264 uint32_t reserved_12_15 : 4; 10265 uint32_t refresh_to_x1_x32 : 6; 10266 uint32_t reserved_22_23 : 2; 10267 uint32_t refresh_margin : 4; 10268 uint32_t reserved_28_30 : 3; 10269 uint32_t t_refi_x1_sel : 1; 10270 } s; 10271 /* struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg0_s cn; */ 10272 }; 10273 typedef union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg0 ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg0_t; 10274 10275 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0(uint64_t a) __attribute__ ((pure, always_inline)); 10276 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0(uint64_t a) 10277 { 10278 if (a <= 19) 10279 return 0x87e1b0200600ll + 0x1000000ll * ((a) & 0x1f); 10280 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0", 1, a, 0, 0, 0, 0, 0); 10281 } 10282 10283 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg0_t 10284 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0(a) CSR_TYPE_RSL32b 10285 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0" 10286 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0(a) 0x0 /* PF_BAR0 */ 10287 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0(a) (a) 10288 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG0(a) (a), -1, -1, -1 10289 10290 /** 10291 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_rfshset1tmg1 10292 * 10293 * DSS Ddrctl Regb Freq0 Ch0 Rfshset1tmg1 Register 10294 * Refresh Timing Register 1 belonging to Timing Set 1 10295 */ 10296 union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg1 { 10297 uint32_t u; 10298 struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg1_s { 10299 uint32_t t_rfc_min : 12; 10300 uint32_t reserved_12_31 : 20; 10301 } s; 10302 /* struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg1_s cn; */ 10303 }; 10304 typedef union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg1 ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg1_t; 10305 10306 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1(uint64_t a) __attribute__ ((pure, always_inline)); 10307 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1(uint64_t a) 10308 { 10309 if (a <= 19) 10310 return 0x87e1b0200604ll + 0x1000000ll * ((a) & 0x1f); 10311 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1", 1, a, 0, 0, 0, 0, 0); 10312 } 10313 10314 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1(a) ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg1_t 10315 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1(a) CSR_TYPE_RSL32b 10316 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1" 10317 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1(a) 0x0 /* PF_BAR0 */ 10318 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1(a) (a) 10319 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG1(a) (a), -1, -1, -1 10320 10321 /** 10322 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_rfshset1tmg10 10323 * 10324 * DSS Ddrctl Regb Freq0 Ch0 Rfshset1tmg10 Register 10325 * Refresh Timing Register 10 belonging to Timing Set 1 10326 */ 10327 union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg10 { 10328 uint32_t u; 10329 struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg10_s { 10330 uint32_t t_win_size_1xtrefi : 12; 10331 uint32_t reserved_12_31 : 20; 10332 } s; 10333 /* struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg10_s cn; */ 10334 }; 10335 typedef union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg10 ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg10_t; 10336 10337 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10(uint64_t a) __attribute__ ((pure, always_inline)); 10338 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10(uint64_t a) 10339 { 10340 if (a <= 19) 10341 return 0x87e1b0200628ll + 0x1000000ll * ((a) & 0x1f); 10342 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10", 1, a, 0, 0, 0, 0, 0); 10343 } 10344 10345 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10(a) ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg10_t 10346 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10(a) CSR_TYPE_RSL32b 10347 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10" 10348 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10(a) 0x0 /* PF_BAR0 */ 10349 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10(a) (a) 10350 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG10(a) (a), -1, -1, -1 10351 10352 /** 10353 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_rfshset1tmg3 10354 * 10355 * DSS Ddrctl Regb Freq0 Ch0 Rfshset1tmg3 Register 10356 * Refresh Timing Register 3 belonging to Timing Set 1 10357 */ 10358 union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg3 { 10359 uint32_t u; 10360 struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg3_s { 10361 uint32_t t_rfcsb : 12; 10362 uint32_t reserved_12_15 : 4; 10363 uint32_t t_refsbrd : 8; 10364 uint32_t reserved_24_31 : 8; 10365 } s; 10366 /* struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg3_s cn; */ 10367 }; 10368 typedef union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg3 ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg3_t; 10369 10370 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3(uint64_t a) __attribute__ ((pure, always_inline)); 10371 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3(uint64_t a) 10372 { 10373 if (a <= 19) 10374 return 0x87e1b020060cll + 0x1000000ll * ((a) & 0x1f); 10375 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3", 1, a, 0, 0, 0, 0, 0); 10376 } 10377 10378 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3(a) ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg3_t 10379 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3(a) CSR_TYPE_RSL32b 10380 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3" 10381 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3(a) 0x0 /* PF_BAR0 */ 10382 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3(a) (a) 10383 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG3(a) (a), -1, -1, -1 10384 10385 /** 10386 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_rfshset1tmg4 10387 * 10388 * DSS Ddrctl Regb Freq0 Ch0 Rfshset1tmg4 Register 10389 * Refresh Timing Register 4 belonging to Timing Set 1 10390 */ 10391 union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg4 { 10392 uint32_t u; 10393 struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg4_s { 10394 uint32_t refresh_timer0_start_value_x32 : 12; 10395 uint32_t reserved_12_15 : 4; 10396 uint32_t refresh_timer1_start_value_x32 : 12; 10397 uint32_t reserved_28_31 : 4; 10398 } s; 10399 /* struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg4_s cn; */ 10400 }; 10401 typedef union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg4 ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg4_t; 10402 10403 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4(uint64_t a) __attribute__ ((pure, always_inline)); 10404 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4(uint64_t a) 10405 { 10406 if (a <= 19) 10407 return 0x87e1b0200610ll + 0x1000000ll * ((a) & 0x1f); 10408 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4", 1, a, 0, 0, 0, 0, 0); 10409 } 10410 10411 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4(a) ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg4_t 10412 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4(a) CSR_TYPE_RSL32b 10413 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4" 10414 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4(a) 0x0 /* PF_BAR0 */ 10415 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4(a) (a) 10416 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG4(a) (a), -1, -1, -1 10417 10418 /** 10419 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_rfshset1tmg9 10420 * 10421 * DSS Ddrctl Regb Freq0 Ch0 Rfshset1tmg9 Register 10422 * Refresh Timing Register 9 belonging to Timing Set 1 10423 */ 10424 union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg9 { 10425 uint32_t u; 10426 struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg9_s { 10427 uint32_t refab_hi_sch_gap : 13; 10428 uint32_t reserved_13_15 : 3; 10429 uint32_t refsb_hi_sch_gap : 12; 10430 uint32_t reserved_28_31 : 4; 10431 } s; 10432 /* struct ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg9_s cn; */ 10433 }; 10434 typedef union ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg9 ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg9_t; 10435 10436 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9(uint64_t a) __attribute__ ((pure, always_inline)); 10437 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9(uint64_t a) 10438 { 10439 if (a <= 19) 10440 return 0x87e1b0200624ll + 0x1000000ll * ((a) & 0x1f); 10441 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9", 1, a, 0, 0, 0, 0, 0); 10442 } 10443 10444 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9(a) ody_dssx_ddrctl_regb_freq0_ch0_rfshset1tmg9_t 10445 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9(a) CSR_TYPE_RSL32b 10446 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9" 10447 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9(a) 0x0 /* PF_BAR0 */ 10448 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9(a) (a) 10449 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_RFSHSET1TMG9(a) (a), -1, -1, -1 10450 10451 /** 10452 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_schedtmg0 10453 * 10454 * DSS Ddrctl Regb Freq0 Ch0 Schedtmg0 Register 10455 * Scheduler Control Register 10456 */ 10457 union ody_dssx_ddrctl_regb_freq0_ch0_schedtmg0 { 10458 uint32_t u; 10459 struct ody_dssx_ddrctl_regb_freq0_ch0_schedtmg0_s { 10460 uint32_t pageclose_timer : 8; 10461 uint32_t rdwr_idle_gap : 7; 10462 uint32_t reserved_15_31 : 17; 10463 } s; 10464 /* struct ody_dssx_ddrctl_regb_freq0_ch0_schedtmg0_s cn; */ 10465 }; 10466 typedef union ody_dssx_ddrctl_regb_freq0_ch0_schedtmg0 ody_dssx_ddrctl_regb_freq0_ch0_schedtmg0_t; 10467 10468 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0(uint64_t a) __attribute__ ((pure, always_inline)); 10469 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0(uint64_t a) 10470 { 10471 if (a <= 19) 10472 return 0x87e1b0200c00ll + 0x1000000ll * ((a) & 0x1f); 10473 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0", 1, a, 0, 0, 0, 0, 0); 10474 } 10475 10476 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_schedtmg0_t 10477 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0(a) CSR_TYPE_RSL32b 10478 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0" 10479 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0(a) 0x0 /* PF_BAR0 */ 10480 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0(a) (a) 10481 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_SCHEDTMG0(a) (a), -1, -1, -1 10482 10483 /** 10484 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_tmgcfg 10485 * 10486 * DSS Ddrctl Regb Freq0 Ch0 Tmgcfg Register 10487 * Timing Configuration Register 10488 */ 10489 union ody_dssx_ddrctl_regb_freq0_ch0_tmgcfg { 10490 uint32_t u; 10491 struct ody_dssx_ddrctl_regb_freq0_ch0_tmgcfg_s { 10492 uint32_t frequency_ratio : 1; 10493 uint32_t reserved_1_31 : 31; 10494 } s; 10495 /* struct ody_dssx_ddrctl_regb_freq0_ch0_tmgcfg_s cn; */ 10496 }; 10497 typedef union ody_dssx_ddrctl_regb_freq0_ch0_tmgcfg ody_dssx_ddrctl_regb_freq0_ch0_tmgcfg_t; 10498 10499 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG(uint64_t a) __attribute__ ((pure, always_inline)); 10500 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG(uint64_t a) 10501 { 10502 if (a <= 19) 10503 return 0x87e1b0200d00ll + 0x1000000ll * ((a) & 0x1f); 10504 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG", 1, a, 0, 0, 0, 0, 0); 10505 } 10506 10507 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG(a) ody_dssx_ddrctl_regb_freq0_ch0_tmgcfg_t 10508 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG(a) CSR_TYPE_RSL32b 10509 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG" 10510 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG(a) 0x0 /* PF_BAR0 */ 10511 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG(a) (a) 10512 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_TMGCFG(a) (a), -1, -1, -1 10513 10514 /** 10515 * Register (RSL32b) dss#_ddrctl_regb_freq0_ch0_zqset1tmg0 10516 * 10517 * DSS Ddrctl Regb Freq0 Ch0 Zqset1tmg0 Register 10518 * ZQ Timing Register 0 belonging to DRAM ZQ timing set 1 10519 */ 10520 union ody_dssx_ddrctl_regb_freq0_ch0_zqset1tmg0 { 10521 uint32_t u; 10522 struct ody_dssx_ddrctl_regb_freq0_ch0_zqset1tmg0_s { 10523 uint32_t t_zq_long_nop : 14; 10524 uint32_t reserved_14_15 : 2; 10525 uint32_t t_zq_short_nop : 10; 10526 uint32_t reserved_26_31 : 6; 10527 } s; 10528 /* struct ody_dssx_ddrctl_regb_freq0_ch0_zqset1tmg0_s cn; */ 10529 }; 10530 typedef union ody_dssx_ddrctl_regb_freq0_ch0_zqset1tmg0 ody_dssx_ddrctl_regb_freq0_ch0_zqset1tmg0_t; 10531 10532 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0(uint64_t a) __attribute__ ((pure, always_inline)); 10533 static inline uint64_t ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0(uint64_t a) 10534 { 10535 if (a <= 19) 10536 return 0x87e1b0200800ll + 0x1000000ll * ((a) & 0x1f); 10537 __ody_csr_fatal("DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0", 1, a, 0, 0, 0, 0, 0); 10538 } 10539 10540 #define typedef_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0(a) ody_dssx_ddrctl_regb_freq0_ch0_zqset1tmg0_t 10541 #define bustype_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0(a) CSR_TYPE_RSL32b 10542 #define basename_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0(a) "DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0" 10543 #define device_bar_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0(a) 0x0 /* PF_BAR0 */ 10544 #define busnum_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0(a) (a) 10545 #define arguments_ODY_DSSX_DDRCTL_REGB_FREQ0_CH0_ZQSET1TMG0(a) (a), -1, -1, -1 10546 10547 /** 10548 * Register (RSL) dss#_early_reset_n 10549 * 10550 * DSS Early reset Register 10551 * Soft early reset. 10552 */ 10553 union ody_dssx_early_reset_n { 10554 uint64_t u; 10555 struct ody_dssx_early_reset_n_s { 10556 uint64_t s_early_reset_n : 1; 10557 uint64_t reserved_1_63 : 63; 10558 } s; 10559 /* struct ody_dssx_early_reset_n_s cn; */ 10560 }; 10561 typedef union ody_dssx_early_reset_n ody_dssx_early_reset_n_t; 10562 10563 static inline uint64_t ODY_DSSX_EARLY_RESET_N(uint64_t a) __attribute__ ((pure, always_inline)); 10564 static inline uint64_t ODY_DSSX_EARLY_RESET_N(uint64_t a) 10565 { 10566 if (a <= 19) 10567 return 0x87e1b0000068ll + 0x1000000ll * ((a) & 0x1f); 10568 __ody_csr_fatal("DSSX_EARLY_RESET_N", 1, a, 0, 0, 0, 0, 0); 10569 } 10570 10571 #define typedef_ODY_DSSX_EARLY_RESET_N(a) ody_dssx_early_reset_n_t 10572 #define bustype_ODY_DSSX_EARLY_RESET_N(a) CSR_TYPE_RSL 10573 #define basename_ODY_DSSX_EARLY_RESET_N(a) "DSSX_EARLY_RESET_N" 10574 #define device_bar_ODY_DSSX_EARLY_RESET_N(a) 0x0 /* PF_BAR0 */ 10575 #define busnum_ODY_DSSX_EARLY_RESET_N(a) (a) 10576 #define arguments_ODY_DSSX_EARLY_RESET_N(a) (a), -1, -1, -1 10577 10578 /** 10579 * Register (RSL) dss#_fill_lvl_cnt_cfg# 10580 * 10581 * DSS Performance Counters accumulative Occupancy Level Configuration Register 10582 * Configuration register of internal memory controller FIFOs. 10583 * This register is responsible of choosing the FIFO to be counted. 10584 * Note: SW should set only one FIFO to be counted! If more than one is chosen, then 10585 * the design will choose first one! 10586 */ 10587 union ody_dssx_fill_lvl_cnt_cfgx { 10588 uint64_t u; 10589 struct ody_dssx_fill_lvl_cnt_cfgx_s { 10590 uint64_t chb_link_rxreq_flitq : 1; 10591 uint64_t chb_link_rxdat_flitq : 1; 10592 uint64_t chb_link_txdat_flitq : 1; 10593 uint64_t chb_tran_txrsp_dbid : 1; 10594 uint64_t chb_tran_txrsp_retryack : 1; 10595 uint64_t chb_tran_txrsp_pcrdgrant : 1; 10596 uint64_t chb_tran_txrsp_readreceipt : 1; 10597 uint64_t chb_tran_txrsp_comp_resp : 1; 10598 uint64_t chb_tran_rpq_lpr : 1; 10599 uint64_t chb_tran_rpq_hpr : 1; 10600 uint64_t chb_tran_rpq_vpr : 1; 10601 uint64_t chb_tran_wpq : 1; 10602 uint64_t chb_tran_rtlst_lpr : 1; 10603 uint64_t chb_tran_rtlst_vpr : 1; 10604 uint64_t chb_tran_rtlst_hpr : 1; 10605 uint64_t chb_tran_rtlst_npw : 1; 10606 uint64_t chb_tran_rtlst_vpw : 1; 10607 uint64_t chb_tran_hif_wr_crd : 1; 10608 uint64_t chb_tran_hif_lpr_crd : 1; 10609 uint64_t chb_tran_hif_hpr_crd : 1; 10610 uint64_t chb_tran_wr_pcrd_cnt : 1; 10611 uint64_t chb_tran_rd_pcrd_cnt : 1; 10612 uint64_t reserved_22_60 : 39; 10613 uint64_t interrupt_en : 1; 10614 uint64_t wrap_value : 1; 10615 uint64_t cnt_en : 1; 10616 } s; 10617 /* struct ody_dssx_fill_lvl_cnt_cfgx_s cn; */ 10618 }; 10619 typedef union ody_dssx_fill_lvl_cnt_cfgx ody_dssx_fill_lvl_cnt_cfgx_t; 10620 10621 static inline uint64_t ODY_DSSX_FILL_LVL_CNT_CFGX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 10622 static inline uint64_t ODY_DSSX_FILL_LVL_CNT_CFGX(uint64_t a, uint64_t b) 10623 { 10624 if ((a <= 19) && (b <= 2)) 10625 return 0x87e1b0008418ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 10626 __ody_csr_fatal("DSSX_FILL_LVL_CNT_CFGX", 2, a, b, 0, 0, 0, 0); 10627 } 10628 10629 #define typedef_ODY_DSSX_FILL_LVL_CNT_CFGX(a, b) ody_dssx_fill_lvl_cnt_cfgx_t 10630 #define bustype_ODY_DSSX_FILL_LVL_CNT_CFGX(a, b) CSR_TYPE_RSL 10631 #define basename_ODY_DSSX_FILL_LVL_CNT_CFGX(a, b) "DSSX_FILL_LVL_CNT_CFGX" 10632 #define device_bar_ODY_DSSX_FILL_LVL_CNT_CFGX(a, b) 0x0 /* PF_BAR0 */ 10633 #define busnum_ODY_DSSX_FILL_LVL_CNT_CFGX(a, b) (a) 10634 #define arguments_ODY_DSSX_FILL_LVL_CNT_CFGX(a, b) (a), (b), -1, -1 10635 10636 /** 10637 * Register (RSL) dss#_fill_lvl_cnt_clr 10638 * 10639 * Performance Counters Fill Level Clear Register 10640 * This register is used to clear fill level counters. 10641 */ 10642 union ody_dssx_fill_lvl_cnt_clr { 10643 uint64_t u; 10644 struct ody_dssx_fill_lvl_cnt_clr_s { 10645 uint64_t gen_fill_level_cnt_clr : 3; 10646 uint64_t txrsp_fill_level_cnt_clr : 1; 10647 uint64_t reserved_4_63 : 60; 10648 } s; 10649 /* struct ody_dssx_fill_lvl_cnt_clr_s cn; */ 10650 }; 10651 typedef union ody_dssx_fill_lvl_cnt_clr ody_dssx_fill_lvl_cnt_clr_t; 10652 10653 static inline uint64_t ODY_DSSX_FILL_LVL_CNT_CLR(uint64_t a) __attribute__ ((pure, always_inline)); 10654 static inline uint64_t ODY_DSSX_FILL_LVL_CNT_CLR(uint64_t a) 10655 { 10656 if (a <= 19) 10657 return 0x87e1b00086c8ll + 0x1000000ll * ((a) & 0x1f); 10658 __ody_csr_fatal("DSSX_FILL_LVL_CNT_CLR", 1, a, 0, 0, 0, 0, 0); 10659 } 10660 10661 #define typedef_ODY_DSSX_FILL_LVL_CNT_CLR(a) ody_dssx_fill_lvl_cnt_clr_t 10662 #define bustype_ODY_DSSX_FILL_LVL_CNT_CLR(a) CSR_TYPE_RSL 10663 #define basename_ODY_DSSX_FILL_LVL_CNT_CLR(a) "DSSX_FILL_LVL_CNT_CLR" 10664 #define device_bar_ODY_DSSX_FILL_LVL_CNT_CLR(a) 0x0 /* PF_BAR0 */ 10665 #define busnum_ODY_DSSX_FILL_LVL_CNT_CLR(a) (a) 10666 #define arguments_ODY_DSSX_FILL_LVL_CNT_CLR(a) (a), -1, -1, -1 10667 10668 /** 10669 * Register (RSL) dss#_fill_lvl_cnt_ovrflw# 10670 * 10671 * Performance Counters Fill Level overflow indication Register 10672 * This register indicates if the corresponding counter overflowed. 10673 */ 10674 union ody_dssx_fill_lvl_cnt_ovrflwx { 10675 uint64_t u; 10676 struct ody_dssx_fill_lvl_cnt_ovrflwx_s { 10677 uint64_t counter_overflow : 1; 10678 uint64_t reserved_1_63 : 63; 10679 } s; 10680 /* struct ody_dssx_fill_lvl_cnt_ovrflwx_s cn; */ 10681 }; 10682 typedef union ody_dssx_fill_lvl_cnt_ovrflwx ody_dssx_fill_lvl_cnt_ovrflwx_t; 10683 10684 static inline uint64_t ODY_DSSX_FILL_LVL_CNT_OVRFLWX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 10685 static inline uint64_t ODY_DSSX_FILL_LVL_CNT_OVRFLWX(uint64_t a, uint64_t b) 10686 { 10687 if ((a <= 19) && (b <= 2)) 10688 return 0x87e1b0008600ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 10689 __ody_csr_fatal("DSSX_FILL_LVL_CNT_OVRFLWX", 2, a, b, 0, 0, 0, 0); 10690 } 10691 10692 #define typedef_ODY_DSSX_FILL_LVL_CNT_OVRFLWX(a, b) ody_dssx_fill_lvl_cnt_ovrflwx_t 10693 #define bustype_ODY_DSSX_FILL_LVL_CNT_OVRFLWX(a, b) CSR_TYPE_RSL 10694 #define basename_ODY_DSSX_FILL_LVL_CNT_OVRFLWX(a, b) "DSSX_FILL_LVL_CNT_OVRFLWX" 10695 #define device_bar_ODY_DSSX_FILL_LVL_CNT_OVRFLWX(a, b) 0x0 /* PF_BAR0 */ 10696 #define busnum_ODY_DSSX_FILL_LVL_CNT_OVRFLWX(a, b) (a) 10697 #define arguments_ODY_DSSX_FILL_LVL_CNT_OVRFLWX(a, b) (a), (b), -1, -1 10698 10699 /** 10700 * Register (RSL) dss#_fill_lvl_cnt_val# 10701 * 10702 * Performance Counters Fill Level Value Register 10703 * Count of Accumulative occupancy level of chosen internal memory controller FIFOs. 10704 */ 10705 union ody_dssx_fill_lvl_cnt_valx { 10706 uint64_t u; 10707 struct ody_dssx_fill_lvl_cnt_valx_s { 10708 uint64_t counter_value : 64; 10709 } s; 10710 /* struct ody_dssx_fill_lvl_cnt_valx_s cn; */ 10711 }; 10712 typedef union ody_dssx_fill_lvl_cnt_valx ody_dssx_fill_lvl_cnt_valx_t; 10713 10714 static inline uint64_t ODY_DSSX_FILL_LVL_CNT_VALX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 10715 static inline uint64_t ODY_DSSX_FILL_LVL_CNT_VALX(uint64_t a, uint64_t b) 10716 { 10717 if ((a <= 19) && (b <= 2)) 10718 return 0x87e1b0008500ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 10719 __ody_csr_fatal("DSSX_FILL_LVL_CNT_VALX", 2, a, b, 0, 0, 0, 0); 10720 } 10721 10722 #define typedef_ODY_DSSX_FILL_LVL_CNT_VALX(a, b) ody_dssx_fill_lvl_cnt_valx_t 10723 #define bustype_ODY_DSSX_FILL_LVL_CNT_VALX(a, b) CSR_TYPE_RSL 10724 #define basename_ODY_DSSX_FILL_LVL_CNT_VALX(a, b) "DSSX_FILL_LVL_CNT_VALX" 10725 #define device_bar_ODY_DSSX_FILL_LVL_CNT_VALX(a, b) 0x0 /* PF_BAR0 */ 10726 #define busnum_ODY_DSSX_FILL_LVL_CNT_VALX(a, b) (a) 10727 #define arguments_ODY_DSSX_FILL_LVL_CNT_VALX(a, b) (a), (b), -1, -1 10728 10729 /** 10730 * Register (RSL) dss#_int_ena_w1c 10731 * 10732 * DSS Interrupt Enable Clear Registers 10733 * This register clears interrupt enable bits. 10734 */ 10735 union ody_dssx_int_ena_w1c { 10736 uint64_t u; 10737 struct ody_dssx_int_ena_w1c_s { 10738 uint64_t ctrlupd_err_intr : 1; 10739 uint64_t derate_temp_limit_intr : 1; 10740 uint64_t ducmd_err_intr : 1; 10741 uint64_t ecc_corrected_err_intr : 1; 10742 uint64_t ecc_uncorrected_err_intr : 1; 10743 uint64_t lccmd_err_intr : 1; 10744 uint64_t wr_crc_err_max_reached_intr : 1; 10745 uint64_t rd_crc_err_max_reached_intr : 1; 10746 uint64_t swcmd_err_intr : 1; 10747 uint64_t wr_crc_err_intr : 1; 10748 uint64_t capar_err_max_reached_intr : 1; 10749 uint64_t capar_err_intr : 1; 10750 uint64_t rfm_alert_intr : 1; 10751 uint64_t msh_dss_dat_chk_error_intr : 1; 10752 uint64_t msh_dss_req_chk_error_intr : 1; 10753 uint64_t rd_retry_limit_intr : 1; 10754 uint64_t wr_crc_retry_limit_intr : 1; 10755 uint64_t sbr_done_intr : 1; 10756 uint64_t dwc_ddrphy_int : 1; 10757 uint64_t dss_wr_crc_ret_lo_ecc_sbe_intr : 1; 10758 uint64_t dss_wr_crc_ret_lo_ecc_dbe_intr : 1; 10759 uint64_t dss_wr_crc_ret_hi_ecc_sbe_intr : 1; 10760 uint64_t dss_wr_crc_ret_hi_ecc_dbe_intr : 1; 10761 uint64_t dss_chb_rt_ecc_sbe_intr : 1; 10762 uint64_t dss_chb_rt_ecc_dbe_intr : 1; 10763 uint64_t dss_wdata_ram_ecc_sbe_intr : 1; 10764 uint64_t dss_wdata_ram_ecc_dbe_intr : 1; 10765 uint64_t dss_chb_wrb_lo_ecc_sbe_intr : 1; 10766 uint64_t dss_chb_wrb_hi_ecc_sbe_intr : 1; 10767 uint64_t dss_chb_wrb_lo_ecc_dbe_intr : 1; 10768 uint64_t dss_chb_wrb_hi_ecc_dbe_intr : 1; 10769 uint64_t capar_retry_limit_reached_intr : 1; 10770 uint64_t capar_fatl_err_intr : 1; 10771 uint64_t caparcmd_err_intr : 1; 10772 uint64_t reserved_34_63 : 30; 10773 } s; 10774 /* struct ody_dssx_int_ena_w1c_s cn; */ 10775 }; 10776 typedef union ody_dssx_int_ena_w1c ody_dssx_int_ena_w1c_t; 10777 10778 static inline uint64_t ODY_DSSX_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 10779 static inline uint64_t ODY_DSSX_INT_ENA_W1C(uint64_t a) 10780 { 10781 if (a <= 19) 10782 return 0x87e1b0008010ll + 0x1000000ll * ((a) & 0x1f); 10783 __ody_csr_fatal("DSSX_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0); 10784 } 10785 10786 #define typedef_ODY_DSSX_INT_ENA_W1C(a) ody_dssx_int_ena_w1c_t 10787 #define bustype_ODY_DSSX_INT_ENA_W1C(a) CSR_TYPE_RSL 10788 #define basename_ODY_DSSX_INT_ENA_W1C(a) "DSSX_INT_ENA_W1C" 10789 #define device_bar_ODY_DSSX_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */ 10790 #define busnum_ODY_DSSX_INT_ENA_W1C(a) (a) 10791 #define arguments_ODY_DSSX_INT_ENA_W1C(a) (a), -1, -1, -1 10792 10793 /** 10794 * Register (RSL) dss#_int_ena_w1s 10795 * 10796 * DSS Interrupt Enable Set Registers 10797 * This register sets interrupt enable bits. 10798 */ 10799 union ody_dssx_int_ena_w1s { 10800 uint64_t u; 10801 struct ody_dssx_int_ena_w1s_s { 10802 uint64_t ctrlupd_err_intr : 1; 10803 uint64_t derate_temp_limit_intr : 1; 10804 uint64_t ducmd_err_intr : 1; 10805 uint64_t ecc_corrected_err_intr : 1; 10806 uint64_t ecc_uncorrected_err_intr : 1; 10807 uint64_t lccmd_err_intr : 1; 10808 uint64_t wr_crc_err_max_reached_intr : 1; 10809 uint64_t rd_crc_err_max_reached_intr : 1; 10810 uint64_t swcmd_err_intr : 1; 10811 uint64_t wr_crc_err_intr : 1; 10812 uint64_t capar_err_max_reached_intr : 1; 10813 uint64_t capar_err_intr : 1; 10814 uint64_t rfm_alert_intr : 1; 10815 uint64_t msh_dss_dat_chk_error_intr : 1; 10816 uint64_t msh_dss_req_chk_error_intr : 1; 10817 uint64_t rd_retry_limit_intr : 1; 10818 uint64_t wr_crc_retry_limit_intr : 1; 10819 uint64_t sbr_done_intr : 1; 10820 uint64_t dwc_ddrphy_int : 1; 10821 uint64_t dss_wr_crc_ret_lo_ecc_sbe_intr : 1; 10822 uint64_t dss_wr_crc_ret_lo_ecc_dbe_intr : 1; 10823 uint64_t dss_wr_crc_ret_hi_ecc_sbe_intr : 1; 10824 uint64_t dss_wr_crc_ret_hi_ecc_dbe_intr : 1; 10825 uint64_t dss_chb_rt_ecc_sbe_intr : 1; 10826 uint64_t dss_chb_rt_ecc_dbe_intr : 1; 10827 uint64_t dss_wdata_ram_ecc_sbe_intr : 1; 10828 uint64_t dss_wdata_ram_ecc_dbe_intr : 1; 10829 uint64_t dss_chb_wrb_lo_ecc_sbe_intr : 1; 10830 uint64_t dss_chb_wrb_hi_ecc_sbe_intr : 1; 10831 uint64_t dss_chb_wrb_lo_ecc_dbe_intr : 1; 10832 uint64_t dss_chb_wrb_hi_ecc_dbe_intr : 1; 10833 uint64_t capar_retry_limit_reached_intr : 1; 10834 uint64_t capar_fatl_err_intr : 1; 10835 uint64_t caparcmd_err_intr : 1; 10836 uint64_t reserved_34_63 : 30; 10837 } s; 10838 /* struct ody_dssx_int_ena_w1s_s cn; */ 10839 }; 10840 typedef union ody_dssx_int_ena_w1s ody_dssx_int_ena_w1s_t; 10841 10842 static inline uint64_t ODY_DSSX_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 10843 static inline uint64_t ODY_DSSX_INT_ENA_W1S(uint64_t a) 10844 { 10845 if (a <= 19) 10846 return 0x87e1b0008018ll + 0x1000000ll * ((a) & 0x1f); 10847 __ody_csr_fatal("DSSX_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0); 10848 } 10849 10850 #define typedef_ODY_DSSX_INT_ENA_W1S(a) ody_dssx_int_ena_w1s_t 10851 #define bustype_ODY_DSSX_INT_ENA_W1S(a) CSR_TYPE_RSL 10852 #define basename_ODY_DSSX_INT_ENA_W1S(a) "DSSX_INT_ENA_W1S" 10853 #define device_bar_ODY_DSSX_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */ 10854 #define busnum_ODY_DSSX_INT_ENA_W1S(a) (a) 10855 #define arguments_ODY_DSSX_INT_ENA_W1S(a) (a), -1, -1, -1 10856 10857 /** 10858 * Register (RSL) dss#_int_w1c 10859 * 10860 * DSS Interrupt Register 10861 * This register is for DSS-based interrupts. 10862 */ 10863 union ody_dssx_int_w1c { 10864 uint64_t u; 10865 struct ody_dssx_int_w1c_s { 10866 uint64_t ctrlupd_err_intr : 1; 10867 uint64_t derate_temp_limit_intr : 1; 10868 uint64_t ducmd_err_intr : 1; 10869 uint64_t ecc_corrected_err_intr : 1; 10870 uint64_t ecc_uncorrected_err_intr : 1; 10871 uint64_t lccmd_err_intr : 1; 10872 uint64_t wr_crc_err_max_reached_intr : 1; 10873 uint64_t rd_crc_err_max_reached_intr : 1; 10874 uint64_t swcmd_err_intr : 1; 10875 uint64_t wr_crc_err_intr : 1; 10876 uint64_t capar_err_max_reached_intr : 1; 10877 uint64_t capar_err_intr : 1; 10878 uint64_t rfm_alert_intr : 1; 10879 uint64_t msh_dss_dat_chk_error_intr : 1; 10880 uint64_t msh_dss_req_chk_error_intr : 1; 10881 uint64_t rd_retry_limit_intr : 1; 10882 uint64_t wr_crc_retry_limit_intr : 1; 10883 uint64_t sbr_done_intr : 1; 10884 uint64_t dwc_ddrphy_int : 1; 10885 uint64_t dss_wr_crc_ret_lo_ecc_sbe_intr : 1; 10886 uint64_t dss_wr_crc_ret_lo_ecc_dbe_intr : 1; 10887 uint64_t dss_wr_crc_ret_hi_ecc_sbe_intr : 1; 10888 uint64_t dss_wr_crc_ret_hi_ecc_dbe_intr : 1; 10889 uint64_t dss_chb_rt_ecc_sbe_intr : 1; 10890 uint64_t dss_chb_rt_ecc_dbe_intr : 1; 10891 uint64_t dss_wdata_ram_ecc_sbe_intr : 1; 10892 uint64_t dss_wdata_ram_ecc_dbe_intr : 1; 10893 uint64_t dss_chb_wrb_lo_ecc_sbe_intr : 1; 10894 uint64_t dss_chb_wrb_hi_ecc_sbe_intr : 1; 10895 uint64_t dss_chb_wrb_lo_ecc_dbe_intr : 1; 10896 uint64_t dss_chb_wrb_hi_ecc_dbe_intr : 1; 10897 uint64_t capar_retry_limit_reached_intr : 1; 10898 uint64_t capar_fatl_err_intr : 1; 10899 uint64_t caparcmd_err_intr : 1; 10900 uint64_t reserved_34_63 : 30; 10901 } s; 10902 /* struct ody_dssx_int_w1c_s cn; */ 10903 }; 10904 typedef union ody_dssx_int_w1c ody_dssx_int_w1c_t; 10905 10906 static inline uint64_t ODY_DSSX_INT_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 10907 static inline uint64_t ODY_DSSX_INT_W1C(uint64_t a) 10908 { 10909 if (a <= 19) 10910 return 0x87e1b0008000ll + 0x1000000ll * ((a) & 0x1f); 10911 __ody_csr_fatal("DSSX_INT_W1C", 1, a, 0, 0, 0, 0, 0); 10912 } 10913 10914 #define typedef_ODY_DSSX_INT_W1C(a) ody_dssx_int_w1c_t 10915 #define bustype_ODY_DSSX_INT_W1C(a) CSR_TYPE_RSL 10916 #define basename_ODY_DSSX_INT_W1C(a) "DSSX_INT_W1C" 10917 #define device_bar_ODY_DSSX_INT_W1C(a) 0x0 /* PF_BAR0 */ 10918 #define busnum_ODY_DSSX_INT_W1C(a) (a) 10919 #define arguments_ODY_DSSX_INT_W1C(a) (a), -1, -1, -1 10920 10921 /** 10922 * Register (RSL) dss#_int_w1s 10923 * 10924 * DSS Interrupt Set Registers 10925 * This register sets interrupt bits. 10926 */ 10927 union ody_dssx_int_w1s { 10928 uint64_t u; 10929 struct ody_dssx_int_w1s_s { 10930 uint64_t ctrlupd_err_intr : 1; 10931 uint64_t derate_temp_limit_intr : 1; 10932 uint64_t ducmd_err_intr : 1; 10933 uint64_t ecc_corrected_err_intr : 1; 10934 uint64_t ecc_uncorrected_err_intr : 1; 10935 uint64_t lccmd_err_intr : 1; 10936 uint64_t wr_crc_err_max_reached_intr : 1; 10937 uint64_t rd_crc_err_max_reached_intr : 1; 10938 uint64_t swcmd_err_intr : 1; 10939 uint64_t wr_crc_err_intr : 1; 10940 uint64_t capar_err_max_reached_intr : 1; 10941 uint64_t capar_err_intr : 1; 10942 uint64_t rfm_alert_intr : 1; 10943 uint64_t msh_dss_dat_chk_error_intr : 1; 10944 uint64_t msh_dss_req_chk_error_intr : 1; 10945 uint64_t rd_retry_limit_intr : 1; 10946 uint64_t wr_crc_retry_limit_intr : 1; 10947 uint64_t sbr_done_intr : 1; 10948 uint64_t dwc_ddrphy_int : 1; 10949 uint64_t dss_wr_crc_ret_lo_ecc_sbe_intr : 1; 10950 uint64_t dss_wr_crc_ret_lo_ecc_dbe_intr : 1; 10951 uint64_t dss_wr_crc_ret_hi_ecc_sbe_intr : 1; 10952 uint64_t dss_wr_crc_ret_hi_ecc_dbe_intr : 1; 10953 uint64_t dss_chb_rt_ecc_sbe_intr : 1; 10954 uint64_t dss_chb_rt_ecc_dbe_intr : 1; 10955 uint64_t dss_wdata_ram_ecc_sbe_intr : 1; 10956 uint64_t dss_wdata_ram_ecc_dbe_intr : 1; 10957 uint64_t dss_chb_wrb_lo_ecc_sbe_intr : 1; 10958 uint64_t dss_chb_wrb_hi_ecc_sbe_intr : 1; 10959 uint64_t dss_chb_wrb_lo_ecc_dbe_intr : 1; 10960 uint64_t dss_chb_wrb_hi_ecc_dbe_intr : 1; 10961 uint64_t capar_retry_limit_reached_intr : 1; 10962 uint64_t capar_fatl_err_intr : 1; 10963 uint64_t caparcmd_err_intr : 1; 10964 uint64_t reserved_34_63 : 30; 10965 } s; 10966 /* struct ody_dssx_int_w1s_s cn; */ 10967 }; 10968 typedef union ody_dssx_int_w1s ody_dssx_int_w1s_t; 10969 10970 static inline uint64_t ODY_DSSX_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 10971 static inline uint64_t ODY_DSSX_INT_W1S(uint64_t a) 10972 { 10973 if (a <= 19) 10974 return 0x87e1b0008008ll + 0x1000000ll * ((a) & 0x1f); 10975 __ody_csr_fatal("DSSX_INT_W1S", 1, a, 0, 0, 0, 0, 0); 10976 } 10977 10978 #define typedef_ODY_DSSX_INT_W1S(a) ody_dssx_int_w1s_t 10979 #define bustype_ODY_DSSX_INT_W1S(a) CSR_TYPE_RSL 10980 #define basename_ODY_DSSX_INT_W1S(a) "DSSX_INT_W1S" 10981 #define device_bar_ODY_DSSX_INT_W1S(a) 0x0 /* PF_BAR0 */ 10982 #define busnum_ODY_DSSX_INT_W1S(a) (a) 10983 #define arguments_ODY_DSSX_INT_W1S(a) (a), -1, -1, -1 10984 10985 /** 10986 * Register (RSL) dss#_lat_calc_ctrl 10987 * 10988 * DSS latency calculation control Register 10989 * Control register for read/write commands latency calculator. 10990 */ 10991 union ody_dssx_lat_calc_ctrl { 10992 uint64_t u; 10993 struct ody_dssx_lat_calc_ctrl_s { 10994 uint64_t wr_latency_calc_enable : 1; 10995 uint64_t rd_latency_calc_enable : 1; 10996 uint64_t latch_latency_registers : 1; 10997 uint64_t reserved_3_63 : 61; 10998 } s; 10999 /* struct ody_dssx_lat_calc_ctrl_s cn; */ 11000 }; 11001 typedef union ody_dssx_lat_calc_ctrl ody_dssx_lat_calc_ctrl_t; 11002 11003 static inline uint64_t ODY_DSSX_LAT_CALC_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 11004 static inline uint64_t ODY_DSSX_LAT_CALC_CTRL(uint64_t a) 11005 { 11006 if (a <= 19) 11007 return 0x87e1b0008300ll + 0x1000000ll * ((a) & 0x1f); 11008 __ody_csr_fatal("DSSX_LAT_CALC_CTRL", 1, a, 0, 0, 0, 0, 0); 11009 } 11010 11011 #define typedef_ODY_DSSX_LAT_CALC_CTRL(a) ody_dssx_lat_calc_ctrl_t 11012 #define bustype_ODY_DSSX_LAT_CALC_CTRL(a) CSR_TYPE_RSL 11013 #define basename_ODY_DSSX_LAT_CALC_CTRL(a) "DSSX_LAT_CALC_CTRL" 11014 #define device_bar_ODY_DSSX_LAT_CALC_CTRL(a) 0x0 /* PF_BAR0 */ 11015 #define busnum_ODY_DSSX_LAT_CALC_CTRL(a) (a) 11016 #define arguments_ODY_DSSX_LAT_CALC_CTRL(a) (a), -1, -1, -1 11017 11018 /** 11019 * Register (RSL) dss#_lat_num_rd_req_hi 11020 * 11021 * DSS number read requests Register 11022 * Status register indicating number of total issued read requests to DSS. 11023 * Total number of read requests is {DSS_LAT_NUM_RD_REQ_HI, DSS_LAT_NUM_RD_REQ_LO}. 11024 */ 11025 union ody_dssx_lat_num_rd_req_hi { 11026 uint64_t u; 11027 struct ody_dssx_lat_num_rd_req_hi_s { 11028 uint64_t lat_num_rd_req_hi : 64; 11029 } s; 11030 /* struct ody_dssx_lat_num_rd_req_hi_s cn; */ 11031 }; 11032 typedef union ody_dssx_lat_num_rd_req_hi ody_dssx_lat_num_rd_req_hi_t; 11033 11034 static inline uint64_t ODY_DSSX_LAT_NUM_RD_REQ_HI(uint64_t a) __attribute__ ((pure, always_inline)); 11035 static inline uint64_t ODY_DSSX_LAT_NUM_RD_REQ_HI(uint64_t a) 11036 { 11037 if (a <= 19) 11038 return 0x87e1b0008310ll + 0x1000000ll * ((a) & 0x1f); 11039 __ody_csr_fatal("DSSX_LAT_NUM_RD_REQ_HI", 1, a, 0, 0, 0, 0, 0); 11040 } 11041 11042 #define typedef_ODY_DSSX_LAT_NUM_RD_REQ_HI(a) ody_dssx_lat_num_rd_req_hi_t 11043 #define bustype_ODY_DSSX_LAT_NUM_RD_REQ_HI(a) CSR_TYPE_RSL 11044 #define basename_ODY_DSSX_LAT_NUM_RD_REQ_HI(a) "DSSX_LAT_NUM_RD_REQ_HI" 11045 #define device_bar_ODY_DSSX_LAT_NUM_RD_REQ_HI(a) 0x0 /* PF_BAR0 */ 11046 #define busnum_ODY_DSSX_LAT_NUM_RD_REQ_HI(a) (a) 11047 #define arguments_ODY_DSSX_LAT_NUM_RD_REQ_HI(a) (a), -1, -1, -1 11048 11049 /** 11050 * Register (RSL) dss#_lat_num_rd_req_lo 11051 * 11052 * DSS number read requests Register 11053 * Status register indicating number of total issued read requests to DSS. 11054 * Total number of read requests is {DSS_LAT_NUM_RD_REQ_HI, DSS_LAT_NUM_RD_REQ_LO}. 11055 */ 11056 union ody_dssx_lat_num_rd_req_lo { 11057 uint64_t u; 11058 struct ody_dssx_lat_num_rd_req_lo_s { 11059 uint64_t lat_num_rd_req_lo : 64; 11060 } s; 11061 /* struct ody_dssx_lat_num_rd_req_lo_s cn; */ 11062 }; 11063 typedef union ody_dssx_lat_num_rd_req_lo ody_dssx_lat_num_rd_req_lo_t; 11064 11065 static inline uint64_t ODY_DSSX_LAT_NUM_RD_REQ_LO(uint64_t a) __attribute__ ((pure, always_inline)); 11066 static inline uint64_t ODY_DSSX_LAT_NUM_RD_REQ_LO(uint64_t a) 11067 { 11068 if (a <= 19) 11069 return 0x87e1b0008308ll + 0x1000000ll * ((a) & 0x1f); 11070 __ody_csr_fatal("DSSX_LAT_NUM_RD_REQ_LO", 1, a, 0, 0, 0, 0, 0); 11071 } 11072 11073 #define typedef_ODY_DSSX_LAT_NUM_RD_REQ_LO(a) ody_dssx_lat_num_rd_req_lo_t 11074 #define bustype_ODY_DSSX_LAT_NUM_RD_REQ_LO(a) CSR_TYPE_RSL 11075 #define basename_ODY_DSSX_LAT_NUM_RD_REQ_LO(a) "DSSX_LAT_NUM_RD_REQ_LO" 11076 #define device_bar_ODY_DSSX_LAT_NUM_RD_REQ_LO(a) 0x0 /* PF_BAR0 */ 11077 #define busnum_ODY_DSSX_LAT_NUM_RD_REQ_LO(a) (a) 11078 #define arguments_ODY_DSSX_LAT_NUM_RD_REQ_LO(a) (a), -1, -1, -1 11079 11080 /** 11081 * Register (RSL) dss#_lat_num_wr_req_hi 11082 * 11083 * DSS number write requests Register 11084 * Status register indicating number of total issued write requests to DSS. 11085 * Total number of read requests is {DSS_LAT_NUM_WR_REQ_HI, DSS_LAT_NUM_WR_REQ_LO}. 11086 */ 11087 union ody_dssx_lat_num_wr_req_hi { 11088 uint64_t u; 11089 struct ody_dssx_lat_num_wr_req_hi_s { 11090 uint64_t lat_num_wr_req_hi : 64; 11091 } s; 11092 /* struct ody_dssx_lat_num_wr_req_hi_s cn; */ 11093 }; 11094 typedef union ody_dssx_lat_num_wr_req_hi ody_dssx_lat_num_wr_req_hi_t; 11095 11096 static inline uint64_t ODY_DSSX_LAT_NUM_WR_REQ_HI(uint64_t a) __attribute__ ((pure, always_inline)); 11097 static inline uint64_t ODY_DSSX_LAT_NUM_WR_REQ_HI(uint64_t a) 11098 { 11099 if (a <= 19) 11100 return 0x87e1b0008320ll + 0x1000000ll * ((a) & 0x1f); 11101 __ody_csr_fatal("DSSX_LAT_NUM_WR_REQ_HI", 1, a, 0, 0, 0, 0, 0); 11102 } 11103 11104 #define typedef_ODY_DSSX_LAT_NUM_WR_REQ_HI(a) ody_dssx_lat_num_wr_req_hi_t 11105 #define bustype_ODY_DSSX_LAT_NUM_WR_REQ_HI(a) CSR_TYPE_RSL 11106 #define basename_ODY_DSSX_LAT_NUM_WR_REQ_HI(a) "DSSX_LAT_NUM_WR_REQ_HI" 11107 #define device_bar_ODY_DSSX_LAT_NUM_WR_REQ_HI(a) 0x0 /* PF_BAR0 */ 11108 #define busnum_ODY_DSSX_LAT_NUM_WR_REQ_HI(a) (a) 11109 #define arguments_ODY_DSSX_LAT_NUM_WR_REQ_HI(a) (a), -1, -1, -1 11110 11111 /** 11112 * Register (RSL) dss#_lat_num_wr_req_lo 11113 * 11114 * DSS number write requests Register 11115 * Status register indicating number of total issued write requests to DSS. 11116 * Total number of write requests is {DSS_LAT_NUM_WR_REQ_HI, DSS_LAT_NUM_WR_REQ_LO}. 11117 */ 11118 union ody_dssx_lat_num_wr_req_lo { 11119 uint64_t u; 11120 struct ody_dssx_lat_num_wr_req_lo_s { 11121 uint64_t lat_num_wr_req_lo : 64; 11122 } s; 11123 /* struct ody_dssx_lat_num_wr_req_lo_s cn; */ 11124 }; 11125 typedef union ody_dssx_lat_num_wr_req_lo ody_dssx_lat_num_wr_req_lo_t; 11126 11127 static inline uint64_t ODY_DSSX_LAT_NUM_WR_REQ_LO(uint64_t a) __attribute__ ((pure, always_inline)); 11128 static inline uint64_t ODY_DSSX_LAT_NUM_WR_REQ_LO(uint64_t a) 11129 { 11130 if (a <= 19) 11131 return 0x87e1b0008318ll + 0x1000000ll * ((a) & 0x1f); 11132 __ody_csr_fatal("DSSX_LAT_NUM_WR_REQ_LO", 1, a, 0, 0, 0, 0, 0); 11133 } 11134 11135 #define typedef_ODY_DSSX_LAT_NUM_WR_REQ_LO(a) ody_dssx_lat_num_wr_req_lo_t 11136 #define bustype_ODY_DSSX_LAT_NUM_WR_REQ_LO(a) CSR_TYPE_RSL 11137 #define basename_ODY_DSSX_LAT_NUM_WR_REQ_LO(a) "DSSX_LAT_NUM_WR_REQ_LO" 11138 #define device_bar_ODY_DSSX_LAT_NUM_WR_REQ_LO(a) 0x0 /* PF_BAR0 */ 11139 #define busnum_ODY_DSSX_LAT_NUM_WR_REQ_LO(a) (a) 11140 #define arguments_ODY_DSSX_LAT_NUM_WR_REQ_LO(a) (a), -1, -1, -1 11141 11142 /** 11143 * Register (RSL) dss#_lat_outstand_rd_wr_req 11144 * 11145 * DSS number of outstanding read/write requests Register 11146 * Status register indicating number of current outstanding read/write requests in DSS. 11147 */ 11148 union ody_dssx_lat_outstand_rd_wr_req { 11149 uint64_t u; 11150 struct ody_dssx_lat_outstand_rd_wr_req_s { 11151 uint64_t lat_outstanding_rd : 9; 11152 uint64_t lat_outstanding_wr : 9; 11153 uint64_t reserved_18_63 : 46; 11154 } s; 11155 /* struct ody_dssx_lat_outstand_rd_wr_req_s cn; */ 11156 }; 11157 typedef union ody_dssx_lat_outstand_rd_wr_req ody_dssx_lat_outstand_rd_wr_req_t; 11158 11159 static inline uint64_t ODY_DSSX_LAT_OUTSTAND_RD_WR_REQ(uint64_t a) __attribute__ ((pure, always_inline)); 11160 static inline uint64_t ODY_DSSX_LAT_OUTSTAND_RD_WR_REQ(uint64_t a) 11161 { 11162 if (a <= 19) 11163 return 0x87e1b0008328ll + 0x1000000ll * ((a) & 0x1f); 11164 __ody_csr_fatal("DSSX_LAT_OUTSTAND_RD_WR_REQ", 1, a, 0, 0, 0, 0, 0); 11165 } 11166 11167 #define typedef_ODY_DSSX_LAT_OUTSTAND_RD_WR_REQ(a) ody_dssx_lat_outstand_rd_wr_req_t 11168 #define bustype_ODY_DSSX_LAT_OUTSTAND_RD_WR_REQ(a) CSR_TYPE_RSL 11169 #define basename_ODY_DSSX_LAT_OUTSTAND_RD_WR_REQ(a) "DSSX_LAT_OUTSTAND_RD_WR_REQ" 11170 #define device_bar_ODY_DSSX_LAT_OUTSTAND_RD_WR_REQ(a) 0x0 /* PF_BAR0 */ 11171 #define busnum_ODY_DSSX_LAT_OUTSTAND_RD_WR_REQ(a) (a) 11172 #define arguments_ODY_DSSX_LAT_OUTSTAND_RD_WR_REQ(a) (a), -1, -1, -1 11173 11174 /** 11175 * Register (RSL) dss#_lat_total_rd_latency_hi 11176 * 11177 * DSS Total Read Latency High Register 11178 * Status register indicating number of total latency of all read requests since 11179 * latency calculation is enabled in DSS. 11180 * Total number of read latency in DFI cycles is {DSS_LAT_TOTAL_RD_LATENCY_HI, 11181 * DSS_LAT_TOTAL_RD_LATENCY_LO}. 11182 */ 11183 union ody_dssx_lat_total_rd_latency_hi { 11184 uint64_t u; 11185 struct ody_dssx_lat_total_rd_latency_hi_s { 11186 uint64_t total_rd_latency_hi : 64; 11187 } s; 11188 /* struct ody_dssx_lat_total_rd_latency_hi_s cn; */ 11189 }; 11190 typedef union ody_dssx_lat_total_rd_latency_hi ody_dssx_lat_total_rd_latency_hi_t; 11191 11192 static inline uint64_t ODY_DSSX_LAT_TOTAL_RD_LATENCY_HI(uint64_t a) __attribute__ ((pure, always_inline)); 11193 static inline uint64_t ODY_DSSX_LAT_TOTAL_RD_LATENCY_HI(uint64_t a) 11194 { 11195 if (a <= 19) 11196 return 0x87e1b0008338ll + 0x1000000ll * ((a) & 0x1f); 11197 __ody_csr_fatal("DSSX_LAT_TOTAL_RD_LATENCY_HI", 1, a, 0, 0, 0, 0, 0); 11198 } 11199 11200 #define typedef_ODY_DSSX_LAT_TOTAL_RD_LATENCY_HI(a) ody_dssx_lat_total_rd_latency_hi_t 11201 #define bustype_ODY_DSSX_LAT_TOTAL_RD_LATENCY_HI(a) CSR_TYPE_RSL 11202 #define basename_ODY_DSSX_LAT_TOTAL_RD_LATENCY_HI(a) "DSSX_LAT_TOTAL_RD_LATENCY_HI" 11203 #define device_bar_ODY_DSSX_LAT_TOTAL_RD_LATENCY_HI(a) 0x0 /* PF_BAR0 */ 11204 #define busnum_ODY_DSSX_LAT_TOTAL_RD_LATENCY_HI(a) (a) 11205 #define arguments_ODY_DSSX_LAT_TOTAL_RD_LATENCY_HI(a) (a), -1, -1, -1 11206 11207 /** 11208 * Register (RSL) dss#_lat_total_rd_latency_lo 11209 * 11210 * DSS Total Read Latency Low Register 11211 * Status register indicating number of total latency of all read requests since 11212 * latency calculation is enabled in DSS. 11213 * Total number of read latency in DFI cycles is {DSS_LAT_TOTAL_RD_LATENCY_HI, 11214 * DSS_LAT_TOTAL_RD_LATENCY_LO}. 11215 */ 11216 union ody_dssx_lat_total_rd_latency_lo { 11217 uint64_t u; 11218 struct ody_dssx_lat_total_rd_latency_lo_s { 11219 uint64_t total_rd_latency_lo : 64; 11220 } s; 11221 /* struct ody_dssx_lat_total_rd_latency_lo_s cn; */ 11222 }; 11223 typedef union ody_dssx_lat_total_rd_latency_lo ody_dssx_lat_total_rd_latency_lo_t; 11224 11225 static inline uint64_t ODY_DSSX_LAT_TOTAL_RD_LATENCY_LO(uint64_t a) __attribute__ ((pure, always_inline)); 11226 static inline uint64_t ODY_DSSX_LAT_TOTAL_RD_LATENCY_LO(uint64_t a) 11227 { 11228 if (a <= 19) 11229 return 0x87e1b0008330ll + 0x1000000ll * ((a) & 0x1f); 11230 __ody_csr_fatal("DSSX_LAT_TOTAL_RD_LATENCY_LO", 1, a, 0, 0, 0, 0, 0); 11231 } 11232 11233 #define typedef_ODY_DSSX_LAT_TOTAL_RD_LATENCY_LO(a) ody_dssx_lat_total_rd_latency_lo_t 11234 #define bustype_ODY_DSSX_LAT_TOTAL_RD_LATENCY_LO(a) CSR_TYPE_RSL 11235 #define basename_ODY_DSSX_LAT_TOTAL_RD_LATENCY_LO(a) "DSSX_LAT_TOTAL_RD_LATENCY_LO" 11236 #define device_bar_ODY_DSSX_LAT_TOTAL_RD_LATENCY_LO(a) 0x0 /* PF_BAR0 */ 11237 #define busnum_ODY_DSSX_LAT_TOTAL_RD_LATENCY_LO(a) (a) 11238 #define arguments_ODY_DSSX_LAT_TOTAL_RD_LATENCY_LO(a) (a), -1, -1, -1 11239 11240 /** 11241 * Register (RSL) dss#_lat_total_wr_latency_hi 11242 * 11243 * DSS Total Write Latency High Register 11244 * Status register indicating number of total latency of all write requests since 11245 * latency calculation is enabled in DSS. 11246 * Total number of write latency in DFI cycles is {DSS_LAT_TOTAL_WR_LATENCY_HI, 11247 * DSS_LAT_TOTAL_WR_LATENCY_LO}. 11248 */ 11249 union ody_dssx_lat_total_wr_latency_hi { 11250 uint64_t u; 11251 struct ody_dssx_lat_total_wr_latency_hi_s { 11252 uint64_t total_wr_latency_hi : 64; 11253 } s; 11254 /* struct ody_dssx_lat_total_wr_latency_hi_s cn; */ 11255 }; 11256 typedef union ody_dssx_lat_total_wr_latency_hi ody_dssx_lat_total_wr_latency_hi_t; 11257 11258 static inline uint64_t ODY_DSSX_LAT_TOTAL_WR_LATENCY_HI(uint64_t a) __attribute__ ((pure, always_inline)); 11259 static inline uint64_t ODY_DSSX_LAT_TOTAL_WR_LATENCY_HI(uint64_t a) 11260 { 11261 if (a <= 19) 11262 return 0x87e1b0008348ll + 0x1000000ll * ((a) & 0x1f); 11263 __ody_csr_fatal("DSSX_LAT_TOTAL_WR_LATENCY_HI", 1, a, 0, 0, 0, 0, 0); 11264 } 11265 11266 #define typedef_ODY_DSSX_LAT_TOTAL_WR_LATENCY_HI(a) ody_dssx_lat_total_wr_latency_hi_t 11267 #define bustype_ODY_DSSX_LAT_TOTAL_WR_LATENCY_HI(a) CSR_TYPE_RSL 11268 #define basename_ODY_DSSX_LAT_TOTAL_WR_LATENCY_HI(a) "DSSX_LAT_TOTAL_WR_LATENCY_HI" 11269 #define device_bar_ODY_DSSX_LAT_TOTAL_WR_LATENCY_HI(a) 0x0 /* PF_BAR0 */ 11270 #define busnum_ODY_DSSX_LAT_TOTAL_WR_LATENCY_HI(a) (a) 11271 #define arguments_ODY_DSSX_LAT_TOTAL_WR_LATENCY_HI(a) (a), -1, -1, -1 11272 11273 /** 11274 * Register (RSL) dss#_lat_total_wr_latency_lo 11275 * 11276 * DSS Total Write Latency Low Register 11277 * Status register indicating number of total latency of all write requests since 11278 * latency calculation is enabled in DSS. 11279 * Total number of write latency in DFI cycles is {DSS_LAT_TOTAL_WR_LATENCY_HI, 11280 * DSS_LAT_TOTAL_WR_LATENCY_LO}. 11281 */ 11282 union ody_dssx_lat_total_wr_latency_lo { 11283 uint64_t u; 11284 struct ody_dssx_lat_total_wr_latency_lo_s { 11285 uint64_t total_wr_latency_lo : 64; 11286 } s; 11287 /* struct ody_dssx_lat_total_wr_latency_lo_s cn; */ 11288 }; 11289 typedef union ody_dssx_lat_total_wr_latency_lo ody_dssx_lat_total_wr_latency_lo_t; 11290 11291 static inline uint64_t ODY_DSSX_LAT_TOTAL_WR_LATENCY_LO(uint64_t a) __attribute__ ((pure, always_inline)); 11292 static inline uint64_t ODY_DSSX_LAT_TOTAL_WR_LATENCY_LO(uint64_t a) 11293 { 11294 if (a <= 19) 11295 return 0x87e1b0008340ll + 0x1000000ll * ((a) & 0x1f); 11296 __ody_csr_fatal("DSSX_LAT_TOTAL_WR_LATENCY_LO", 1, a, 0, 0, 0, 0, 0); 11297 } 11298 11299 #define typedef_ODY_DSSX_LAT_TOTAL_WR_LATENCY_LO(a) ody_dssx_lat_total_wr_latency_lo_t 11300 #define bustype_ODY_DSSX_LAT_TOTAL_WR_LATENCY_LO(a) CSR_TYPE_RSL 11301 #define basename_ODY_DSSX_LAT_TOTAL_WR_LATENCY_LO(a) "DSSX_LAT_TOTAL_WR_LATENCY_LO" 11302 #define device_bar_ODY_DSSX_LAT_TOTAL_WR_LATENCY_LO(a) 0x0 /* PF_BAR0 */ 11303 #define busnum_ODY_DSSX_LAT_TOTAL_WR_LATENCY_LO(a) (a) 11304 #define arguments_ODY_DSSX_LAT_TOTAL_WR_LATENCY_LO(a) (a), -1, -1, -1 11305 11306 /** 11307 * Register (RSL) dss#_lp_cfg 11308 * 11309 * DSS Low Power Configuration Register 11310 * Low-power mode configuration. 11311 */ 11312 union ody_dssx_lp_cfg { 11313 uint64_t u; 11314 struct ody_dssx_lp_cfg_s { 11315 uint64_t s_dfi_reset_force : 1; 11316 uint64_t s_dfi_cs_addr_force : 1; 11317 uint64_t s_put_phy_in_lp2_mode : 1; 11318 uint64_t s_sync_with_peer_dmc : 1; 11319 uint64_t reserved_4_63 : 60; 11320 } s; 11321 /* struct ody_dssx_lp_cfg_s cn; */ 11322 }; 11323 typedef union ody_dssx_lp_cfg ody_dssx_lp_cfg_t; 11324 11325 static inline uint64_t ODY_DSSX_LP_CFG(uint64_t a) __attribute__ ((pure, always_inline)); 11326 static inline uint64_t ODY_DSSX_LP_CFG(uint64_t a) 11327 { 11328 if (a <= 19) 11329 return 0x87e1b0000078ll + 0x1000000ll * ((a) & 0x1f); 11330 __ody_csr_fatal("DSSX_LP_CFG", 1, a, 0, 0, 0, 0, 0); 11331 } 11332 11333 #define typedef_ODY_DSSX_LP_CFG(a) ody_dssx_lp_cfg_t 11334 #define bustype_ODY_DSSX_LP_CFG(a) CSR_TYPE_RSL 11335 #define basename_ODY_DSSX_LP_CFG(a) "DSSX_LP_CFG" 11336 #define device_bar_ODY_DSSX_LP_CFG(a) 0x0 /* PF_BAR0 */ 11337 #define busnum_ODY_DSSX_LP_CFG(a) (a) 11338 #define arguments_ODY_DSSX_LP_CFG(a) (a), -1, -1, -1 11339 11340 /** 11341 * Register (RSL) dss#_lp_ctrl 11342 * 11343 * DSS Low Power Control Register 11344 * Low-power mode control. 11345 */ 11346 union ody_dssx_lp_ctrl { 11347 uint64_t u; 11348 struct ody_dssx_lp_ctrl_s { 11349 uint64_t s_lp_entry : 1; 11350 uint64_t s_lp_exit : 1; 11351 uint64_t s_lp_entry_ongoing : 1; 11352 uint64_t s_lp_exit_ongoing : 1; 11353 uint64_t reserved_4_63 : 60; 11354 } s; 11355 /* struct ody_dssx_lp_ctrl_s cn; */ 11356 }; 11357 typedef union ody_dssx_lp_ctrl ody_dssx_lp_ctrl_t; 11358 11359 static inline uint64_t ODY_DSSX_LP_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 11360 static inline uint64_t ODY_DSSX_LP_CTRL(uint64_t a) 11361 { 11362 if (a <= 19) 11363 return 0x87e1b0000070ll + 0x1000000ll * ((a) & 0x1f); 11364 __ody_csr_fatal("DSSX_LP_CTRL", 1, a, 0, 0, 0, 0, 0); 11365 } 11366 11367 #define typedef_ODY_DSSX_LP_CTRL(a) ody_dssx_lp_ctrl_t 11368 #define bustype_ODY_DSSX_LP_CTRL(a) CSR_TYPE_RSL 11369 #define basename_ODY_DSSX_LP_CTRL(a) "DSSX_LP_CTRL" 11370 #define device_bar_ODY_DSSX_LP_CTRL(a) 0x0 /* PF_BAR0 */ 11371 #define busnum_ODY_DSSX_LP_CTRL(a) (a) 11372 #define arguments_ODY_DSSX_LP_CTRL(a) (a), -1, -1, -1 11373 11374 /** 11375 * Register (RSL) dss#_lp_status 11376 * 11377 * DSS Low Power Status Register 11378 * Low-power mode status, this register indicates if low power and self refresh modes are succeeded. 11379 */ 11380 union ody_dssx_lp_status { 11381 uint64_t u; 11382 struct ody_dssx_lp_status_s { 11383 uint64_t s_dram_sre_status : 1; 11384 uint64_t s_phy_lp2_status : 1; 11385 uint64_t s_phy_lpx_status : 1; 11386 uint64_t s_low_power_state : 2; 11387 uint64_t s_selfref_type_status_mirror : 4; 11388 uint64_t reserved_9_63 : 55; 11389 } s; 11390 /* struct ody_dssx_lp_status_s cn; */ 11391 }; 11392 typedef union ody_dssx_lp_status ody_dssx_lp_status_t; 11393 11394 static inline uint64_t ODY_DSSX_LP_STATUS(uint64_t a) __attribute__ ((pure, always_inline)); 11395 static inline uint64_t ODY_DSSX_LP_STATUS(uint64_t a) 11396 { 11397 if (a <= 19) 11398 return 0x87e1b0000080ll + 0x1000000ll * ((a) & 0x1f); 11399 __ody_csr_fatal("DSSX_LP_STATUS", 1, a, 0, 0, 0, 0, 0); 11400 } 11401 11402 #define typedef_ODY_DSSX_LP_STATUS(a) ody_dssx_lp_status_t 11403 #define bustype_ODY_DSSX_LP_STATUS(a) CSR_TYPE_RSL 11404 #define basename_ODY_DSSX_LP_STATUS(a) "DSSX_LP_STATUS" 11405 #define device_bar_ODY_DSSX_LP_STATUS(a) 0x0 /* PF_BAR0 */ 11406 #define busnum_ODY_DSSX_LP_STATUS(a) (a) 11407 #define arguments_ODY_DSSX_LP_STATUS(a) (a), -1, -1, -1 11408 11409 /** 11410 * Register (RSL) dss#_mc_core_reset_n 11411 * 11412 * DSS DFI Domain Reset Register 11413 * DFI clock software reset - active low. 11414 */ 11415 union ody_dssx_mc_core_reset_n { 11416 uint64_t u; 11417 struct ody_dssx_mc_core_reset_n_s { 11418 uint64_t s_mc_core_reset_n : 1; 11419 uint64_t reserved_1_63 : 63; 11420 } s; 11421 /* struct ody_dssx_mc_core_reset_n_s cn; */ 11422 }; 11423 typedef union ody_dssx_mc_core_reset_n ody_dssx_mc_core_reset_n_t; 11424 11425 static inline uint64_t ODY_DSSX_MC_CORE_RESET_N(uint64_t a) __attribute__ ((pure, always_inline)); 11426 static inline uint64_t ODY_DSSX_MC_CORE_RESET_N(uint64_t a) 11427 { 11428 if (a <= 19) 11429 return 0x87e1b0000000ll + 0x1000000ll * ((a) & 0x1f); 11430 __ody_csr_fatal("DSSX_MC_CORE_RESET_N", 1, a, 0, 0, 0, 0, 0); 11431 } 11432 11433 #define typedef_ODY_DSSX_MC_CORE_RESET_N(a) ody_dssx_mc_core_reset_n_t 11434 #define bustype_ODY_DSSX_MC_CORE_RESET_N(a) CSR_TYPE_RSL 11435 #define basename_ODY_DSSX_MC_CORE_RESET_N(a) "DSSX_MC_CORE_RESET_N" 11436 #define device_bar_ODY_DSSX_MC_CORE_RESET_N(a) 0x0 /* PF_BAR0 */ 11437 #define busnum_ODY_DSSX_MC_CORE_RESET_N(a) (a) 11438 #define arguments_ODY_DSSX_MC_CORE_RESET_N(a) (a), -1, -1, -1 11439 11440 /** 11441 * Register (RSL) dss#_mc_ctrl 11442 * 11443 * DSS Memory Controller Control Register 11444 * Memory controller control register. 11445 */ 11446 union ody_dssx_mc_ctrl { 11447 uint64_t u; 11448 struct ody_dssx_mc_ctrl_s { 11449 uint64_t s_mc_csysreq : 1; 11450 uint64_t s_mc_csysack : 1; 11451 uint64_t s_mc_cactive : 1; 11452 uint64_t reserved_3_63 : 61; 11453 } s; 11454 /* struct ody_dssx_mc_ctrl_s cn; */ 11455 }; 11456 typedef union ody_dssx_mc_ctrl ody_dssx_mc_ctrl_t; 11457 11458 static inline uint64_t ODY_DSSX_MC_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 11459 static inline uint64_t ODY_DSSX_MC_CTRL(uint64_t a) 11460 { 11461 if (a <= 19) 11462 return 0x87e1b0000050ll + 0x1000000ll * ((a) & 0x1f); 11463 __ody_csr_fatal("DSSX_MC_CTRL", 1, a, 0, 0, 0, 0, 0); 11464 } 11465 11466 #define typedef_ODY_DSSX_MC_CTRL(a) ody_dssx_mc_ctrl_t 11467 #define bustype_ODY_DSSX_MC_CTRL(a) CSR_TYPE_RSL 11468 #define basename_ODY_DSSX_MC_CTRL(a) "DSSX_MC_CTRL" 11469 #define device_bar_ODY_DSSX_MC_CTRL(a) 0x0 /* PF_BAR0 */ 11470 #define busnum_ODY_DSSX_MC_CTRL(a) (a) 11471 #define arguments_ODY_DSSX_MC_CTRL(a) (a), -1, -1, -1 11472 11473 /** 11474 * Register (RSL) dss#_mct_crc_ctrl 11475 * 11476 * DSS MCT CRC Control Register 11477 * MCT CRC control register. 11478 * This register should be configured only when (DSS_MCT()_ENABLE[S_MCT_EN] = 0). 11479 */ 11480 union ody_dssx_mct_crc_ctrl { 11481 uint64_t u; 11482 struct ody_dssx_mct_crc_ctrl_s { 11483 uint64_t wr_crc_en : 1; 11484 uint64_t rd_crc_en : 1; 11485 uint64_t mc_wr_crc_is_enabled : 1; 11486 uint64_t mc_rd_crc_is_enabled : 1; 11487 uint64_t dis_rd_crc_ecc_upr_nibble : 1; 11488 uint64_t reserved_5_63 : 59; 11489 } s; 11490 /* struct ody_dssx_mct_crc_ctrl_s cn; */ 11491 }; 11492 typedef union ody_dssx_mct_crc_ctrl ody_dssx_mct_crc_ctrl_t; 11493 11494 static inline uint64_t ODY_DSSX_MCT_CRC_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 11495 static inline uint64_t ODY_DSSX_MCT_CRC_CTRL(uint64_t a) 11496 { 11497 if (a <= 19) 11498 return 0x87e1b0010010ll + 0x1000000ll * ((a) & 0x1f); 11499 __ody_csr_fatal("DSSX_MCT_CRC_CTRL", 1, a, 0, 0, 0, 0, 0); 11500 } 11501 11502 #define typedef_ODY_DSSX_MCT_CRC_CTRL(a) ody_dssx_mct_crc_ctrl_t 11503 #define bustype_ODY_DSSX_MCT_CRC_CTRL(a) CSR_TYPE_RSL 11504 #define basename_ODY_DSSX_MCT_CRC_CTRL(a) "DSSX_MCT_CRC_CTRL" 11505 #define device_bar_ODY_DSSX_MCT_CRC_CTRL(a) 0x0 /* PF_BAR0 */ 11506 #define busnum_ODY_DSSX_MCT_CRC_CTRL(a) (a) 11507 #define arguments_ODY_DSSX_MCT_CRC_CTRL(a) (a), -1, -1, -1 11508 11509 /** 11510 * Register (RSL) dss#_mct_ctrl 11511 * 11512 * DSS MCT Control Register 11513 * MCT module control register. 11514 * This register should be configured only when (DSS_MCT()_ENABLE[S_MCT_EN] = 0). 11515 */ 11516 union ody_dssx_mct_ctrl { 11517 uint64_t u; 11518 struct ody_dssx_mct_ctrl_s { 11519 uint64_t reserved_0_1 : 2; 11520 uint64_t cmd_type : 1; 11521 uint64_t dfi_data_cs_polarity : 1; 11522 uint64_t key_scramble : 1; 11523 uint64_t reserved_5 : 1; 11524 uint64_t aes_bypass : 1; 11525 uint64_t ecc_en : 1; 11526 uint64_t data_width : 1; 11527 uint64_t reserved_9_15 : 7; 11528 uint64_t active_ranks : 4; 11529 uint64_t cmd_delay_in_dfi_cyc : 1; 11530 uint64_t reserved_21_63 : 43; 11531 } s; 11532 /* struct ody_dssx_mct_ctrl_s cn; */ 11533 }; 11534 typedef union ody_dssx_mct_ctrl ody_dssx_mct_ctrl_t; 11535 11536 static inline uint64_t ODY_DSSX_MCT_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 11537 static inline uint64_t ODY_DSSX_MCT_CTRL(uint64_t a) 11538 { 11539 if (a <= 19) 11540 return 0x87e1b0010008ll + 0x1000000ll * ((a) & 0x1f); 11541 __ody_csr_fatal("DSSX_MCT_CTRL", 1, a, 0, 0, 0, 0, 0); 11542 } 11543 11544 #define typedef_ODY_DSSX_MCT_CTRL(a) ody_dssx_mct_ctrl_t 11545 #define bustype_ODY_DSSX_MCT_CTRL(a) CSR_TYPE_RSL 11546 #define basename_ODY_DSSX_MCT_CTRL(a) "DSSX_MCT_CTRL" 11547 #define device_bar_ODY_DSSX_MCT_CTRL(a) 0x0 /* PF_BAR0 */ 11548 #define busnum_ODY_DSSX_MCT_CTRL(a) (a) 11549 #define arguments_ODY_DSSX_MCT_CTRL(a) (a), -1, -1, -1 11550 11551 /** 11552 * Register (RSL) dss#_mct_current_key_127_64# 11553 * 11554 * DSS MCT CURRENT KEY Register 11555 * Holds bits[127:64] of the current key used for encryption of selected index. 11556 */ 11557 union ody_dssx_mct_current_key_127_64x { 11558 uint64_t u; 11559 struct ody_dssx_mct_current_key_127_64x_s { 11560 uint64_t current_key_127_64 : 64; 11561 } s; 11562 /* struct ody_dssx_mct_current_key_127_64x_s cn; */ 11563 }; 11564 typedef union ody_dssx_mct_current_key_127_64x ody_dssx_mct_current_key_127_64x_t; 11565 11566 static inline uint64_t ODY_DSSX_MCT_CURRENT_KEY_127_64X(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 11567 static inline uint64_t ODY_DSSX_MCT_CURRENT_KEY_127_64X(uint64_t a, uint64_t b) 11568 { 11569 if ((a <= 19) && (b <= 3)) 11570 return 0x87e1b00100c0ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 11571 __ody_csr_fatal("DSSX_MCT_CURRENT_KEY_127_64X", 2, a, b, 0, 0, 0, 0); 11572 } 11573 11574 #define typedef_ODY_DSSX_MCT_CURRENT_KEY_127_64X(a, b) ody_dssx_mct_current_key_127_64x_t 11575 #define bustype_ODY_DSSX_MCT_CURRENT_KEY_127_64X(a, b) CSR_TYPE_RSL 11576 #define basename_ODY_DSSX_MCT_CURRENT_KEY_127_64X(a, b) "DSSX_MCT_CURRENT_KEY_127_64X" 11577 #define device_bar_ODY_DSSX_MCT_CURRENT_KEY_127_64X(a, b) 0x0 /* PF_BAR0 */ 11578 #define busnum_ODY_DSSX_MCT_CURRENT_KEY_127_64X(a, b) (a) 11579 #define arguments_ODY_DSSX_MCT_CURRENT_KEY_127_64X(a, b) (a), (b), -1, -1 11580 11581 /** 11582 * Register (RSL) dss#_mct_current_key_63_0# 11583 * 11584 * DSS MCT CURRENT ENCRYPTION KEY Register 11585 * Holds bits[63:0] of the current key used for encryption of selected index. 11586 */ 11587 union ody_dssx_mct_current_key_63_0x { 11588 uint64_t u; 11589 struct ody_dssx_mct_current_key_63_0x_s { 11590 uint64_t current_key_63_0 : 64; 11591 } s; 11592 /* struct ody_dssx_mct_current_key_63_0x_s cn; */ 11593 }; 11594 typedef union ody_dssx_mct_current_key_63_0x ody_dssx_mct_current_key_63_0x_t; 11595 11596 static inline uint64_t ODY_DSSX_MCT_CURRENT_KEY_63_0X(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 11597 static inline uint64_t ODY_DSSX_MCT_CURRENT_KEY_63_0X(uint64_t a, uint64_t b) 11598 { 11599 if ((a <= 19) && (b <= 3)) 11600 return 0x87e1b00110a0ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 11601 __ody_csr_fatal("DSSX_MCT_CURRENT_KEY_63_0X", 2, a, b, 0, 0, 0, 0); 11602 } 11603 11604 #define typedef_ODY_DSSX_MCT_CURRENT_KEY_63_0X(a, b) ody_dssx_mct_current_key_63_0x_t 11605 #define bustype_ODY_DSSX_MCT_CURRENT_KEY_63_0X(a, b) CSR_TYPE_RSL 11606 #define basename_ODY_DSSX_MCT_CURRENT_KEY_63_0X(a, b) "DSSX_MCT_CURRENT_KEY_63_0X" 11607 #define device_bar_ODY_DSSX_MCT_CURRENT_KEY_63_0X(a, b) 0x0 /* PF_BAR0 */ 11608 #define busnum_ODY_DSSX_MCT_CURRENT_KEY_63_0X(a, b) (a) 11609 #define arguments_ODY_DSSX_MCT_CURRENT_KEY_63_0X(a, b) (a), (b), -1, -1 11610 11611 /** 11612 * Register (RSL) dss#_mct_dbg_sw_data_high 11613 * 11614 * DSS MCT Software Debug Data Register 11615 * Holds the higher bits of the debug data used for the encryption/decryption operation 11616 * of software commands. 11617 */ 11618 union ody_dssx_mct_dbg_sw_data_high { 11619 uint64_t u; 11620 struct ody_dssx_mct_dbg_sw_data_high_s { 11621 uint64_t dbg_sw_data_hi : 64; 11622 } s; 11623 /* struct ody_dssx_mct_dbg_sw_data_high_s cn; */ 11624 }; 11625 typedef union ody_dssx_mct_dbg_sw_data_high ody_dssx_mct_dbg_sw_data_high_t; 11626 11627 static inline uint64_t ODY_DSSX_MCT_DBG_SW_DATA_HIGH(uint64_t a) __attribute__ ((pure, always_inline)); 11628 static inline uint64_t ODY_DSSX_MCT_DBG_SW_DATA_HIGH(uint64_t a) 11629 { 11630 if (a <= 19) 11631 return 0x87e1b00103f8ll + 0x1000000ll * ((a) & 0x1f); 11632 __ody_csr_fatal("DSSX_MCT_DBG_SW_DATA_HIGH", 1, a, 0, 0, 0, 0, 0); 11633 } 11634 11635 #define typedef_ODY_DSSX_MCT_DBG_SW_DATA_HIGH(a) ody_dssx_mct_dbg_sw_data_high_t 11636 #define bustype_ODY_DSSX_MCT_DBG_SW_DATA_HIGH(a) CSR_TYPE_RSL 11637 #define basename_ODY_DSSX_MCT_DBG_SW_DATA_HIGH(a) "DSSX_MCT_DBG_SW_DATA_HIGH" 11638 #define device_bar_ODY_DSSX_MCT_DBG_SW_DATA_HIGH(a) 0x0 /* PF_BAR0 */ 11639 #define busnum_ODY_DSSX_MCT_DBG_SW_DATA_HIGH(a) (a) 11640 #define arguments_ODY_DSSX_MCT_DBG_SW_DATA_HIGH(a) (a), -1, -1, -1 11641 11642 /** 11643 * Register (RSL) dss#_mct_dbg_sw_data_low 11644 * 11645 * DSS MCT Software Debug Data Register 11646 * Holds the lower bits of the debug data used for the encryption/decryption operation 11647 * of software commands. 11648 */ 11649 union ody_dssx_mct_dbg_sw_data_low { 11650 uint64_t u; 11651 struct ody_dssx_mct_dbg_sw_data_low_s { 11652 uint64_t dbg_sw_data_lo : 64; 11653 } s; 11654 /* struct ody_dssx_mct_dbg_sw_data_low_s cn; */ 11655 }; 11656 typedef union ody_dssx_mct_dbg_sw_data_low ody_dssx_mct_dbg_sw_data_low_t; 11657 11658 static inline uint64_t ODY_DSSX_MCT_DBG_SW_DATA_LOW(uint64_t a) __attribute__ ((pure, always_inline)); 11659 static inline uint64_t ODY_DSSX_MCT_DBG_SW_DATA_LOW(uint64_t a) 11660 { 11661 if (a <= 19) 11662 return 0x87e1b00103f0ll + 0x1000000ll * ((a) & 0x1f); 11663 __ody_csr_fatal("DSSX_MCT_DBG_SW_DATA_LOW", 1, a, 0, 0, 0, 0, 0); 11664 } 11665 11666 #define typedef_ODY_DSSX_MCT_DBG_SW_DATA_LOW(a) ody_dssx_mct_dbg_sw_data_low_t 11667 #define bustype_ODY_DSSX_MCT_DBG_SW_DATA_LOW(a) CSR_TYPE_RSL 11668 #define basename_ODY_DSSX_MCT_DBG_SW_DATA_LOW(a) "DSSX_MCT_DBG_SW_DATA_LOW" 11669 #define device_bar_ODY_DSSX_MCT_DBG_SW_DATA_LOW(a) 0x0 /* PF_BAR0 */ 11670 #define busnum_ODY_DSSX_MCT_DBG_SW_DATA_LOW(a) (a) 11671 #define arguments_ODY_DSSX_MCT_DBG_SW_DATA_LOW(a) (a), -1, -1, -1 11672 11673 /** 11674 * Register (RSL) dss#_mct_dbg_sw_key_127_64 11675 * 11676 * DSS MCT Software Debug Key Register 11677 * Holds bits[127:64] of the debug key used for the encryption/decryption operation 11678 * of software commands. 11679 */ 11680 union ody_dssx_mct_dbg_sw_key_127_64 { 11681 uint64_t u; 11682 struct ody_dssx_mct_dbg_sw_key_127_64_s { 11683 uint64_t dbg_sw_key_127_64 : 64; 11684 } s; 11685 /* struct ody_dssx_mct_dbg_sw_key_127_64_s cn; */ 11686 }; 11687 typedef union ody_dssx_mct_dbg_sw_key_127_64 ody_dssx_mct_dbg_sw_key_127_64_t; 11688 11689 static inline uint64_t ODY_DSSX_MCT_DBG_SW_KEY_127_64(uint64_t a) __attribute__ ((pure, always_inline)); 11690 static inline uint64_t ODY_DSSX_MCT_DBG_SW_KEY_127_64(uint64_t a) 11691 { 11692 if (a <= 19) 11693 return 0x87e1b00103d8ll + 0x1000000ll * ((a) & 0x1f); 11694 __ody_csr_fatal("DSSX_MCT_DBG_SW_KEY_127_64", 1, a, 0, 0, 0, 0, 0); 11695 } 11696 11697 #define typedef_ODY_DSSX_MCT_DBG_SW_KEY_127_64(a) ody_dssx_mct_dbg_sw_key_127_64_t 11698 #define bustype_ODY_DSSX_MCT_DBG_SW_KEY_127_64(a) CSR_TYPE_RSL 11699 #define basename_ODY_DSSX_MCT_DBG_SW_KEY_127_64(a) "DSSX_MCT_DBG_SW_KEY_127_64" 11700 #define device_bar_ODY_DSSX_MCT_DBG_SW_KEY_127_64(a) 0x0 /* PF_BAR0 */ 11701 #define busnum_ODY_DSSX_MCT_DBG_SW_KEY_127_64(a) (a) 11702 #define arguments_ODY_DSSX_MCT_DBG_SW_KEY_127_64(a) (a), -1, -1, -1 11703 11704 /** 11705 * Register (RSL) dss#_mct_dbg_sw_key_63_0 11706 * 11707 * DSS MCT Software Debug Key Register 11708 * Holds bits[63:0] of the debug key used for the encryption/decryption operation 11709 * of software commands. 11710 */ 11711 union ody_dssx_mct_dbg_sw_key_63_0 { 11712 uint64_t u; 11713 struct ody_dssx_mct_dbg_sw_key_63_0_s { 11714 uint64_t dbg_sw_key_63_0 : 64; 11715 } s; 11716 /* struct ody_dssx_mct_dbg_sw_key_63_0_s cn; */ 11717 }; 11718 typedef union ody_dssx_mct_dbg_sw_key_63_0 ody_dssx_mct_dbg_sw_key_63_0_t; 11719 11720 static inline uint64_t ODY_DSSX_MCT_DBG_SW_KEY_63_0(uint64_t a) __attribute__ ((pure, always_inline)); 11721 static inline uint64_t ODY_DSSX_MCT_DBG_SW_KEY_63_0(uint64_t a) 11722 { 11723 if (a <= 19) 11724 return 0x87e1b00103d0ll + 0x1000000ll * ((a) & 0x1f); 11725 __ody_csr_fatal("DSSX_MCT_DBG_SW_KEY_63_0", 1, a, 0, 0, 0, 0, 0); 11726 } 11727 11728 #define typedef_ODY_DSSX_MCT_DBG_SW_KEY_63_0(a) ody_dssx_mct_dbg_sw_key_63_0_t 11729 #define bustype_ODY_DSSX_MCT_DBG_SW_KEY_63_0(a) CSR_TYPE_RSL 11730 #define basename_ODY_DSSX_MCT_DBG_SW_KEY_63_0(a) "DSSX_MCT_DBG_SW_KEY_63_0" 11731 #define device_bar_ODY_DSSX_MCT_DBG_SW_KEY_63_0(a) 0x0 /* PF_BAR0 */ 11732 #define busnum_ODY_DSSX_MCT_DBG_SW_KEY_63_0(a) (a) 11733 #define arguments_ODY_DSSX_MCT_DBG_SW_KEY_63_0(a) (a), -1, -1, -1 11734 11735 /** 11736 * Register (RSL) dss#_mct_dbg_sw_op_cmd_ctrl 11737 * 11738 * DSS MCT Software Operation Control Register 11739 * This register is RW/HW handshake control, using DBG_* registers that allow software to initiate 11740 * encryption / decryption commands to MCT. 11741 */ 11742 union ody_dssx_mct_dbg_sw_op_cmd_ctrl { 11743 uint64_t u; 11744 struct ody_dssx_mct_dbg_sw_op_cmd_ctrl_s { 11745 uint64_t sw_op_type : 1; 11746 uint64_t sw_op_behavior : 1; 11747 uint64_t reserved_2_9 : 8; 11748 uint64_t sw_op_sys_addr : 52; 11749 uint64_t reserved_62_63 : 2; 11750 } s; 11751 /* struct ody_dssx_mct_dbg_sw_op_cmd_ctrl_s cn; */ 11752 }; 11753 typedef union ody_dssx_mct_dbg_sw_op_cmd_ctrl ody_dssx_mct_dbg_sw_op_cmd_ctrl_t; 11754 11755 static inline uint64_t ODY_DSSX_MCT_DBG_SW_OP_CMD_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 11756 static inline uint64_t ODY_DSSX_MCT_DBG_SW_OP_CMD_CTRL(uint64_t a) 11757 { 11758 if (a <= 19) 11759 return 0x87e1b00103c8ll + 0x1000000ll * ((a) & 0x1f); 11760 __ody_csr_fatal("DSSX_MCT_DBG_SW_OP_CMD_CTRL", 1, a, 0, 0, 0, 0, 0); 11761 } 11762 11763 #define typedef_ODY_DSSX_MCT_DBG_SW_OP_CMD_CTRL(a) ody_dssx_mct_dbg_sw_op_cmd_ctrl_t 11764 #define bustype_ODY_DSSX_MCT_DBG_SW_OP_CMD_CTRL(a) CSR_TYPE_RSL 11765 #define basename_ODY_DSSX_MCT_DBG_SW_OP_CMD_CTRL(a) "DSSX_MCT_DBG_SW_OP_CMD_CTRL" 11766 #define device_bar_ODY_DSSX_MCT_DBG_SW_OP_CMD_CTRL(a) 0x0 /* PF_BAR0 */ 11767 #define busnum_ODY_DSSX_MCT_DBG_SW_OP_CMD_CTRL(a) (a) 11768 #define arguments_ODY_DSSX_MCT_DBG_SW_OP_CMD_CTRL(a) (a), -1, -1, -1 11769 11770 /** 11771 * Register (RSL) dss#_mct_dbg_sw_op_ctrl 11772 * 11773 * DSS MCT Software Operation Control Register 11774 * This register is the RW/HW handshake control, using DBG_* registers that allow software 11775 * to initiate encryption / decryption commands to MCT. 11776 */ 11777 union ody_dssx_mct_dbg_sw_op_ctrl { 11778 uint64_t u; 11779 struct ody_dssx_mct_dbg_sw_op_ctrl_s { 11780 uint64_t run : 1; 11781 uint64_t reserved_1_63 : 63; 11782 } s; 11783 /* struct ody_dssx_mct_dbg_sw_op_ctrl_s cn; */ 11784 }; 11785 typedef union ody_dssx_mct_dbg_sw_op_ctrl ody_dssx_mct_dbg_sw_op_ctrl_t; 11786 11787 static inline uint64_t ODY_DSSX_MCT_DBG_SW_OP_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 11788 static inline uint64_t ODY_DSSX_MCT_DBG_SW_OP_CTRL(uint64_t a) 11789 { 11790 if (a <= 19) 11791 return 0x87e1b00103c0ll + 0x1000000ll * ((a) & 0x1f); 11792 __ody_csr_fatal("DSSX_MCT_DBG_SW_OP_CTRL", 1, a, 0, 0, 0, 0, 0); 11793 } 11794 11795 #define typedef_ODY_DSSX_MCT_DBG_SW_OP_CTRL(a) ody_dssx_mct_dbg_sw_op_ctrl_t 11796 #define bustype_ODY_DSSX_MCT_DBG_SW_OP_CTRL(a) CSR_TYPE_RSL 11797 #define basename_ODY_DSSX_MCT_DBG_SW_OP_CTRL(a) "DSSX_MCT_DBG_SW_OP_CTRL" 11798 #define device_bar_ODY_DSSX_MCT_DBG_SW_OP_CTRL(a) 0x0 /* PF_BAR0 */ 11799 #define busnum_ODY_DSSX_MCT_DBG_SW_OP_CTRL(a) (a) 11800 #define arguments_ODY_DSSX_MCT_DBG_SW_OP_CTRL(a) (a), -1, -1, -1 11801 11802 /** 11803 * Register (RSL) dss#_mct_dbg_sw_resp_high 11804 * 11805 * DSS MCT Software Debug Response Register 11806 * Holds the higher bits of the debug response data for the 11807 * encryption/decryption operation of software commands. 11808 */ 11809 union ody_dssx_mct_dbg_sw_resp_high { 11810 uint64_t u; 11811 struct ody_dssx_mct_dbg_sw_resp_high_s { 11812 uint64_t dbg_sw_data_hi : 64; 11813 } s; 11814 /* struct ody_dssx_mct_dbg_sw_resp_high_s cn; */ 11815 }; 11816 typedef union ody_dssx_mct_dbg_sw_resp_high ody_dssx_mct_dbg_sw_resp_high_t; 11817 11818 static inline uint64_t ODY_DSSX_MCT_DBG_SW_RESP_HIGH(uint64_t a) __attribute__ ((pure, always_inline)); 11819 static inline uint64_t ODY_DSSX_MCT_DBG_SW_RESP_HIGH(uint64_t a) 11820 { 11821 if (a <= 19) 11822 return 0x87e1b0010408ll + 0x1000000ll * ((a) & 0x1f); 11823 __ody_csr_fatal("DSSX_MCT_DBG_SW_RESP_HIGH", 1, a, 0, 0, 0, 0, 0); 11824 } 11825 11826 #define typedef_ODY_DSSX_MCT_DBG_SW_RESP_HIGH(a) ody_dssx_mct_dbg_sw_resp_high_t 11827 #define bustype_ODY_DSSX_MCT_DBG_SW_RESP_HIGH(a) CSR_TYPE_RSL 11828 #define basename_ODY_DSSX_MCT_DBG_SW_RESP_HIGH(a) "DSSX_MCT_DBG_SW_RESP_HIGH" 11829 #define device_bar_ODY_DSSX_MCT_DBG_SW_RESP_HIGH(a) 0x0 /* PF_BAR0 */ 11830 #define busnum_ODY_DSSX_MCT_DBG_SW_RESP_HIGH(a) (a) 11831 #define arguments_ODY_DSSX_MCT_DBG_SW_RESP_HIGH(a) (a), -1, -1, -1 11832 11833 /** 11834 * Register (RSL) dss#_mct_dbg_sw_resp_low 11835 * 11836 * DSS MCT Software Debug Response Register 11837 * Holds the lower bits of the debug response data for the 11838 * encryption/decryption operation of software commands. 11839 */ 11840 union ody_dssx_mct_dbg_sw_resp_low { 11841 uint64_t u; 11842 struct ody_dssx_mct_dbg_sw_resp_low_s { 11843 uint64_t dbg_sw_resp_lo : 64; 11844 } s; 11845 /* struct ody_dssx_mct_dbg_sw_resp_low_s cn; */ 11846 }; 11847 typedef union ody_dssx_mct_dbg_sw_resp_low ody_dssx_mct_dbg_sw_resp_low_t; 11848 11849 static inline uint64_t ODY_DSSX_MCT_DBG_SW_RESP_LOW(uint64_t a) __attribute__ ((pure, always_inline)); 11850 static inline uint64_t ODY_DSSX_MCT_DBG_SW_RESP_LOW(uint64_t a) 11851 { 11852 if (a <= 19) 11853 return 0x87e1b0010400ll + 0x1000000ll * ((a) & 0x1f); 11854 __ody_csr_fatal("DSSX_MCT_DBG_SW_RESP_LOW", 1, a, 0, 0, 0, 0, 0); 11855 } 11856 11857 #define typedef_ODY_DSSX_MCT_DBG_SW_RESP_LOW(a) ody_dssx_mct_dbg_sw_resp_low_t 11858 #define bustype_ODY_DSSX_MCT_DBG_SW_RESP_LOW(a) CSR_TYPE_RSL 11859 #define basename_ODY_DSSX_MCT_DBG_SW_RESP_LOW(a) "DSSX_MCT_DBG_SW_RESP_LOW" 11860 #define device_bar_ODY_DSSX_MCT_DBG_SW_RESP_LOW(a) 0x0 /* PF_BAR0 */ 11861 #define busnum_ODY_DSSX_MCT_DBG_SW_RESP_LOW(a) (a) 11862 #define arguments_ODY_DSSX_MCT_DBG_SW_RESP_LOW(a) (a), -1, -1, -1 11863 11864 /** 11865 * Register (RSL) dss#_mct_default_win_cfg 11866 * 11867 * DSS MCT Default Window Configuration Register 11868 * Defines the default window configuration. 11869 * This register should be configured only when (DSS_MCT()_ENABLE[S_MCT_EN] = 0). 11870 */ 11871 union ody_dssx_mct_default_win_cfg { 11872 uint64_t u; 11873 struct ody_dssx_mct_default_win_cfg_s { 11874 uint64_t default_enc_en : 1; 11875 uint64_t default_key_index : 2; 11876 uint64_t reserved_3_63 : 61; 11877 } s; 11878 /* struct ody_dssx_mct_default_win_cfg_s cn; */ 11879 }; 11880 typedef union ody_dssx_mct_default_win_cfg ody_dssx_mct_default_win_cfg_t; 11881 11882 static inline uint64_t ODY_DSSX_MCT_DEFAULT_WIN_CFG(uint64_t a) __attribute__ ((pure, always_inline)); 11883 static inline uint64_t ODY_DSSX_MCT_DEFAULT_WIN_CFG(uint64_t a) 11884 { 11885 if (a <= 19) 11886 return 0x87e1b0010228ll + 0x1000000ll * ((a) & 0x1f); 11887 __ody_csr_fatal("DSSX_MCT_DEFAULT_WIN_CFG", 1, a, 0, 0, 0, 0, 0); 11888 } 11889 11890 #define typedef_ODY_DSSX_MCT_DEFAULT_WIN_CFG(a) ody_dssx_mct_default_win_cfg_t 11891 #define bustype_ODY_DSSX_MCT_DEFAULT_WIN_CFG(a) CSR_TYPE_RSL 11892 #define basename_ODY_DSSX_MCT_DEFAULT_WIN_CFG(a) "DSSX_MCT_DEFAULT_WIN_CFG" 11893 #define device_bar_ODY_DSSX_MCT_DEFAULT_WIN_CFG(a) 0x0 /* PF_BAR0 */ 11894 #define busnum_ODY_DSSX_MCT_DEFAULT_WIN_CFG(a) (a) 11895 #define arguments_ODY_DSSX_MCT_DEFAULT_WIN_CFG(a) (a), -1, -1, -1 11896 11897 /** 11898 * Register (RSL) dss#_mct_enable 11899 * 11900 * DSS MCT Enable Register 11901 * MCT block enable register. 11902 */ 11903 union ody_dssx_mct_enable { 11904 uint64_t u; 11905 struct ody_dssx_mct_enable_s { 11906 uint64_t mct_en : 1; 11907 uint64_t mct_clk_dis : 1; 11908 uint64_t mct_is_active : 1; 11909 uint64_t reserved_3_63 : 61; 11910 } s; 11911 /* struct ody_dssx_mct_enable_s cn; */ 11912 }; 11913 typedef union ody_dssx_mct_enable ody_dssx_mct_enable_t; 11914 11915 static inline uint64_t ODY_DSSX_MCT_ENABLE(uint64_t a) __attribute__ ((pure, always_inline)); 11916 static inline uint64_t ODY_DSSX_MCT_ENABLE(uint64_t a) 11917 { 11918 if (a <= 19) 11919 return 0x87e1b0010000ll + 0x1000000ll * ((a) & 0x1f); 11920 __ody_csr_fatal("DSSX_MCT_ENABLE", 1, a, 0, 0, 0, 0, 0); 11921 } 11922 11923 #define typedef_ODY_DSSX_MCT_ENABLE(a) ody_dssx_mct_enable_t 11924 #define bustype_ODY_DSSX_MCT_ENABLE(a) CSR_TYPE_RSL 11925 #define basename_ODY_DSSX_MCT_ENABLE(a) "DSSX_MCT_ENABLE" 11926 #define device_bar_ODY_DSSX_MCT_ENABLE(a) 0x0 /* PF_BAR0 */ 11927 #define busnum_ODY_DSSX_MCT_ENABLE(a) (a) 11928 #define arguments_ODY_DSSX_MCT_ENABLE(a) (a), -1, -1, -1 11929 11930 /** 11931 * Register (RSL) dss#_mct_global_clock_enable 11932 * 11933 * DSS MCT Global Clock Enable Register 11934 * Force MCT sub-blocks coarse clock to be always on. 11935 */ 11936 union ody_dssx_mct_global_clock_enable { 11937 uint64_t u; 11938 struct ody_dssx_mct_global_clock_enable_s { 11939 uint64_t csr_core_clk_force : 1; 11940 uint64_t wr_path_mc_side_clk_force : 1; 11941 uint64_t rd_en_path_mc_side_clk_force : 1; 11942 uint64_t rddat_path_mc_side_clk_force : 1; 11943 uint64_t rden_path_phy_side_clk_force : 1; 11944 uint64_t wr_path_phy_side_clk_force : 1; 11945 uint64_t rddat_path_phy_side_clk_force : 1; 11946 uint64_t rd_data_cs_path_clk_force : 1; 11947 uint64_t wr_data_cs_path_clk_force : 1; 11948 uint64_t cmd_dec_clk_force : 1; 11949 uint64_t crypto_wr_path_clk_force : 1; 11950 uint64_t crypto_rd_path_clk_force : 1; 11951 uint64_t reserved_12_63 : 52; 11952 } s; 11953 /* struct ody_dssx_mct_global_clock_enable_s cn; */ 11954 }; 11955 typedef union ody_dssx_mct_global_clock_enable ody_dssx_mct_global_clock_enable_t; 11956 11957 static inline uint64_t ODY_DSSX_MCT_GLOBAL_CLOCK_ENABLE(uint64_t a) __attribute__ ((pure, always_inline)); 11958 static inline uint64_t ODY_DSSX_MCT_GLOBAL_CLOCK_ENABLE(uint64_t a) 11959 { 11960 if (a <= 19) 11961 return 0x87e1b0010410ll + 0x1000000ll * ((a) & 0x1f); 11962 __ody_csr_fatal("DSSX_MCT_GLOBAL_CLOCK_ENABLE", 1, a, 0, 0, 0, 0, 0); 11963 } 11964 11965 #define typedef_ODY_DSSX_MCT_GLOBAL_CLOCK_ENABLE(a) ody_dssx_mct_global_clock_enable_t 11966 #define bustype_ODY_DSSX_MCT_GLOBAL_CLOCK_ENABLE(a) CSR_TYPE_RSL 11967 #define basename_ODY_DSSX_MCT_GLOBAL_CLOCK_ENABLE(a) "DSSX_MCT_GLOBAL_CLOCK_ENABLE" 11968 #define device_bar_ODY_DSSX_MCT_GLOBAL_CLOCK_ENABLE(a) 0x0 /* PF_BAR0 */ 11969 #define busnum_ODY_DSSX_MCT_GLOBAL_CLOCK_ENABLE(a) (a) 11970 #define arguments_ODY_DSSX_MCT_GLOBAL_CLOCK_ENABLE(a) (a), -1, -1, -1 11971 11972 /** 11973 * Register (RSL) dss#_mct_hide_crypto_status 11974 * 11975 * DSS MCT Hide Crypto Status Register 11976 * This register is used to hide crypto status. 11977 */ 11978 union ody_dssx_mct_hide_crypto_status { 11979 uint64_t u; 11980 struct ody_dssx_mct_hide_crypto_status_s { 11981 uint64_t hide_crypto_status : 1; 11982 uint64_t dis_sw_cmd : 1; 11983 uint64_t reserved_2_63 : 62; 11984 } s; 11985 /* struct ody_dssx_mct_hide_crypto_status_s cn; */ 11986 }; 11987 typedef union ody_dssx_mct_hide_crypto_status ody_dssx_mct_hide_crypto_status_t; 11988 11989 static inline uint64_t ODY_DSSX_MCT_HIDE_CRYPTO_STATUS(uint64_t a) __attribute__ ((pure, always_inline)); 11990 static inline uint64_t ODY_DSSX_MCT_HIDE_CRYPTO_STATUS(uint64_t a) 11991 { 11992 if (a <= 19) 11993 return 0x87e1b0010128ll + 0x1000000ll * ((a) & 0x1f); 11994 __ody_csr_fatal("DSSX_MCT_HIDE_CRYPTO_STATUS", 1, a, 0, 0, 0, 0, 0); 11995 } 11996 11997 #define typedef_ODY_DSSX_MCT_HIDE_CRYPTO_STATUS(a) ody_dssx_mct_hide_crypto_status_t 11998 #define bustype_ODY_DSSX_MCT_HIDE_CRYPTO_STATUS(a) CSR_TYPE_RSL 11999 #define basename_ODY_DSSX_MCT_HIDE_CRYPTO_STATUS(a) "DSSX_MCT_HIDE_CRYPTO_STATUS" 12000 #define device_bar_ODY_DSSX_MCT_HIDE_CRYPTO_STATUS(a) 0x0 /* PF_BAR0 */ 12001 #define busnum_ODY_DSSX_MCT_HIDE_CRYPTO_STATUS(a) (a) 12002 #define arguments_ODY_DSSX_MCT_HIDE_CRYPTO_STATUS(a) (a), -1, -1, -1 12003 12004 /** 12005 * Register (RSL) dss#_mct_int_ena_w1c 12006 * 12007 * DSS Interrupt Enable Clear Registers 12008 * This register clears interrupt enable bits. 12009 */ 12010 union ody_dssx_mct_int_ena_w1c { 12011 uint64_t u; 12012 struct ody_dssx_mct_int_ena_w1c_s { 12013 uint64_t mct_not_config_rd_addr_intr : 1; 12014 uint64_t mct_not_config_wr_addr_intr : 1; 12015 uint64_t mct_rd_multi_hits_intr : 1; 12016 uint64_t mct_rd_fifo_ovrflw_intr : 1; 12017 uint64_t mct_wr_multi_hits_intr : 1; 12018 uint64_t mct_wr_data_fifo_ovrflw_intr : 1; 12019 uint64_t reserved_6_63 : 58; 12020 } s; 12021 /* struct ody_dssx_mct_int_ena_w1c_s cn; */ 12022 }; 12023 typedef union ody_dssx_mct_int_ena_w1c ody_dssx_mct_int_ena_w1c_t; 12024 12025 static inline uint64_t ODY_DSSX_MCT_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 12026 static inline uint64_t ODY_DSSX_MCT_INT_ENA_W1C(uint64_t a) 12027 { 12028 if (a <= 19) 12029 return 0x87e1b0018010ll + 0x1000000ll * ((a) & 0x1f); 12030 __ody_csr_fatal("DSSX_MCT_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0); 12031 } 12032 12033 #define typedef_ODY_DSSX_MCT_INT_ENA_W1C(a) ody_dssx_mct_int_ena_w1c_t 12034 #define bustype_ODY_DSSX_MCT_INT_ENA_W1C(a) CSR_TYPE_RSL 12035 #define basename_ODY_DSSX_MCT_INT_ENA_W1C(a) "DSSX_MCT_INT_ENA_W1C" 12036 #define device_bar_ODY_DSSX_MCT_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */ 12037 #define busnum_ODY_DSSX_MCT_INT_ENA_W1C(a) (a) 12038 #define arguments_ODY_DSSX_MCT_INT_ENA_W1C(a) (a), -1, -1, -1 12039 12040 /** 12041 * Register (RSL) dss#_mct_int_ena_w1s 12042 * 12043 * DSS Interrupt Enable Set Registers 12044 * This register sets interrupt enable bits. 12045 */ 12046 union ody_dssx_mct_int_ena_w1s { 12047 uint64_t u; 12048 struct ody_dssx_mct_int_ena_w1s_s { 12049 uint64_t mct_not_config_rd_addr_intr : 1; 12050 uint64_t mct_not_config_wr_addr_intr : 1; 12051 uint64_t mct_rd_multi_hits_intr : 1; 12052 uint64_t mct_rd_fifo_ovrflw_intr : 1; 12053 uint64_t mct_wr_multi_hits_intr : 1; 12054 uint64_t mct_wr_data_fifo_ovrflw_intr : 1; 12055 uint64_t reserved_6_63 : 58; 12056 } s; 12057 /* struct ody_dssx_mct_int_ena_w1s_s cn; */ 12058 }; 12059 typedef union ody_dssx_mct_int_ena_w1s ody_dssx_mct_int_ena_w1s_t; 12060 12061 static inline uint64_t ODY_DSSX_MCT_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 12062 static inline uint64_t ODY_DSSX_MCT_INT_ENA_W1S(uint64_t a) 12063 { 12064 if (a <= 19) 12065 return 0x87e1b0018018ll + 0x1000000ll * ((a) & 0x1f); 12066 __ody_csr_fatal("DSSX_MCT_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0); 12067 } 12068 12069 #define typedef_ODY_DSSX_MCT_INT_ENA_W1S(a) ody_dssx_mct_int_ena_w1s_t 12070 #define bustype_ODY_DSSX_MCT_INT_ENA_W1S(a) CSR_TYPE_RSL 12071 #define basename_ODY_DSSX_MCT_INT_ENA_W1S(a) "DSSX_MCT_INT_ENA_W1S" 12072 #define device_bar_ODY_DSSX_MCT_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */ 12073 #define busnum_ODY_DSSX_MCT_INT_ENA_W1S(a) (a) 12074 #define arguments_ODY_DSSX_MCT_INT_ENA_W1S(a) (a), -1, -1, -1 12075 12076 /** 12077 * Register (RSL) dss#_mct_int_w1c 12078 * 12079 * DSS Interrupt Register 12080 * This register is for DSS-based interrupts. 12081 */ 12082 union ody_dssx_mct_int_w1c { 12083 uint64_t u; 12084 struct ody_dssx_mct_int_w1c_s { 12085 uint64_t mct_not_config_rd_addr_intr : 1; 12086 uint64_t mct_not_config_wr_addr_intr : 1; 12087 uint64_t mct_rd_multi_hits_intr : 1; 12088 uint64_t mct_rd_fifo_ovrflw_intr : 1; 12089 uint64_t mct_wr_multi_hits_intr : 1; 12090 uint64_t mct_wr_data_fifo_ovrflw_intr : 1; 12091 uint64_t reserved_6_63 : 58; 12092 } s; 12093 /* struct ody_dssx_mct_int_w1c_s cn; */ 12094 }; 12095 typedef union ody_dssx_mct_int_w1c ody_dssx_mct_int_w1c_t; 12096 12097 static inline uint64_t ODY_DSSX_MCT_INT_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 12098 static inline uint64_t ODY_DSSX_MCT_INT_W1C(uint64_t a) 12099 { 12100 if (a <= 19) 12101 return 0x87e1b0018000ll + 0x1000000ll * ((a) & 0x1f); 12102 __ody_csr_fatal("DSSX_MCT_INT_W1C", 1, a, 0, 0, 0, 0, 0); 12103 } 12104 12105 #define typedef_ODY_DSSX_MCT_INT_W1C(a) ody_dssx_mct_int_w1c_t 12106 #define bustype_ODY_DSSX_MCT_INT_W1C(a) CSR_TYPE_RSL 12107 #define basename_ODY_DSSX_MCT_INT_W1C(a) "DSSX_MCT_INT_W1C" 12108 #define device_bar_ODY_DSSX_MCT_INT_W1C(a) 0x0 /* PF_BAR0 */ 12109 #define busnum_ODY_DSSX_MCT_INT_W1C(a) (a) 12110 #define arguments_ODY_DSSX_MCT_INT_W1C(a) (a), -1, -1, -1 12111 12112 /** 12113 * Register (RSL) dss#_mct_int_w1s 12114 * 12115 * DSS Interrupt Set Registers 12116 * This register sets interrupt bits. 12117 */ 12118 union ody_dssx_mct_int_w1s { 12119 uint64_t u; 12120 struct ody_dssx_mct_int_w1s_s { 12121 uint64_t mct_not_config_rd_addr_intr : 1; 12122 uint64_t mct_not_config_wr_addr_intr : 1; 12123 uint64_t mct_rd_multi_hits_intr : 1; 12124 uint64_t mct_rd_fifo_ovrflw_intr : 1; 12125 uint64_t mct_wr_multi_hits_intr : 1; 12126 uint64_t mct_wr_data_fifo_ovrflw_intr : 1; 12127 uint64_t reserved_6_63 : 58; 12128 } s; 12129 /* struct ody_dssx_mct_int_w1s_s cn; */ 12130 }; 12131 typedef union ody_dssx_mct_int_w1s ody_dssx_mct_int_w1s_t; 12132 12133 static inline uint64_t ODY_DSSX_MCT_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 12134 static inline uint64_t ODY_DSSX_MCT_INT_W1S(uint64_t a) 12135 { 12136 if (a <= 19) 12137 return 0x87e1b0018008ll + 0x1000000ll * ((a) & 0x1f); 12138 __ody_csr_fatal("DSSX_MCT_INT_W1S", 1, a, 0, 0, 0, 0, 0); 12139 } 12140 12141 #define typedef_ODY_DSSX_MCT_INT_W1S(a) ody_dssx_mct_int_w1s_t 12142 #define bustype_ODY_DSSX_MCT_INT_W1S(a) CSR_TYPE_RSL 12143 #define basename_ODY_DSSX_MCT_INT_W1S(a) "DSSX_MCT_INT_W1S" 12144 #define device_bar_ODY_DSSX_MCT_INT_W1S(a) 0x0 /* PF_BAR0 */ 12145 #define busnum_ODY_DSSX_MCT_INT_W1S(a) (a) 12146 #define arguments_ODY_DSSX_MCT_INT_W1S(a) (a), -1, -1, -1 12147 12148 /** 12149 * Register (RSL) dss#_mct_next_key_127_64# 12150 * 12151 * DSS MCT NEXT KEY Register 12152 * Holds bits[127:64] of the next key used for encryption of selected index. 12153 */ 12154 union ody_dssx_mct_next_key_127_64x { 12155 uint64_t u; 12156 struct ody_dssx_mct_next_key_127_64x_s { 12157 uint64_t next_key_127_64 : 64; 12158 } s; 12159 /* struct ody_dssx_mct_next_key_127_64x_s cn; */ 12160 }; 12161 typedef union ody_dssx_mct_next_key_127_64x ody_dssx_mct_next_key_127_64x_t; 12162 12163 static inline uint64_t ODY_DSSX_MCT_NEXT_KEY_127_64X(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12164 static inline uint64_t ODY_DSSX_MCT_NEXT_KEY_127_64X(uint64_t a, uint64_t b) 12165 { 12166 if ((a <= 19) && (b <= 3)) 12167 return 0x87e1b0010060ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 12168 __ody_csr_fatal("DSSX_MCT_NEXT_KEY_127_64X", 2, a, b, 0, 0, 0, 0); 12169 } 12170 12171 #define typedef_ODY_DSSX_MCT_NEXT_KEY_127_64X(a, b) ody_dssx_mct_next_key_127_64x_t 12172 #define bustype_ODY_DSSX_MCT_NEXT_KEY_127_64X(a, b) CSR_TYPE_RSL 12173 #define basename_ODY_DSSX_MCT_NEXT_KEY_127_64X(a, b) "DSSX_MCT_NEXT_KEY_127_64X" 12174 #define device_bar_ODY_DSSX_MCT_NEXT_KEY_127_64X(a, b) 0x0 /* PF_BAR0 */ 12175 #define busnum_ODY_DSSX_MCT_NEXT_KEY_127_64X(a, b) (a) 12176 #define arguments_ODY_DSSX_MCT_NEXT_KEY_127_64X(a, b) (a), (b), -1, -1 12177 12178 /** 12179 * Register (RSL) dss#_mct_next_key_63_0# 12180 * 12181 * DSS MCT NEXT ENCRYPTION KEY Register 12182 * Holds bits[63:0] of the next key used for encryption of selected index. 12183 */ 12184 union ody_dssx_mct_next_key_63_0x { 12185 uint64_t u; 12186 struct ody_dssx_mct_next_key_63_0x_s { 12187 uint64_t next_key_63_0 : 64; 12188 } s; 12189 /* struct ody_dssx_mct_next_key_63_0x_s cn; */ 12190 }; 12191 typedef union ody_dssx_mct_next_key_63_0x ody_dssx_mct_next_key_63_0x_t; 12192 12193 static inline uint64_t ODY_DSSX_MCT_NEXT_KEY_63_0X(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12194 static inline uint64_t ODY_DSSX_MCT_NEXT_KEY_63_0X(uint64_t a, uint64_t b) 12195 { 12196 if ((a <= 19) && (b <= 3)) 12197 return 0x87e1b0010040ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 12198 __ody_csr_fatal("DSSX_MCT_NEXT_KEY_63_0X", 2, a, b, 0, 0, 0, 0); 12199 } 12200 12201 #define typedef_ODY_DSSX_MCT_NEXT_KEY_63_0X(a, b) ody_dssx_mct_next_key_63_0x_t 12202 #define bustype_ODY_DSSX_MCT_NEXT_KEY_63_0X(a, b) CSR_TYPE_RSL 12203 #define basename_ODY_DSSX_MCT_NEXT_KEY_63_0X(a, b) "DSSX_MCT_NEXT_KEY_63_0X" 12204 #define device_bar_ODY_DSSX_MCT_NEXT_KEY_63_0X(a, b) 0x0 /* PF_BAR0 */ 12205 #define busnum_ODY_DSSX_MCT_NEXT_KEY_63_0X(a, b) (a) 12206 #define arguments_ODY_DSSX_MCT_NEXT_KEY_63_0X(a, b) (a), (b), -1, -1 12207 12208 /** 12209 * Register (RSL) dss#_mct_next_key_ready# 12210 * 12211 * DSS MCT Next Key Is Ready Register 12212 * SW needs to write DSS_MCT_NEXT_KEY_63_0 and DSS_MCT_NEXT_KEY_127_64 periodically in 12213 * order to keep changing DRAM encryption key. 12214 * The encryption key width in AES-128 is 128 bits, which is divided into two 12215 * registers. To ensure that MCT takes the two halves synchronously, SW need to write 12216 * this field to one to indicate MCT that DSS_MCT_NEXT_KEY_* registers has a valid new 12217 * key. 12218 */ 12219 union ody_dssx_mct_next_key_readyx { 12220 uint64_t u; 12221 struct ody_dssx_mct_next_key_readyx_s { 12222 uint64_t next_key_is_ready : 1; 12223 uint64_t reserved_1_63 : 63; 12224 } s; 12225 /* struct ody_dssx_mct_next_key_readyx_s cn; */ 12226 }; 12227 typedef union ody_dssx_mct_next_key_readyx ody_dssx_mct_next_key_readyx_t; 12228 12229 static inline uint64_t ODY_DSSX_MCT_NEXT_KEY_READYX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12230 static inline uint64_t ODY_DSSX_MCT_NEXT_KEY_READYX(uint64_t a, uint64_t b) 12231 { 12232 if ((a <= 19) && (b <= 3)) 12233 return 0x87e1b0010020ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 12234 __ody_csr_fatal("DSSX_MCT_NEXT_KEY_READYX", 2, a, b, 0, 0, 0, 0); 12235 } 12236 12237 #define typedef_ODY_DSSX_MCT_NEXT_KEY_READYX(a, b) ody_dssx_mct_next_key_readyx_t 12238 #define bustype_ODY_DSSX_MCT_NEXT_KEY_READYX(a, b) CSR_TYPE_RSL 12239 #define basename_ODY_DSSX_MCT_NEXT_KEY_READYX(a, b) "DSSX_MCT_NEXT_KEY_READYX" 12240 #define device_bar_ODY_DSSX_MCT_NEXT_KEY_READYX(a, b) 0x0 /* PF_BAR0 */ 12241 #define busnum_ODY_DSSX_MCT_NEXT_KEY_READYX(a, b) (a) 12242 #define arguments_ODY_DSSX_MCT_NEXT_KEY_READYX(a, b) (a), (b), -1, -1 12243 12244 /** 12245 * Register (RSL) dss#_mct_previous_key_127_64# 12246 * 12247 * DSS MCT PREVIOUS KEY Register 12248 * Holds bits[127:64] of the previous key used for encryption of selected index. 12249 */ 12250 union ody_dssx_mct_previous_key_127_64x { 12251 uint64_t u; 12252 struct ody_dssx_mct_previous_key_127_64x_s { 12253 uint64_t previous_key_127_64 : 64; 12254 } s; 12255 /* struct ody_dssx_mct_previous_key_127_64x_s cn; */ 12256 }; 12257 typedef union ody_dssx_mct_previous_key_127_64x ody_dssx_mct_previous_key_127_64x_t; 12258 12259 static inline uint64_t ODY_DSSX_MCT_PREVIOUS_KEY_127_64X(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12260 static inline uint64_t ODY_DSSX_MCT_PREVIOUS_KEY_127_64X(uint64_t a, uint64_t b) 12261 { 12262 if ((a <= 19) && (b <= 3)) 12263 return 0x87e1b0010100ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 12264 __ody_csr_fatal("DSSX_MCT_PREVIOUS_KEY_127_64X", 2, a, b, 0, 0, 0, 0); 12265 } 12266 12267 #define typedef_ODY_DSSX_MCT_PREVIOUS_KEY_127_64X(a, b) ody_dssx_mct_previous_key_127_64x_t 12268 #define bustype_ODY_DSSX_MCT_PREVIOUS_KEY_127_64X(a, b) CSR_TYPE_RSL 12269 #define basename_ODY_DSSX_MCT_PREVIOUS_KEY_127_64X(a, b) "DSSX_MCT_PREVIOUS_KEY_127_64X" 12270 #define device_bar_ODY_DSSX_MCT_PREVIOUS_KEY_127_64X(a, b) 0x0 /* PF_BAR0 */ 12271 #define busnum_ODY_DSSX_MCT_PREVIOUS_KEY_127_64X(a, b) (a) 12272 #define arguments_ODY_DSSX_MCT_PREVIOUS_KEY_127_64X(a, b) (a), (b), -1, -1 12273 12274 /** 12275 * Register (RSL) dss#_mct_previous_key_63_0# 12276 * 12277 * DSS MCT PREVIOUS ENCRYPTION KEY Register 12278 * Holds bits[63:0] of the previous key used for encryption of selected index. 12279 */ 12280 union ody_dssx_mct_previous_key_63_0x { 12281 uint64_t u; 12282 struct ody_dssx_mct_previous_key_63_0x_s { 12283 uint64_t previous_key_63_0 : 64; 12284 } s; 12285 /* struct ody_dssx_mct_previous_key_63_0x_s cn; */ 12286 }; 12287 typedef union ody_dssx_mct_previous_key_63_0x ody_dssx_mct_previous_key_63_0x_t; 12288 12289 static inline uint64_t ODY_DSSX_MCT_PREVIOUS_KEY_63_0X(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12290 static inline uint64_t ODY_DSSX_MCT_PREVIOUS_KEY_63_0X(uint64_t a, uint64_t b) 12291 { 12292 if ((a <= 19) && (b <= 3)) 12293 return 0x87e1b00100e0ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x3); 12294 __ody_csr_fatal("DSSX_MCT_PREVIOUS_KEY_63_0X", 2, a, b, 0, 0, 0, 0); 12295 } 12296 12297 #define typedef_ODY_DSSX_MCT_PREVIOUS_KEY_63_0X(a, b) ody_dssx_mct_previous_key_63_0x_t 12298 #define bustype_ODY_DSSX_MCT_PREVIOUS_KEY_63_0X(a, b) CSR_TYPE_RSL 12299 #define basename_ODY_DSSX_MCT_PREVIOUS_KEY_63_0X(a, b) "DSSX_MCT_PREVIOUS_KEY_63_0X" 12300 #define device_bar_ODY_DSSX_MCT_PREVIOUS_KEY_63_0X(a, b) 0x0 /* PF_BAR0 */ 12301 #define busnum_ODY_DSSX_MCT_PREVIOUS_KEY_63_0X(a, b) (a) 12302 #define arguments_ODY_DSSX_MCT_PREVIOUS_KEY_63_0X(a, b) (a), (b), -1, -1 12303 12304 /** 12305 * Register (RSL) dss#_mct_reset_n 12306 * 12307 * DSS MCT Clock Domain Reset Register 12308 * MCT clock domain software reset - active low. 12309 */ 12310 union ody_dssx_mct_reset_n { 12311 uint64_t u; 12312 struct ody_dssx_mct_reset_n_s { 12313 uint64_t s_mct_reset_n : 1; 12314 uint64_t reserved_1_63 : 63; 12315 } s; 12316 /* struct ody_dssx_mct_reset_n_s cn; */ 12317 }; 12318 typedef union ody_dssx_mct_reset_n ody_dssx_mct_reset_n_t; 12319 12320 static inline uint64_t ODY_DSSX_MCT_RESET_N(uint64_t a) __attribute__ ((pure, always_inline)); 12321 static inline uint64_t ODY_DSSX_MCT_RESET_N(uint64_t a) 12322 { 12323 if (a <= 19) 12324 return 0x87e1b0000010ll + 0x1000000ll * ((a) & 0x1f); 12325 __ody_csr_fatal("DSSX_MCT_RESET_N", 1, a, 0, 0, 0, 0, 0); 12326 } 12327 12328 #define typedef_ODY_DSSX_MCT_RESET_N(a) ody_dssx_mct_reset_n_t 12329 #define bustype_ODY_DSSX_MCT_RESET_N(a) CSR_TYPE_RSL 12330 #define basename_ODY_DSSX_MCT_RESET_N(a) "DSSX_MCT_RESET_N" 12331 #define device_bar_ODY_DSSX_MCT_RESET_N(a) 0x0 /* PF_BAR0 */ 12332 #define busnum_ODY_DSSX_MCT_RESET_N(a) (a) 12333 #define arguments_ODY_DSSX_MCT_RESET_N(a) (a), -1, -1, -1 12334 12335 /** 12336 * Register (RSL) dss#_mct_scrub_pointer 12337 * 12338 * DSS MCT Scrub Pointer Register 12339 * This register holds last accessed address by the scrub. 12340 */ 12341 union ody_dssx_mct_scrub_pointer { 12342 uint64_t u; 12343 struct ody_dssx_mct_scrub_pointer_s { 12344 uint64_t scrub_pointer : 52; 12345 uint64_t reserved_52_63 : 12; 12346 } s; 12347 /* struct ody_dssx_mct_scrub_pointer_s cn; */ 12348 }; 12349 typedef union ody_dssx_mct_scrub_pointer ody_dssx_mct_scrub_pointer_t; 12350 12351 static inline uint64_t ODY_DSSX_MCT_SCRUB_POINTER(uint64_t a) __attribute__ ((pure, always_inline)); 12352 static inline uint64_t ODY_DSSX_MCT_SCRUB_POINTER(uint64_t a) 12353 { 12354 if (a <= 19) 12355 return 0x87e1b0010120ll + 0x1000000ll * ((a) & 0x1f); 12356 __ody_csr_fatal("DSSX_MCT_SCRUB_POINTER", 1, a, 0, 0, 0, 0, 0); 12357 } 12358 12359 #define typedef_ODY_DSSX_MCT_SCRUB_POINTER(a) ody_dssx_mct_scrub_pointer_t 12360 #define bustype_ODY_DSSX_MCT_SCRUB_POINTER(a) CSR_TYPE_RSL 12361 #define basename_ODY_DSSX_MCT_SCRUB_POINTER(a) "DSSX_MCT_SCRUB_POINTER" 12362 #define device_bar_ODY_DSSX_MCT_SCRUB_POINTER(a) 0x0 /* PF_BAR0 */ 12363 #define busnum_ODY_DSSX_MCT_SCRUB_POINTER(a) (a) 12364 #define arguments_ODY_DSSX_MCT_SCRUB_POINTER(a) (a), -1, -1, -1 12365 12366 /** 12367 * Register (RSL) dss#_mct_tmg_param_mc_side 12368 * 12369 * DSS MCT Timing Parameters - MC Side Register 12370 * Timing parameters configured in the memory controller. 12371 * This register should be configured only when (DSS_MCT()_ENABLE[S_MCT_EN] = 0). 12372 */ 12373 union ody_dssx_mct_tmg_param_mc_side { 12374 uint64_t u; 12375 struct ody_dssx_mct_tmg_param_mc_side_s { 12376 uint64_t tphy_wrdata_mc_side : 6; 12377 uint64_t tphy_wrlat_mc_side : 6; 12378 uint64_t tphy_wrcslat_mc_side : 6; 12379 uint64_t t_phy_rddata_en_mc_side : 6; 12380 uint64_t tphy_rdcslat_mc_side : 6; 12381 uint64_t reserved_30_63 : 34; 12382 } s; 12383 /* struct ody_dssx_mct_tmg_param_mc_side_s cn; */ 12384 }; 12385 typedef union ody_dssx_mct_tmg_param_mc_side ody_dssx_mct_tmg_param_mc_side_t; 12386 12387 static inline uint64_t ODY_DSSX_MCT_TMG_PARAM_MC_SIDE(uint64_t a) __attribute__ ((pure, always_inline)); 12388 static inline uint64_t ODY_DSSX_MCT_TMG_PARAM_MC_SIDE(uint64_t a) 12389 { 12390 if (a <= 19) 12391 return 0x87e1b00103b0ll + 0x1000000ll * ((a) & 0x1f); 12392 __ody_csr_fatal("DSSX_MCT_TMG_PARAM_MC_SIDE", 1, a, 0, 0, 0, 0, 0); 12393 } 12394 12395 #define typedef_ODY_DSSX_MCT_TMG_PARAM_MC_SIDE(a) ody_dssx_mct_tmg_param_mc_side_t 12396 #define bustype_ODY_DSSX_MCT_TMG_PARAM_MC_SIDE(a) CSR_TYPE_RSL 12397 #define basename_ODY_DSSX_MCT_TMG_PARAM_MC_SIDE(a) "DSSX_MCT_TMG_PARAM_MC_SIDE" 12398 #define device_bar_ODY_DSSX_MCT_TMG_PARAM_MC_SIDE(a) 0x0 /* PF_BAR0 */ 12399 #define busnum_ODY_DSSX_MCT_TMG_PARAM_MC_SIDE(a) (a) 12400 #define arguments_ODY_DSSX_MCT_TMG_PARAM_MC_SIDE(a) (a), -1, -1, -1 12401 12402 /** 12403 * Register (RSL) dss#_mct_tmg_param_phy_side 12404 * 12405 * DSS MCT Timing Parameters - PHY Side Register 12406 * Timing parameters towards PHY on DFI interface. 12407 * This register should be configured only when (DSS_MCT()_ENABLE[S_MCT_EN] = 0). 12408 */ 12409 union ody_dssx_mct_tmg_param_phy_side { 12410 uint64_t u; 12411 struct ody_dssx_mct_tmg_param_phy_side_s { 12412 uint64_t tphy_wrdata_phy_side : 6; 12413 uint64_t tphy_wrlat_phy_side : 6; 12414 uint64_t tphy_wrcslat_phy_side : 6; 12415 uint64_t t_phy_rddata_en_phy_side : 6; 12416 uint64_t tphy_rdcslat_phy_side : 6; 12417 uint64_t reserved_30_63 : 34; 12418 } s; 12419 /* struct ody_dssx_mct_tmg_param_phy_side_s cn; */ 12420 }; 12421 typedef union ody_dssx_mct_tmg_param_phy_side ody_dssx_mct_tmg_param_phy_side_t; 12422 12423 static inline uint64_t ODY_DSSX_MCT_TMG_PARAM_PHY_SIDE(uint64_t a) __attribute__ ((pure, always_inline)); 12424 static inline uint64_t ODY_DSSX_MCT_TMG_PARAM_PHY_SIDE(uint64_t a) 12425 { 12426 if (a <= 19) 12427 return 0x87e1b00103b8ll + 0x1000000ll * ((a) & 0x1f); 12428 __ody_csr_fatal("DSSX_MCT_TMG_PARAM_PHY_SIDE", 1, a, 0, 0, 0, 0, 0); 12429 } 12430 12431 #define typedef_ODY_DSSX_MCT_TMG_PARAM_PHY_SIDE(a) ody_dssx_mct_tmg_param_phy_side_t 12432 #define bustype_ODY_DSSX_MCT_TMG_PARAM_PHY_SIDE(a) CSR_TYPE_RSL 12433 #define basename_ODY_DSSX_MCT_TMG_PARAM_PHY_SIDE(a) "DSSX_MCT_TMG_PARAM_PHY_SIDE" 12434 #define device_bar_ODY_DSSX_MCT_TMG_PARAM_PHY_SIDE(a) 0x0 /* PF_BAR0 */ 12435 #define busnum_ODY_DSSX_MCT_TMG_PARAM_PHY_SIDE(a) (a) 12436 #define arguments_ODY_DSSX_MCT_TMG_PARAM_PHY_SIDE(a) (a), -1, -1, -1 12437 12438 /** 12439 * Register (RSL) dss#_mct_win_addr_hi# 12440 * 12441 * DSS MCT WIN ADDR HI Register 12442 * This register defines the crypto high address windows. 12443 * This register should be configured only when (DSS_MCT()_ENABLE[S_MCT_EN] = 0). 12444 */ 12445 union ody_dssx_mct_win_addr_hix { 12446 uint64_t u; 12447 struct ody_dssx_mct_win_addr_hix_s { 12448 uint64_t win_addr_hi : 52; 12449 uint64_t reserved_52_63 : 12; 12450 } s; 12451 /* struct ody_dssx_mct_win_addr_hix_s cn; */ 12452 }; 12453 typedef union ody_dssx_mct_win_addr_hix ody_dssx_mct_win_addr_hix_t; 12454 12455 static inline uint64_t ODY_DSSX_MCT_WIN_ADDR_HIX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12456 static inline uint64_t ODY_DSSX_MCT_WIN_ADDR_HIX(uint64_t a, uint64_t b) 12457 { 12458 if ((a <= 19) && (b <= 15)) 12459 return 0x87e1b0010330ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0xf); 12460 __ody_csr_fatal("DSSX_MCT_WIN_ADDR_HIX", 2, a, b, 0, 0, 0, 0); 12461 } 12462 12463 #define typedef_ODY_DSSX_MCT_WIN_ADDR_HIX(a, b) ody_dssx_mct_win_addr_hix_t 12464 #define bustype_ODY_DSSX_MCT_WIN_ADDR_HIX(a, b) CSR_TYPE_RSL 12465 #define basename_ODY_DSSX_MCT_WIN_ADDR_HIX(a, b) "DSSX_MCT_WIN_ADDR_HIX" 12466 #define device_bar_ODY_DSSX_MCT_WIN_ADDR_HIX(a, b) 0x0 /* PF_BAR0 */ 12467 #define busnum_ODY_DSSX_MCT_WIN_ADDR_HIX(a, b) (a) 12468 #define arguments_ODY_DSSX_MCT_WIN_ADDR_HIX(a, b) (a), (b), -1, -1 12469 12470 /** 12471 * Register (RSL) dss#_mct_win_addr_lo# 12472 * 12473 * DSS MCT WIN ADDR LO Register 12474 * This register defines the crypto low address windows. 12475 * This register should be configured only when (DSS_MCT()_ENABLE[S_MCT_EN] = 0). 12476 */ 12477 union ody_dssx_mct_win_addr_lox { 12478 uint64_t u; 12479 struct ody_dssx_mct_win_addr_lox_s { 12480 uint64_t win_addr_lo : 52; 12481 uint64_t reserved_52_63 : 12; 12482 } s; 12483 /* struct ody_dssx_mct_win_addr_lox_s cn; */ 12484 }; 12485 typedef union ody_dssx_mct_win_addr_lox ody_dssx_mct_win_addr_lox_t; 12486 12487 static inline uint64_t ODY_DSSX_MCT_WIN_ADDR_LOX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12488 static inline uint64_t ODY_DSSX_MCT_WIN_ADDR_LOX(uint64_t a, uint64_t b) 12489 { 12490 if ((a <= 19) && (b <= 15)) 12491 return 0x87e1b00102b0ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0xf); 12492 __ody_csr_fatal("DSSX_MCT_WIN_ADDR_LOX", 2, a, b, 0, 0, 0, 0); 12493 } 12494 12495 #define typedef_ODY_DSSX_MCT_WIN_ADDR_LOX(a, b) ody_dssx_mct_win_addr_lox_t 12496 #define bustype_ODY_DSSX_MCT_WIN_ADDR_LOX(a, b) CSR_TYPE_RSL 12497 #define basename_ODY_DSSX_MCT_WIN_ADDR_LOX(a, b) "DSSX_MCT_WIN_ADDR_LOX" 12498 #define device_bar_ODY_DSSX_MCT_WIN_ADDR_LOX(a, b) 0x0 /* PF_BAR0 */ 12499 #define busnum_ODY_DSSX_MCT_WIN_ADDR_LOX(a, b) (a) 12500 #define arguments_ODY_DSSX_MCT_WIN_ADDR_LOX(a, b) (a), (b), -1, -1 12501 12502 /** 12503 * Register (RSL) dss#_mct_win_ctrl# 12504 * 12505 * DSS MCT WINDOW CTRL Register 12506 * This register defines the crypto address windows attributes. 12507 * This register should be configured only when (DSS_MCT()_ENABLE[S_MCT_EN] = 0). 12508 */ 12509 union ody_dssx_mct_win_ctrlx { 12510 uint64_t u; 12511 struct ody_dssx_mct_win_ctrlx_s { 12512 uint64_t win_en : 1; 12513 uint64_t win_encryption_en : 1; 12514 uint64_t key_index : 2; 12515 uint64_t reserved_4_63 : 60; 12516 } s; 12517 /* struct ody_dssx_mct_win_ctrlx_s cn; */ 12518 }; 12519 typedef union ody_dssx_mct_win_ctrlx ody_dssx_mct_win_ctrlx_t; 12520 12521 static inline uint64_t ODY_DSSX_MCT_WIN_CTRLX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12522 static inline uint64_t ODY_DSSX_MCT_WIN_CTRLX(uint64_t a, uint64_t b) 12523 { 12524 if ((a <= 19) && (b <= 15)) 12525 return 0x87e1b0010230ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0xf); 12526 __ody_csr_fatal("DSSX_MCT_WIN_CTRLX", 2, a, b, 0, 0, 0, 0); 12527 } 12528 12529 #define typedef_ODY_DSSX_MCT_WIN_CTRLX(a, b) ody_dssx_mct_win_ctrlx_t 12530 #define bustype_ODY_DSSX_MCT_WIN_CTRLX(a, b) CSR_TYPE_RSL 12531 #define basename_ODY_DSSX_MCT_WIN_CTRLX(a, b) "DSSX_MCT_WIN_CTRLX" 12532 #define device_bar_ODY_DSSX_MCT_WIN_CTRLX(a, b) 0x0 /* PF_BAR0 */ 12533 #define busnum_ODY_DSSX_MCT_WIN_CTRLX(a, b) (a) 12534 #define arguments_ODY_DSSX_MCT_WIN_CTRLX(a, b) (a), (b), -1, -1 12535 12536 /** 12537 * Register (RSL) dss#_mpam_cap_mon_event 12538 * 12539 * DSS TOP MPAM Capture Monitors Event Register 12540 * SoftWare trigger to capture memory controller MPAM monitors. 12541 */ 12542 union ody_dssx_mpam_cap_mon_event { 12543 uint64_t u; 12544 struct ody_dssx_mpam_cap_mon_event_s { 12545 uint64_t mc_mpam_cap_mon_event_0 : 1; 12546 uint64_t mc_mpam_cap_mon_event_1 : 1; 12547 uint64_t reserved_2_63 : 62; 12548 } s; 12549 /* struct ody_dssx_mpam_cap_mon_event_s cn; */ 12550 }; 12551 typedef union ody_dssx_mpam_cap_mon_event ody_dssx_mpam_cap_mon_event_t; 12552 12553 static inline uint64_t ODY_DSSX_MPAM_CAP_MON_EVENT(uint64_t a) __attribute__ ((pure, always_inline)); 12554 static inline uint64_t ODY_DSSX_MPAM_CAP_MON_EVENT(uint64_t a) 12555 { 12556 if (a <= 19) 12557 return 0x87e1b0000110ll + 0x1000000ll * ((a) & 0x1f); 12558 __ody_csr_fatal("DSSX_MPAM_CAP_MON_EVENT", 1, a, 0, 0, 0, 0, 0); 12559 } 12560 12561 #define typedef_ODY_DSSX_MPAM_CAP_MON_EVENT(a) ody_dssx_mpam_cap_mon_event_t 12562 #define bustype_ODY_DSSX_MPAM_CAP_MON_EVENT(a) CSR_TYPE_RSL 12563 #define basename_ODY_DSSX_MPAM_CAP_MON_EVENT(a) "DSSX_MPAM_CAP_MON_EVENT" 12564 #define device_bar_ODY_DSSX_MPAM_CAP_MON_EVENT(a) 0x0 /* PF_BAR0 */ 12565 #define busnum_ODY_DSSX_MPAM_CAP_MON_EVENT(a) (a) 12566 #define arguments_ODY_DSSX_MPAM_CAP_MON_EVENT(a) (a), -1, -1, -1 12567 12568 /** 12569 * Register (RSL) dss#_msix_pba# 12570 * 12571 * DSS MSI-X Pending Bit Array Registers 12572 */ 12573 union ody_dssx_msix_pbax { 12574 uint64_t u; 12575 struct ody_dssx_msix_pbax_s { 12576 uint64_t pend : 64; 12577 } s; 12578 /* struct ody_dssx_msix_pbax_s cn; */ 12579 }; 12580 typedef union ody_dssx_msix_pbax ody_dssx_msix_pbax_t; 12581 12582 static inline uint64_t ODY_DSSX_MSIX_PBAX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12583 static inline uint64_t ODY_DSSX_MSIX_PBAX(uint64_t a, uint64_t b) 12584 { 12585 if ((a <= 19) && (b == 0)) 12586 return 0x87e1b0708000ll + 0x1000000ll * ((a) & 0x1f); 12587 __ody_csr_fatal("DSSX_MSIX_PBAX", 2, a, b, 0, 0, 0, 0); 12588 } 12589 12590 #define typedef_ODY_DSSX_MSIX_PBAX(a, b) ody_dssx_msix_pbax_t 12591 #define bustype_ODY_DSSX_MSIX_PBAX(a, b) CSR_TYPE_RSL 12592 #define basename_ODY_DSSX_MSIX_PBAX(a, b) "DSSX_MSIX_PBAX" 12593 #define device_bar_ODY_DSSX_MSIX_PBAX(a, b) 0x4 /* PF_BAR4 */ 12594 #define busnum_ODY_DSSX_MSIX_PBAX(a, b) (a) 12595 #define arguments_ODY_DSSX_MSIX_PBAX(a, b) (a), (b), -1, -1 12596 12597 /** 12598 * Register (RSL) dss#_msix_vec#_addr 12599 * 12600 * DSS MSI-X Vector-Table Address Register 12601 * This register is the MSI-X vector table, indexed by the DSS_INT_VEC_E enumeration. 12602 */ 12603 union ody_dssx_msix_vecx_addr { 12604 uint64_t u; 12605 struct ody_dssx_msix_vecx_addr_s { 12606 uint64_t secvec : 1; 12607 uint64_t reserved_1 : 1; 12608 uint64_t addr : 51; 12609 uint64_t reserved_53_63 : 11; 12610 } s; 12611 /* struct ody_dssx_msix_vecx_addr_s cn; */ 12612 }; 12613 typedef union ody_dssx_msix_vecx_addr ody_dssx_msix_vecx_addr_t; 12614 12615 static inline uint64_t ODY_DSSX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12616 static inline uint64_t ODY_DSSX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) 12617 { 12618 if ((a <= 19) && (b <= 4)) 12619 return 0x87e1b0700000ll + 0x1000000ll * ((a) & 0x1f) + 0x10ll * ((b) & 0x7); 12620 __ody_csr_fatal("DSSX_MSIX_VECX_ADDR", 2, a, b, 0, 0, 0, 0); 12621 } 12622 12623 #define typedef_ODY_DSSX_MSIX_VECX_ADDR(a, b) ody_dssx_msix_vecx_addr_t 12624 #define bustype_ODY_DSSX_MSIX_VECX_ADDR(a, b) CSR_TYPE_RSL 12625 #define basename_ODY_DSSX_MSIX_VECX_ADDR(a, b) "DSSX_MSIX_VECX_ADDR" 12626 #define device_bar_ODY_DSSX_MSIX_VECX_ADDR(a, b) 0x4 /* PF_BAR4 */ 12627 #define busnum_ODY_DSSX_MSIX_VECX_ADDR(a, b) (a) 12628 #define arguments_ODY_DSSX_MSIX_VECX_ADDR(a, b) (a), (b), -1, -1 12629 12630 /** 12631 * Register (RSL) dss#_msix_vec#_ctl 12632 * 12633 * DSS MSI-X Vector-Table Control and Data Register 12634 * This register is the MSI-X vector table, indexed by the DSS_INT_VEC_E enumeration. 12635 */ 12636 union ody_dssx_msix_vecx_ctl { 12637 uint64_t u; 12638 struct ody_dssx_msix_vecx_ctl_s { 12639 uint64_t data : 32; 12640 uint64_t mask : 1; 12641 uint64_t reserved_33_63 : 31; 12642 } s; 12643 /* struct ody_dssx_msix_vecx_ctl_s cn; */ 12644 }; 12645 typedef union ody_dssx_msix_vecx_ctl ody_dssx_msix_vecx_ctl_t; 12646 12647 static inline uint64_t ODY_DSSX_MSIX_VECX_CTL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12648 static inline uint64_t ODY_DSSX_MSIX_VECX_CTL(uint64_t a, uint64_t b) 12649 { 12650 if ((a <= 19) && (b <= 4)) 12651 return 0x87e1b0700008ll + 0x1000000ll * ((a) & 0x1f) + 0x10ll * ((b) & 0x7); 12652 __ody_csr_fatal("DSSX_MSIX_VECX_CTL", 2, a, b, 0, 0, 0, 0); 12653 } 12654 12655 #define typedef_ODY_DSSX_MSIX_VECX_CTL(a, b) ody_dssx_msix_vecx_ctl_t 12656 #define bustype_ODY_DSSX_MSIX_VECX_CTL(a, b) CSR_TYPE_RSL 12657 #define basename_ODY_DSSX_MSIX_VECX_CTL(a, b) "DSSX_MSIX_VECX_CTL" 12658 #define device_bar_ODY_DSSX_MSIX_VECX_CTL(a, b) 0x4 /* PF_BAR4 */ 12659 #define busnum_ODY_DSSX_MSIX_VECX_CTL(a, b) (a) 12660 #define arguments_ODY_DSSX_MSIX_VECX_CTL(a, b) (a), (b), -1, -1 12661 12662 /** 12663 * Register (RSL) dss#_nderr_addr 12664 * 12665 * DSS Non-Data Error Address Register 12666 * This register records the error address for non-data error interrupts triggered from 12667 * the REQ mesh [REQ_PERR]. The first [REQ_PERR] error will lock 12668 * the register until the logged error type is cleared. 12669 * See DSS_NDERR_INFO for error opcode and SRCID logging. 12670 */ 12671 union ody_dssx_nderr_addr { 12672 uint64_t u; 12673 struct ody_dssx_nderr_addr_s { 12674 uint64_t addr : 52; 12675 uint64_t nonsec : 1; 12676 uint64_t reserved_53_63 : 11; 12677 } s; 12678 /* struct ody_dssx_nderr_addr_s cn; */ 12679 }; 12680 typedef union ody_dssx_nderr_addr ody_dssx_nderr_addr_t; 12681 12682 static inline uint64_t ODY_DSSX_NDERR_ADDR(uint64_t a) __attribute__ ((pure, always_inline)); 12683 static inline uint64_t ODY_DSSX_NDERR_ADDR(uint64_t a) 12684 { 12685 if (a <= 19) 12686 return 0x87e1b0000090ll + 0x1000000ll * ((a) & 0x1f); 12687 __ody_csr_fatal("DSSX_NDERR_ADDR", 1, a, 0, 0, 0, 0, 0); 12688 } 12689 12690 #define typedef_ODY_DSSX_NDERR_ADDR(a) ody_dssx_nderr_addr_t 12691 #define bustype_ODY_DSSX_NDERR_ADDR(a) CSR_TYPE_RSL 12692 #define basename_ODY_DSSX_NDERR_ADDR(a) "DSSX_NDERR_ADDR" 12693 #define device_bar_ODY_DSSX_NDERR_ADDR(a) 0x0 /* PF_BAR0 */ 12694 #define busnum_ODY_DSSX_NDERR_ADDR(a) (a) 12695 #define arguments_ODY_DSSX_NDERR_ADDR(a) (a), -1, -1, -1 12696 12697 /** 12698 * Register (RSL) dss#_nderr_info 12699 * 12700 * DSS Non-Data Error Info Register 12701 * This register records error information for non-data parity errors 12702 * [REQ_PERR, DAT_PERR]. The first [REQ_PERR, DAT_PERR] error 12703 * will lock the register until the logged error type is cleared; 12704 * See DSS()_NDERR_ADDR for error address logging. 12705 */ 12706 union ody_dssx_nderr_info { 12707 uint64_t u; 12708 struct ody_dssx_nderr_info_s { 12709 uint64_t srcid : 11; 12710 uint64_t opcode : 7; 12711 uint64_t reserved_18_61 : 44; 12712 uint64_t dat_perr : 1; 12713 uint64_t req_perr : 1; 12714 } s; 12715 /* struct ody_dssx_nderr_info_s cn; */ 12716 }; 12717 typedef union ody_dssx_nderr_info ody_dssx_nderr_info_t; 12718 12719 static inline uint64_t ODY_DSSX_NDERR_INFO(uint64_t a) __attribute__ ((pure, always_inline)); 12720 static inline uint64_t ODY_DSSX_NDERR_INFO(uint64_t a) 12721 { 12722 if (a <= 19) 12723 return 0x87e1b0000088ll + 0x1000000ll * ((a) & 0x1f); 12724 __ody_csr_fatal("DSSX_NDERR_INFO", 1, a, 0, 0, 0, 0, 0); 12725 } 12726 12727 #define typedef_ODY_DSSX_NDERR_INFO(a) ody_dssx_nderr_info_t 12728 #define bustype_ODY_DSSX_NDERR_INFO(a) CSR_TYPE_RSL 12729 #define basename_ODY_DSSX_NDERR_INFO(a) "DSSX_NDERR_INFO" 12730 #define device_bar_ODY_DSSX_NDERR_INFO(a) 0x0 /* PF_BAR0 */ 12731 #define busnum_ODY_DSSX_NDERR_INFO(a) (a) 12732 #define arguments_ODY_DSSX_NDERR_INFO(a) (a), -1, -1, -1 12733 12734 /** 12735 * Register (RSL) dss#_perf_cnt_cfg# 12736 * 12737 * Performance Counters Configuration Register 12738 * This register configures the events that the counter will count. 12739 */ 12740 union ody_dssx_perf_cnt_cfgx { 12741 uint64_t u; 12742 struct ody_dssx_perf_cnt_cfgx_s { 12743 uint64_t hif_rd_or_wr : 1; 12744 uint64_t hif_wr : 1; 12745 uint64_t hif_rd : 1; 12746 uint64_t hif_rmw : 1; 12747 uint64_t hif_hi_pri_rd : 1; 12748 uint64_t read_bypass : 1; 12749 uint64_t act_bypass : 1; 12750 uint64_t dfi_wr_data_cycles : 1; 12751 uint64_t dfi_rd_data_cycles : 1; 12752 uint64_t hpr_xact_when_critical : 1; 12753 uint64_t lpr_xact_when_critical : 1; 12754 uint64_t wr_xact_when_critical : 1; 12755 uint64_t op_is_activate : 1; 12756 uint64_t op_is_rd_or_wr : 1; 12757 uint64_t op_is_rd_activate : 1; 12758 uint64_t op_is_rd : 1; 12759 uint64_t op_is_wr : 1; 12760 uint64_t op_is_mwr : 1; 12761 uint64_t op_is_precharge : 1; 12762 uint64_t precharge_for_rdwr : 1; 12763 uint64_t precharge_for_other : 1; 12764 uint64_t rdwr_transitions : 1; 12765 uint64_t write_combine : 1; 12766 uint64_t war_hazard : 1; 12767 uint64_t raw_hazard : 1; 12768 uint64_t waw_hazard : 1; 12769 uint64_t op_is_enter_selfref : 4; 12770 uint64_t op_is_enter_powerdown : 4; 12771 uint64_t op_is_enter_mpsm : 4; 12772 uint64_t op_is_refresh : 1; 12773 uint64_t op_is_crit_ref : 1; 12774 uint64_t op_is_spec_ref : 1; 12775 uint64_t op_is_load_mode : 1; 12776 uint64_t op_is_zqcl : 1; 12777 uint64_t op_is_zqcs : 1; 12778 uint64_t dfi_cycles : 1; 12779 uint64_t retry_fifo_full : 1; 12780 uint64_t bsm_alloc : 1; 12781 uint64_t bsm_starvation : 1; 12782 uint64_t visible_win_limit_reached_rd : 1; 12783 uint64_t visible_win_limit_reached_wr : 1; 12784 uint64_t op_is_dqsosc_mpc : 1; 12785 uint64_t op_is_dqsosc_mrr : 1; 12786 uint64_t op_is_tcr_mrr : 1; 12787 uint64_t op_is_zqstart : 1; 12788 uint64_t op_is_zqlatch : 1; 12789 uint64_t dfi_parity_poison : 1; 12790 uint64_t wr_crc_error : 1; 12791 uint64_t capar_error : 1; 12792 uint64_t rd_crc_error : 1; 12793 uint64_t rd_uc_ecc_error : 1; 12794 uint64_t dfi_cmd_is_retry : 1; 12795 uint64_t interrupt_en : 1; 12796 uint64_t wrap_value : 1; 12797 uint64_t cnt_en : 1; 12798 } s; 12799 /* struct ody_dssx_perf_cnt_cfgx_s cn; */ 12800 }; 12801 typedef union ody_dssx_perf_cnt_cfgx ody_dssx_perf_cnt_cfgx_t; 12802 12803 static inline uint64_t ODY_DSSX_PERF_CNT_CFGX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12804 static inline uint64_t ODY_DSSX_PERF_CNT_CFGX(uint64_t a, uint64_t b) 12805 { 12806 if ((a <= 19) && (b <= 7)) 12807 return 0x87e1b0020160ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 12808 __ody_csr_fatal("DSSX_PERF_CNT_CFGX", 2, a, b, 0, 0, 0, 0); 12809 } 12810 12811 #define typedef_ODY_DSSX_PERF_CNT_CFGX(a, b) ody_dssx_perf_cnt_cfgx_t 12812 #define bustype_ODY_DSSX_PERF_CNT_CFGX(a, b) CSR_TYPE_RSL 12813 #define basename_ODY_DSSX_PERF_CNT_CFGX(a, b) "DSSX_PERF_CNT_CFGX" 12814 #define device_bar_ODY_DSSX_PERF_CNT_CFGX(a, b) 0x0 /* PF_BAR0 */ 12815 #define busnum_ODY_DSSX_PERF_CNT_CFGX(a, b) (a) 12816 #define arguments_ODY_DSSX_PERF_CNT_CFGX(a, b) (a), (b), -1, -1 12817 12818 /** 12819 * Register (RSL) dss#_perf_cnt_current_tmr_val# 12820 * 12821 * Performance Current Timer Value Register 12822 * This register contains the current timer value of the counter when running in timer 12823 * mode. Software can use this value to see the progress (in clock cycles) that counter made 12824 * and may compare it with target timer value. 12825 */ 12826 union ody_dssx_perf_cnt_current_tmr_valx { 12827 uint64_t u; 12828 struct ody_dssx_perf_cnt_current_tmr_valx_s { 12829 uint64_t current_timer_value : 64; 12830 } s; 12831 /* struct ody_dssx_perf_cnt_current_tmr_valx_s cn; */ 12832 }; 12833 typedef union ody_dssx_perf_cnt_current_tmr_valx ody_dssx_perf_cnt_current_tmr_valx_t; 12834 12835 static inline uint64_t ODY_DSSX_PERF_CNT_CURRENT_TMR_VALX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12836 static inline uint64_t ODY_DSSX_PERF_CNT_CURRENT_TMR_VALX(uint64_t a, uint64_t b) 12837 { 12838 if ((a <= 19) && (b <= 7)) 12839 return 0x87e1b00202c0ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 12840 __ody_csr_fatal("DSSX_PERF_CNT_CURRENT_TMR_VALX", 2, a, b, 0, 0, 0, 0); 12841 } 12842 12843 #define typedef_ODY_DSSX_PERF_CNT_CURRENT_TMR_VALX(a, b) ody_dssx_perf_cnt_current_tmr_valx_t 12844 #define bustype_ODY_DSSX_PERF_CNT_CURRENT_TMR_VALX(a, b) CSR_TYPE_RSL 12845 #define basename_ODY_DSSX_PERF_CNT_CURRENT_TMR_VALX(a, b) "DSSX_PERF_CNT_CURRENT_TMR_VALX" 12846 #define device_bar_ODY_DSSX_PERF_CNT_CURRENT_TMR_VALX(a, b) 0x0 /* PF_BAR0 */ 12847 #define busnum_ODY_DSSX_PERF_CNT_CURRENT_TMR_VALX(a, b) (a) 12848 #define arguments_ODY_DSSX_PERF_CNT_CURRENT_TMR_VALX(a, b) (a), (b), -1, -1 12849 12850 /** 12851 * Register (RSL) dss#_perf_cnt_dbg_cnt_sel 12852 * 12853 * Performance Counter selector Register 12854 * This register indicates to which counters to override the initial value 12855 * When DSS_PERF_CNT_DBG_INIT_VAL.CNT_INIT_VALUE is written. 12856 */ 12857 union ody_dssx_perf_cnt_dbg_cnt_sel { 12858 uint64_t u; 12859 struct ody_dssx_perf_cnt_dbg_cnt_sel_s { 12860 uint64_t gen_cnt_override : 8; 12861 uint64_t reserved_8_9 : 2; 12862 uint64_t wr_cnt_override : 1; 12863 uint64_t rd_cnt_override : 1; 12864 uint64_t gen_fill_level_cnt : 3; 12865 uint64_t txrsp_fill_level_cnt : 1; 12866 uint64_t cbusy_cnt : 4; 12867 uint64_t reserved_20_63 : 44; 12868 } s; 12869 /* struct ody_dssx_perf_cnt_dbg_cnt_sel_s cn; */ 12870 }; 12871 typedef union ody_dssx_perf_cnt_dbg_cnt_sel ody_dssx_perf_cnt_dbg_cnt_sel_t; 12872 12873 static inline uint64_t ODY_DSSX_PERF_CNT_DBG_CNT_SEL(uint64_t a) __attribute__ ((pure, always_inline)); 12874 static inline uint64_t ODY_DSSX_PERF_CNT_DBG_CNT_SEL(uint64_t a) 12875 { 12876 if (a <= 19) 12877 return 0x87e1b0020268ll + 0x1000000ll * ((a) & 0x1f); 12878 __ody_csr_fatal("DSSX_PERF_CNT_DBG_CNT_SEL", 1, a, 0, 0, 0, 0, 0); 12879 } 12880 12881 #define typedef_ODY_DSSX_PERF_CNT_DBG_CNT_SEL(a) ody_dssx_perf_cnt_dbg_cnt_sel_t 12882 #define bustype_ODY_DSSX_PERF_CNT_DBG_CNT_SEL(a) CSR_TYPE_RSL 12883 #define basename_ODY_DSSX_PERF_CNT_DBG_CNT_SEL(a) "DSSX_PERF_CNT_DBG_CNT_SEL" 12884 #define device_bar_ODY_DSSX_PERF_CNT_DBG_CNT_SEL(a) 0x0 /* PF_BAR0 */ 12885 #define busnum_ODY_DSSX_PERF_CNT_DBG_CNT_SEL(a) (a) 12886 #define arguments_ODY_DSSX_PERF_CNT_DBG_CNT_SEL(a) (a), -1, -1, -1 12887 12888 /** 12889 * Register (RSL) dss#_perf_cnt_dbg_init_val 12890 * 12891 * Performance Counter initial value Register 12892 * Initial value of the selected counter[s]. To override the initial value need to 12893 * select first the target counter[s] in DSS_PERF_CNT_DBG_CNT_SEL, then to write the 12894 * wanted initial value to this register. 12895 * The initial value takes effect for one counting iteration only, for next count it 12896 * will start from zero un-less reconfigured again. 12897 */ 12898 union ody_dssx_perf_cnt_dbg_init_val { 12899 uint64_t u; 12900 struct ody_dssx_perf_cnt_dbg_init_val_s { 12901 uint64_t cnt_init_value : 64; 12902 } s; 12903 /* struct ody_dssx_perf_cnt_dbg_init_val_s cn; */ 12904 }; 12905 typedef union ody_dssx_perf_cnt_dbg_init_val ody_dssx_perf_cnt_dbg_init_val_t; 12906 12907 static inline uint64_t ODY_DSSX_PERF_CNT_DBG_INIT_VAL(uint64_t a) __attribute__ ((pure, always_inline)); 12908 static inline uint64_t ODY_DSSX_PERF_CNT_DBG_INIT_VAL(uint64_t a) 12909 { 12910 if (a <= 19) 12911 return 0x87e1b0020270ll + 0x1000000ll * ((a) & 0x1f); 12912 __ody_csr_fatal("DSSX_PERF_CNT_DBG_INIT_VAL", 1, a, 0, 0, 0, 0, 0); 12913 } 12914 12915 #define typedef_ODY_DSSX_PERF_CNT_DBG_INIT_VAL(a) ody_dssx_perf_cnt_dbg_init_val_t 12916 #define bustype_ODY_DSSX_PERF_CNT_DBG_INIT_VAL(a) CSR_TYPE_RSL 12917 #define basename_ODY_DSSX_PERF_CNT_DBG_INIT_VAL(a) "DSSX_PERF_CNT_DBG_INIT_VAL" 12918 #define device_bar_ODY_DSSX_PERF_CNT_DBG_INIT_VAL(a) 0x0 /* PF_BAR0 */ 12919 #define busnum_ODY_DSSX_PERF_CNT_DBG_INIT_VAL(a) (a) 12920 #define arguments_ODY_DSSX_PERF_CNT_DBG_INIT_VAL(a) (a), -1, -1, -1 12921 12922 /** 12923 * Register (RSL) dss#_perf_cnt_dmd_rd_hit_cfg# 12924 * 12925 * DSS Performance Counters Demand Read Hit Configuration Register 12926 * Configuration register of demand read hit event. This register is used to configure 12927 * the filtering criteria according to CHI request properties. 12928 * Note: This register is a continuation to DSS_PERF_CNT_CFG. 12929 */ 12930 union ody_dssx_perf_cnt_dmd_rd_hit_cfgx { 12931 uint64_t u; 12932 struct ody_dssx_perf_cnt_dmd_rd_hit_cfgx_s { 12933 uint64_t demand_rd_hit_drop_event_en : 1; 12934 uint64_t demand_rd_hit_no_drop_event_en : 1; 12935 uint64_t demand_hit_match_size : 1; 12936 uint64_t demand_hit_desired_size : 3; 12937 uint64_t demand_hit_match_qos : 1; 12938 uint64_t demand_hit_desired_qos : 4; 12939 uint64_t demand_hit_match_pri : 1; 12940 uint64_t demand_hit_desired_pri : 2; 12941 uint64_t demand_hit_match_mpamns : 1; 12942 uint64_t demand_hit_desired_mpamns : 1; 12943 uint64_t demand_hit_match_pmg : 1; 12944 uint64_t demand_hit_desired_pmg : 1; 12945 uint64_t demand_hit_match_partid : 9; 12946 uint64_t demand_hit_desired_partid : 9; 12947 uint64_t demand_hit_cnt_behavior : 1; 12948 uint64_t reserved_37_63 : 27; 12949 } s; 12950 /* struct ody_dssx_perf_cnt_dmd_rd_hit_cfgx_s cn; */ 12951 }; 12952 typedef union ody_dssx_perf_cnt_dmd_rd_hit_cfgx ody_dssx_perf_cnt_dmd_rd_hit_cfgx_t; 12953 12954 static inline uint64_t ODY_DSSX_PERF_CNT_DMD_RD_HIT_CFGX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12955 static inline uint64_t ODY_DSSX_PERF_CNT_DMD_RD_HIT_CFGX(uint64_t a, uint64_t b) 12956 { 12957 if ((a <= 19) && (b <= 7)) 12958 return 0x87e1b0008350ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 12959 __ody_csr_fatal("DSSX_PERF_CNT_DMD_RD_HIT_CFGX", 2, a, b, 0, 0, 0, 0); 12960 } 12961 12962 #define typedef_ODY_DSSX_PERF_CNT_DMD_RD_HIT_CFGX(a, b) ody_dssx_perf_cnt_dmd_rd_hit_cfgx_t 12963 #define bustype_ODY_DSSX_PERF_CNT_DMD_RD_HIT_CFGX(a, b) CSR_TYPE_RSL 12964 #define basename_ODY_DSSX_PERF_CNT_DMD_RD_HIT_CFGX(a, b) "DSSX_PERF_CNT_DMD_RD_HIT_CFGX" 12965 #define device_bar_ODY_DSSX_PERF_CNT_DMD_RD_HIT_CFGX(a, b) 0x0 /* PF_BAR0 */ 12966 #define busnum_ODY_DSSX_PERF_CNT_DMD_RD_HIT_CFGX(a, b) (a) 12967 #define arguments_ODY_DSSX_PERF_CNT_DMD_RD_HIT_CFGX(a, b) (a), (b), -1, -1 12968 12969 /** 12970 * Register (RSL) dss#_perf_cnt_end_op_ctrl# 12971 * 12972 * Performance Counters End Operation Control Register 12973 * DSS performance counters control. 12974 * This register controls when to stop counters operation for manual mode 12975 * and can also be used to stop counting in timer mode. 12976 */ 12977 union ody_dssx_perf_cnt_end_op_ctrlx { 12978 uint64_t u; 12979 struct ody_dssx_perf_cnt_end_op_ctrlx_s { 12980 uint64_t manual_mode_end : 1; 12981 uint64_t reserved_1_63 : 63; 12982 } s; 12983 /* struct ody_dssx_perf_cnt_end_op_ctrlx_s cn; */ 12984 }; 12985 typedef union ody_dssx_perf_cnt_end_op_ctrlx ody_dssx_perf_cnt_end_op_ctrlx_t; 12986 12987 static inline uint64_t ODY_DSSX_PERF_CNT_END_OP_CTRLX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 12988 static inline uint64_t ODY_DSSX_PERF_CNT_END_OP_CTRLX(uint64_t a, uint64_t b) 12989 { 12990 if ((a <= 19) && (b <= 7)) 12991 return 0x87e1b00200e0ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 12992 __ody_csr_fatal("DSSX_PERF_CNT_END_OP_CTRLX", 2, a, b, 0, 0, 0, 0); 12993 } 12994 12995 #define typedef_ODY_DSSX_PERF_CNT_END_OP_CTRLX(a, b) ody_dssx_perf_cnt_end_op_ctrlx_t 12996 #define bustype_ODY_DSSX_PERF_CNT_END_OP_CTRLX(a, b) CSR_TYPE_RSL 12997 #define basename_ODY_DSSX_PERF_CNT_END_OP_CTRLX(a, b) "DSSX_PERF_CNT_END_OP_CTRLX" 12998 #define device_bar_ODY_DSSX_PERF_CNT_END_OP_CTRLX(a, b) 0x0 /* PF_BAR0 */ 12999 #define busnum_ODY_DSSX_PERF_CNT_END_OP_CTRLX(a, b) (a) 13000 #define arguments_ODY_DSSX_PERF_CNT_END_OP_CTRLX(a, b) (a), (b), -1, -1 13001 13002 /** 13003 * Register (RSL) dss#_perf_cnt_end_status# 13004 * 13005 * Performance Counters End Status Register 13006 * DSS performance counters status. 13007 * This register indicates counter status if still running for timer mode. 13008 */ 13009 union ody_dssx_perf_cnt_end_statusx { 13010 uint64_t u; 13011 struct ody_dssx_perf_cnt_end_statusx_s { 13012 uint64_t timer_mode_end : 1; 13013 uint64_t reserved_1_63 : 63; 13014 } s; 13015 /* struct ody_dssx_perf_cnt_end_statusx_s cn; */ 13016 }; 13017 typedef union ody_dssx_perf_cnt_end_statusx ody_dssx_perf_cnt_end_statusx_t; 13018 13019 static inline uint64_t ODY_DSSX_PERF_CNT_END_STATUSX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 13020 static inline uint64_t ODY_DSSX_PERF_CNT_END_STATUSX(uint64_t a, uint64_t b) 13021 { 13022 if ((a <= 19) && (b <= 7)) 13023 return 0x87e1b0020120ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 13024 __ody_csr_fatal("DSSX_PERF_CNT_END_STATUSX", 2, a, b, 0, 0, 0, 0); 13025 } 13026 13027 #define typedef_ODY_DSSX_PERF_CNT_END_STATUSX(a, b) ody_dssx_perf_cnt_end_statusx_t 13028 #define bustype_ODY_DSSX_PERF_CNT_END_STATUSX(a, b) CSR_TYPE_RSL 13029 #define basename_ODY_DSSX_PERF_CNT_END_STATUSX(a, b) "DSSX_PERF_CNT_END_STATUSX" 13030 #define device_bar_ODY_DSSX_PERF_CNT_END_STATUSX(a, b) 0x0 /* PF_BAR0 */ 13031 #define busnum_ODY_DSSX_PERF_CNT_END_STATUSX(a, b) (a) 13032 #define arguments_ODY_DSSX_PERF_CNT_END_STATUSX(a, b) (a), (b), -1, -1 13033 13034 /** 13035 * Register (RSL) dss#_perf_cnt_freerun_clr 13036 * 13037 * Performance Counters Free Running Counters Clear Register 13038 * Free running read/writes counts clear. 13039 */ 13040 union ody_dssx_perf_cnt_freerun_clr { 13041 uint64_t u; 13042 struct ody_dssx_perf_cnt_freerun_clr_s { 13043 uint64_t wr_op_cnt_clr : 1; 13044 uint64_t rd_op_cnt_clr : 1; 13045 uint64_t reserved_2_63 : 62; 13046 } s; 13047 /* struct ody_dssx_perf_cnt_freerun_clr_s cn; */ 13048 }; 13049 typedef union ody_dssx_perf_cnt_freerun_clr ody_dssx_perf_cnt_freerun_clr_t; 13050 13051 static inline uint64_t ODY_DSSX_PERF_CNT_FREERUN_CLR(uint64_t a) __attribute__ ((pure, always_inline)); 13052 static inline uint64_t ODY_DSSX_PERF_CNT_FREERUN_CLR(uint64_t a) 13053 { 13054 if (a <= 19) 13055 return 0x87e1b0020248ll + 0x1000000ll * ((a) & 0x1f); 13056 __ody_csr_fatal("DSSX_PERF_CNT_FREERUN_CLR", 1, a, 0, 0, 0, 0, 0); 13057 } 13058 13059 #define typedef_ODY_DSSX_PERF_CNT_FREERUN_CLR(a) ody_dssx_perf_cnt_freerun_clr_t 13060 #define bustype_ODY_DSSX_PERF_CNT_FREERUN_CLR(a) CSR_TYPE_RSL 13061 #define basename_ODY_DSSX_PERF_CNT_FREERUN_CLR(a) "DSSX_PERF_CNT_FREERUN_CLR" 13062 #define device_bar_ODY_DSSX_PERF_CNT_FREERUN_CLR(a) 0x0 /* PF_BAR0 */ 13063 #define busnum_ODY_DSSX_PERF_CNT_FREERUN_CLR(a) (a) 13064 #define arguments_ODY_DSSX_PERF_CNT_FREERUN_CLR(a) (a), -1, -1, -1 13065 13066 /** 13067 * Register (RSL) dss#_perf_cnt_freerun_ctrl 13068 * 13069 * Performance Counters Free Running Counters Control Register 13070 * Free running read/writes commands counter control. 13071 */ 13072 union ody_dssx_perf_cnt_freerun_ctrl { 13073 uint64_t u; 13074 struct ody_dssx_perf_cnt_freerun_ctrl_s { 13075 uint64_t wr_op_cnt_en : 1; 13076 uint64_t rd_op_cnt_en : 1; 13077 uint64_t wr_interrupt_en : 1; 13078 uint64_t rd_interrupt_en : 1; 13079 uint64_t wr_wrap_value : 1; 13080 uint64_t rd_wrap_value : 1; 13081 uint64_t reserved_6_63 : 58; 13082 } s; 13083 /* struct ody_dssx_perf_cnt_freerun_ctrl_s cn; */ 13084 }; 13085 typedef union ody_dssx_perf_cnt_freerun_ctrl ody_dssx_perf_cnt_freerun_ctrl_t; 13086 13087 static inline uint64_t ODY_DSSX_PERF_CNT_FREERUN_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 13088 static inline uint64_t ODY_DSSX_PERF_CNT_FREERUN_CTRL(uint64_t a) 13089 { 13090 if (a <= 19) 13091 return 0x87e1b0020240ll + 0x1000000ll * ((a) & 0x1f); 13092 __ody_csr_fatal("DSSX_PERF_CNT_FREERUN_CTRL", 1, a, 0, 0, 0, 0, 0); 13093 } 13094 13095 #define typedef_ODY_DSSX_PERF_CNT_FREERUN_CTRL(a) ody_dssx_perf_cnt_freerun_ctrl_t 13096 #define bustype_ODY_DSSX_PERF_CNT_FREERUN_CTRL(a) CSR_TYPE_RSL 13097 #define basename_ODY_DSSX_PERF_CNT_FREERUN_CTRL(a) "DSSX_PERF_CNT_FREERUN_CTRL" 13098 #define device_bar_ODY_DSSX_PERF_CNT_FREERUN_CTRL(a) 0x0 /* PF_BAR0 */ 13099 #define busnum_ODY_DSSX_PERF_CNT_FREERUN_CTRL(a) (a) 13100 #define arguments_ODY_DSSX_PERF_CNT_FREERUN_CTRL(a) (a), -1, -1, -1 13101 13102 /** 13103 * Register (RSL) dss#_perf_cnt_freerun_ovrflow 13104 * 13105 * Performance Counters Overflow indication of DRAM Read/Write Operations Register 13106 * Free running count of DRAM read operations. 13107 */ 13108 union ody_dssx_perf_cnt_freerun_ovrflow { 13109 uint64_t u; 13110 struct ody_dssx_perf_cnt_freerun_ovrflow_s { 13111 uint64_t wr_overflow : 1; 13112 uint64_t rd_overflow : 1; 13113 uint64_t reserved_2_63 : 62; 13114 } s; 13115 /* struct ody_dssx_perf_cnt_freerun_ovrflow_s cn; */ 13116 }; 13117 typedef union ody_dssx_perf_cnt_freerun_ovrflow ody_dssx_perf_cnt_freerun_ovrflow_t; 13118 13119 static inline uint64_t ODY_DSSX_PERF_CNT_FREERUN_OVRFLOW(uint64_t a) __attribute__ ((pure, always_inline)); 13120 static inline uint64_t ODY_DSSX_PERF_CNT_FREERUN_OVRFLOW(uint64_t a) 13121 { 13122 if (a <= 19) 13123 return 0x87e1b0020260ll + 0x1000000ll * ((a) & 0x1f); 13124 __ody_csr_fatal("DSSX_PERF_CNT_FREERUN_OVRFLOW", 1, a, 0, 0, 0, 0, 0); 13125 } 13126 13127 #define typedef_ODY_DSSX_PERF_CNT_FREERUN_OVRFLOW(a) ody_dssx_perf_cnt_freerun_ovrflow_t 13128 #define bustype_ODY_DSSX_PERF_CNT_FREERUN_OVRFLOW(a) CSR_TYPE_RSL 13129 #define basename_ODY_DSSX_PERF_CNT_FREERUN_OVRFLOW(a) "DSSX_PERF_CNT_FREERUN_OVRFLOW" 13130 #define device_bar_ODY_DSSX_PERF_CNT_FREERUN_OVRFLOW(a) 0x0 /* PF_BAR0 */ 13131 #define busnum_ODY_DSSX_PERF_CNT_FREERUN_OVRFLOW(a) (a) 13132 #define arguments_ODY_DSSX_PERF_CNT_FREERUN_OVRFLOW(a) (a), -1, -1, -1 13133 13134 /** 13135 * Register (RSL) dss#_perf_cnt_int_ena_w1c 13136 * 13137 * DSS Interrupt Enable Clear Registers 13138 * This register clears interrupt enable bits. 13139 */ 13140 union ody_dssx_perf_cnt_int_ena_w1c { 13141 uint64_t u; 13142 struct ody_dssx_perf_cnt_int_ena_w1c_s { 13143 uint64_t perfcnt_general_ovrflw_intr : 8; 13144 uint64_t perfcnt_wr_freerun_ovrflw_intr : 1; 13145 uint64_t perfcnt_rd_freerun_ovrflw_intr : 1; 13146 uint64_t gen_fill_lvl_cnt_ovrflw_intr : 3; 13147 uint64_t txrsp_fill_lvl_cnt_ovrflw_intr : 1; 13148 uint64_t wr_latency_cnt_ovrflw_intr : 1; 13149 uint64_t rd_latency_cnt_ovrflw_intr : 1; 13150 uint64_t cbusy_cnt_ovrflw_intr : 4; 13151 uint64_t reserved_20_63 : 44; 13152 } s; 13153 /* struct ody_dssx_perf_cnt_int_ena_w1c_s cn; */ 13154 }; 13155 typedef union ody_dssx_perf_cnt_int_ena_w1c ody_dssx_perf_cnt_int_ena_w1c_t; 13156 13157 static inline uint64_t ODY_DSSX_PERF_CNT_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 13158 static inline uint64_t ODY_DSSX_PERF_CNT_INT_ENA_W1C(uint64_t a) 13159 { 13160 if (a <= 19) 13161 return 0x87e1b0028010ll + 0x1000000ll * ((a) & 0x1f); 13162 __ody_csr_fatal("DSSX_PERF_CNT_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0); 13163 } 13164 13165 #define typedef_ODY_DSSX_PERF_CNT_INT_ENA_W1C(a) ody_dssx_perf_cnt_int_ena_w1c_t 13166 #define bustype_ODY_DSSX_PERF_CNT_INT_ENA_W1C(a) CSR_TYPE_RSL 13167 #define basename_ODY_DSSX_PERF_CNT_INT_ENA_W1C(a) "DSSX_PERF_CNT_INT_ENA_W1C" 13168 #define device_bar_ODY_DSSX_PERF_CNT_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */ 13169 #define busnum_ODY_DSSX_PERF_CNT_INT_ENA_W1C(a) (a) 13170 #define arguments_ODY_DSSX_PERF_CNT_INT_ENA_W1C(a) (a), -1, -1, -1 13171 13172 /** 13173 * Register (RSL) dss#_perf_cnt_int_ena_w1s 13174 * 13175 * DSS Interrupt Enable Set Registers 13176 * This register sets interrupt enable bits. 13177 */ 13178 union ody_dssx_perf_cnt_int_ena_w1s { 13179 uint64_t u; 13180 struct ody_dssx_perf_cnt_int_ena_w1s_s { 13181 uint64_t perfcnt_general_ovrflw_intr : 8; 13182 uint64_t perfcnt_wr_freerun_ovrflw_intr : 1; 13183 uint64_t perfcnt_rd_freerun_ovrflw_intr : 1; 13184 uint64_t gen_fill_lvl_cnt_ovrflw_intr : 3; 13185 uint64_t txrsp_fill_lvl_cnt_ovrflw_intr : 1; 13186 uint64_t wr_latency_cnt_ovrflw_intr : 1; 13187 uint64_t rd_latency_cnt_ovrflw_intr : 1; 13188 uint64_t cbusy_cnt_ovrflw_intr : 4; 13189 uint64_t reserved_20_63 : 44; 13190 } s; 13191 /* struct ody_dssx_perf_cnt_int_ena_w1s_s cn; */ 13192 }; 13193 typedef union ody_dssx_perf_cnt_int_ena_w1s ody_dssx_perf_cnt_int_ena_w1s_t; 13194 13195 static inline uint64_t ODY_DSSX_PERF_CNT_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 13196 static inline uint64_t ODY_DSSX_PERF_CNT_INT_ENA_W1S(uint64_t a) 13197 { 13198 if (a <= 19) 13199 return 0x87e1b0028018ll + 0x1000000ll * ((a) & 0x1f); 13200 __ody_csr_fatal("DSSX_PERF_CNT_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0); 13201 } 13202 13203 #define typedef_ODY_DSSX_PERF_CNT_INT_ENA_W1S(a) ody_dssx_perf_cnt_int_ena_w1s_t 13204 #define bustype_ODY_DSSX_PERF_CNT_INT_ENA_W1S(a) CSR_TYPE_RSL 13205 #define basename_ODY_DSSX_PERF_CNT_INT_ENA_W1S(a) "DSSX_PERF_CNT_INT_ENA_W1S" 13206 #define device_bar_ODY_DSSX_PERF_CNT_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */ 13207 #define busnum_ODY_DSSX_PERF_CNT_INT_ENA_W1S(a) (a) 13208 #define arguments_ODY_DSSX_PERF_CNT_INT_ENA_W1S(a) (a), -1, -1, -1 13209 13210 /** 13211 * Register (RSL) dss#_perf_cnt_int_w1c 13212 * 13213 * DSS Interrupt Register 13214 * This register is for DSS-based interrupts. 13215 */ 13216 union ody_dssx_perf_cnt_int_w1c { 13217 uint64_t u; 13218 struct ody_dssx_perf_cnt_int_w1c_s { 13219 uint64_t perfcnt_general_ovrflw_intr : 8; 13220 uint64_t perfcnt_wr_freerun_ovrflw_intr : 1; 13221 uint64_t perfcnt_rd_freerun_ovrflw_intr : 1; 13222 uint64_t gen_fill_lvl_cnt_ovrflw_intr : 3; 13223 uint64_t txrsp_fill_lvl_cnt_ovrflw_intr : 1; 13224 uint64_t wr_latency_cnt_ovrflw_intr : 1; 13225 uint64_t rd_latency_cnt_ovrflw_intr : 1; 13226 uint64_t cbusy_cnt_ovrflw_intr : 4; 13227 uint64_t reserved_20_63 : 44; 13228 } s; 13229 /* struct ody_dssx_perf_cnt_int_w1c_s cn; */ 13230 }; 13231 typedef union ody_dssx_perf_cnt_int_w1c ody_dssx_perf_cnt_int_w1c_t; 13232 13233 static inline uint64_t ODY_DSSX_PERF_CNT_INT_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 13234 static inline uint64_t ODY_DSSX_PERF_CNT_INT_W1C(uint64_t a) 13235 { 13236 if (a <= 19) 13237 return 0x87e1b0028000ll + 0x1000000ll * ((a) & 0x1f); 13238 __ody_csr_fatal("DSSX_PERF_CNT_INT_W1C", 1, a, 0, 0, 0, 0, 0); 13239 } 13240 13241 #define typedef_ODY_DSSX_PERF_CNT_INT_W1C(a) ody_dssx_perf_cnt_int_w1c_t 13242 #define bustype_ODY_DSSX_PERF_CNT_INT_W1C(a) CSR_TYPE_RSL 13243 #define basename_ODY_DSSX_PERF_CNT_INT_W1C(a) "DSSX_PERF_CNT_INT_W1C" 13244 #define device_bar_ODY_DSSX_PERF_CNT_INT_W1C(a) 0x0 /* PF_BAR0 */ 13245 #define busnum_ODY_DSSX_PERF_CNT_INT_W1C(a) (a) 13246 #define arguments_ODY_DSSX_PERF_CNT_INT_W1C(a) (a), -1, -1, -1 13247 13248 /** 13249 * Register (RSL) dss#_perf_cnt_int_w1s 13250 * 13251 * DSS Interrupt Set Registers 13252 * This register sets interrupt bits. 13253 */ 13254 union ody_dssx_perf_cnt_int_w1s { 13255 uint64_t u; 13256 struct ody_dssx_perf_cnt_int_w1s_s { 13257 uint64_t perfcnt_general_ovrflw_intr : 8; 13258 uint64_t perfcnt_wr_freerun_ovrflw_intr : 1; 13259 uint64_t perfcnt_rd_freerun_ovrflw_intr : 1; 13260 uint64_t gen_fill_lvl_cnt_ovrflw_intr : 3; 13261 uint64_t txrsp_fill_lvl_cnt_ovrflw_intr : 1; 13262 uint64_t wr_latency_cnt_ovrflw_intr : 1; 13263 uint64_t rd_latency_cnt_ovrflw_intr : 1; 13264 uint64_t cbusy_cnt_ovrflw_intr : 4; 13265 uint64_t reserved_20_63 : 44; 13266 } s; 13267 /* struct ody_dssx_perf_cnt_int_w1s_s cn; */ 13268 }; 13269 typedef union ody_dssx_perf_cnt_int_w1s ody_dssx_perf_cnt_int_w1s_t; 13270 13271 static inline uint64_t ODY_DSSX_PERF_CNT_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 13272 static inline uint64_t ODY_DSSX_PERF_CNT_INT_W1S(uint64_t a) 13273 { 13274 if (a <= 19) 13275 return 0x87e1b0028008ll + 0x1000000ll * ((a) & 0x1f); 13276 __ody_csr_fatal("DSSX_PERF_CNT_INT_W1S", 1, a, 0, 0, 0, 0, 0); 13277 } 13278 13279 #define typedef_ODY_DSSX_PERF_CNT_INT_W1S(a) ody_dssx_perf_cnt_int_w1s_t 13280 #define bustype_ODY_DSSX_PERF_CNT_INT_W1S(a) CSR_TYPE_RSL 13281 #define basename_ODY_DSSX_PERF_CNT_INT_W1S(a) "DSSX_PERF_CNT_INT_W1S" 13282 #define device_bar_ODY_DSSX_PERF_CNT_INT_W1S(a) 0x0 /* PF_BAR0 */ 13283 #define busnum_ODY_DSSX_PERF_CNT_INT_W1S(a) (a) 13284 #define arguments_ODY_DSSX_PERF_CNT_INT_W1S(a) (a), -1, -1, -1 13285 13286 /** 13287 * Register (RSL) dss#_perf_cnt_op_mode_ctrl# 13288 * 13289 * Performance Counters Operating Mode Control Register 13290 * DSS performance counters control. 13291 * This register configures the operating mode of the counters. 13292 */ 13293 union ody_dssx_perf_cnt_op_mode_ctrlx { 13294 uint64_t u; 13295 struct ody_dssx_perf_cnt_op_mode_ctrlx_s { 13296 uint64_t operating_mode : 1; 13297 uint64_t reserved_1_63 : 63; 13298 } s; 13299 /* struct ody_dssx_perf_cnt_op_mode_ctrlx_s cn; */ 13300 }; 13301 typedef union ody_dssx_perf_cnt_op_mode_ctrlx ody_dssx_perf_cnt_op_mode_ctrlx_t; 13302 13303 static inline uint64_t ODY_DSSX_PERF_CNT_OP_MODE_CTRLX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 13304 static inline uint64_t ODY_DSSX_PERF_CNT_OP_MODE_CTRLX(uint64_t a, uint64_t b) 13305 { 13306 if ((a <= 19) && (b <= 7)) 13307 return 0x87e1b0020020ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 13308 __ody_csr_fatal("DSSX_PERF_CNT_OP_MODE_CTRLX", 2, a, b, 0, 0, 0, 0); 13309 } 13310 13311 #define typedef_ODY_DSSX_PERF_CNT_OP_MODE_CTRLX(a, b) ody_dssx_perf_cnt_op_mode_ctrlx_t 13312 #define bustype_ODY_DSSX_PERF_CNT_OP_MODE_CTRLX(a, b) CSR_TYPE_RSL 13313 #define basename_ODY_DSSX_PERF_CNT_OP_MODE_CTRLX(a, b) "DSSX_PERF_CNT_OP_MODE_CTRLX" 13314 #define device_bar_ODY_DSSX_PERF_CNT_OP_MODE_CTRLX(a, b) 0x0 /* PF_BAR0 */ 13315 #define busnum_ODY_DSSX_PERF_CNT_OP_MODE_CTRLX(a, b) (a) 13316 #define arguments_ODY_DSSX_PERF_CNT_OP_MODE_CTRLX(a, b) (a), (b), -1, -1 13317 13318 /** 13319 * Register (RSL) dss#_perf_cnt_overflow# 13320 * 13321 * Performance Counters overflow indication Register 13322 * Status register to indicate if counter overflowed. 13323 */ 13324 union ody_dssx_perf_cnt_overflowx { 13325 uint64_t u; 13326 struct ody_dssx_perf_cnt_overflowx_s { 13327 uint64_t counter_overflow : 1; 13328 uint64_t reserved_1_63 : 63; 13329 } s; 13330 /* struct ody_dssx_perf_cnt_overflowx_s cn; */ 13331 }; 13332 typedef union ody_dssx_perf_cnt_overflowx ody_dssx_perf_cnt_overflowx_t; 13333 13334 static inline uint64_t ODY_DSSX_PERF_CNT_OVERFLOWX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 13335 static inline uint64_t ODY_DSSX_PERF_CNT_OVERFLOWX(uint64_t a, uint64_t b) 13336 { 13337 if ((a <= 19) && (b <= 7)) 13338 return 0x87e1b0020200ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 13339 __ody_csr_fatal("DSSX_PERF_CNT_OVERFLOWX", 2, a, b, 0, 0, 0, 0); 13340 } 13341 13342 #define typedef_ODY_DSSX_PERF_CNT_OVERFLOWX(a, b) ody_dssx_perf_cnt_overflowx_t 13343 #define bustype_ODY_DSSX_PERF_CNT_OVERFLOWX(a, b) CSR_TYPE_RSL 13344 #define basename_ODY_DSSX_PERF_CNT_OVERFLOWX(a, b) "DSSX_PERF_CNT_OVERFLOWX" 13345 #define device_bar_ODY_DSSX_PERF_CNT_OVERFLOWX(a, b) 0x0 /* PF_BAR0 */ 13346 #define busnum_ODY_DSSX_PERF_CNT_OVERFLOWX(a, b) (a) 13347 #define arguments_ODY_DSSX_PERF_CNT_OVERFLOWX(a, b) (a), (b), -1, -1 13348 13349 /** 13350 * Register (RSL) dss#_perf_cnt_rd_cmd_cfg# 13351 * 13352 * DSS Performance Counters CHI Read Command event Configuration Register 13353 * Configuration register of CHI read command event. This register is used to configure 13354 * the filtering criteria according to CHI request properties. 13355 * Note: This register is a continuation to DSS_PERF_CNT_CFG. 13356 */ 13357 union ody_dssx_perf_cnt_rd_cmd_cfgx { 13358 uint64_t u; 13359 struct ody_dssx_perf_cnt_rd_cmd_cfgx_s { 13360 uint64_t rd_cmd_event_en : 1; 13361 uint64_t rd_cmd_match_size : 1; 13362 uint64_t rd_cmd_desired_size : 3; 13363 uint64_t rd_cmd_match_pri : 1; 13364 uint64_t rd_cmd_desired_pri : 2; 13365 uint64_t rd_cmd_match_mpamns : 1; 13366 uint64_t rd_cmd_desired_mpamns : 1; 13367 uint64_t rd_cmd_match_pmg : 1; 13368 uint64_t rd_cmd_desired_pmg : 1; 13369 uint64_t rd_cmd_match_partid : 9; 13370 uint64_t rd_cmd_desired_partid : 9; 13371 uint64_t rd_cmd_match_req_src : 1; 13372 uint64_t rd_cmd_desired_req_src : 2; 13373 uint64_t rd_cmd_cnt_behavior : 1; 13374 uint64_t reserved_34_63 : 30; 13375 } s; 13376 /* struct ody_dssx_perf_cnt_rd_cmd_cfgx_s cn; */ 13377 }; 13378 typedef union ody_dssx_perf_cnt_rd_cmd_cfgx ody_dssx_perf_cnt_rd_cmd_cfgx_t; 13379 13380 static inline uint64_t ODY_DSSX_PERF_CNT_RD_CMD_CFGX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 13381 static inline uint64_t ODY_DSSX_PERF_CNT_RD_CMD_CFGX(uint64_t a, uint64_t b) 13382 { 13383 if ((a <= 19) && (b <= 7)) 13384 return 0x87e1b0008390ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 13385 __ody_csr_fatal("DSSX_PERF_CNT_RD_CMD_CFGX", 2, a, b, 0, 0, 0, 0); 13386 } 13387 13388 #define typedef_ODY_DSSX_PERF_CNT_RD_CMD_CFGX(a, b) ody_dssx_perf_cnt_rd_cmd_cfgx_t 13389 #define bustype_ODY_DSSX_PERF_CNT_RD_CMD_CFGX(a, b) CSR_TYPE_RSL 13390 #define basename_ODY_DSSX_PERF_CNT_RD_CMD_CFGX(a, b) "DSSX_PERF_CNT_RD_CMD_CFGX" 13391 #define device_bar_ODY_DSSX_PERF_CNT_RD_CMD_CFGX(a, b) 0x0 /* PF_BAR0 */ 13392 #define busnum_ODY_DSSX_PERF_CNT_RD_CMD_CFGX(a, b) (a) 13393 #define arguments_ODY_DSSX_PERF_CNT_RD_CMD_CFGX(a, b) (a), (b), -1, -1 13394 13395 /** 13396 * Register (RSL) dss#_perf_cnt_security_cfg 13397 * 13398 * DSS Performance Counters Security Configuration Register 13399 * Configuration register of performance counters security. 13400 */ 13401 union ody_dssx_perf_cnt_security_cfg { 13402 uint64_t u; 13403 struct ody_dssx_perf_cnt_security_cfg_s { 13404 uint64_t allow_mon_secured_partid : 8; 13405 uint64_t reserved_8_63 : 56; 13406 } s; 13407 /* struct ody_dssx_perf_cnt_security_cfg_s cn; */ 13408 }; 13409 typedef union ody_dssx_perf_cnt_security_cfg ody_dssx_perf_cnt_security_cfg_t; 13410 13411 static inline uint64_t ODY_DSSX_PERF_CNT_SECURITY_CFG(uint64_t a) __attribute__ ((pure, always_inline)); 13412 static inline uint64_t ODY_DSSX_PERF_CNT_SECURITY_CFG(uint64_t a) 13413 { 13414 if (a <= 19) 13415 return 0x87e1b0008410ll + 0x1000000ll * ((a) & 0x1f); 13416 __ody_csr_fatal("DSSX_PERF_CNT_SECURITY_CFG", 1, a, 0, 0, 0, 0, 0); 13417 } 13418 13419 #define typedef_ODY_DSSX_PERF_CNT_SECURITY_CFG(a) ody_dssx_perf_cnt_security_cfg_t 13420 #define bustype_ODY_DSSX_PERF_CNT_SECURITY_CFG(a) CSR_TYPE_RSL 13421 #define basename_ODY_DSSX_PERF_CNT_SECURITY_CFG(a) "DSSX_PERF_CNT_SECURITY_CFG" 13422 #define device_bar_ODY_DSSX_PERF_CNT_SECURITY_CFG(a) 0x0 /* PF_BAR0 */ 13423 #define busnum_ODY_DSSX_PERF_CNT_SECURITY_CFG(a) (a) 13424 #define arguments_ODY_DSSX_PERF_CNT_SECURITY_CFG(a) (a), -1, -1, -1 13425 13426 /** 13427 * Register (RSL) dss#_perf_cnt_start_op_ctrl# 13428 * 13429 * Performance Counters Start Operation Control Register 13430 * DSS performance counters control. 13431 * This register controls the start of counters operation. 13432 */ 13433 union ody_dssx_perf_cnt_start_op_ctrlx { 13434 uint64_t u; 13435 struct ody_dssx_perf_cnt_start_op_ctrlx_s { 13436 uint64_t start : 1; 13437 uint64_t ongoing_cnt_op : 1; 13438 uint64_t reserved_2_63 : 62; 13439 } s; 13440 /* struct ody_dssx_perf_cnt_start_op_ctrlx_s cn; */ 13441 }; 13442 typedef union ody_dssx_perf_cnt_start_op_ctrlx ody_dssx_perf_cnt_start_op_ctrlx_t; 13443 13444 static inline uint64_t ODY_DSSX_PERF_CNT_START_OP_CTRLX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 13445 static inline uint64_t ODY_DSSX_PERF_CNT_START_OP_CTRLX(uint64_t a, uint64_t b) 13446 { 13447 if ((a <= 19) && (b <= 7)) 13448 return 0x87e1b00200a0ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 13449 __ody_csr_fatal("DSSX_PERF_CNT_START_OP_CTRLX", 2, a, b, 0, 0, 0, 0); 13450 } 13451 13452 #define typedef_ODY_DSSX_PERF_CNT_START_OP_CTRLX(a, b) ody_dssx_perf_cnt_start_op_ctrlx_t 13453 #define bustype_ODY_DSSX_PERF_CNT_START_OP_CTRLX(a, b) CSR_TYPE_RSL 13454 #define basename_ODY_DSSX_PERF_CNT_START_OP_CTRLX(a, b) "DSSX_PERF_CNT_START_OP_CTRLX" 13455 #define device_bar_ODY_DSSX_PERF_CNT_START_OP_CTRLX(a, b) 0x0 /* PF_BAR0 */ 13456 #define busnum_ODY_DSSX_PERF_CNT_START_OP_CTRLX(a, b) (a) 13457 #define arguments_ODY_DSSX_PERF_CNT_START_OP_CTRLX(a, b) (a), (b), -1, -1 13458 13459 /** 13460 * Register (RSL) dss#_perf_cnt_target_tmr_val# 13461 * 13462 * Performance Counters Target Timer Value Register 13463 * DSS performance counters timer control. 13464 * This register configures the target timer value for timer operation mode. 13465 */ 13466 union ody_dssx_perf_cnt_target_tmr_valx { 13467 uint64_t u; 13468 struct ody_dssx_perf_cnt_target_tmr_valx_s { 13469 uint64_t timer_value : 64; 13470 } s; 13471 /* struct ody_dssx_perf_cnt_target_tmr_valx_s cn; */ 13472 }; 13473 typedef union ody_dssx_perf_cnt_target_tmr_valx ody_dssx_perf_cnt_target_tmr_valx_t; 13474 13475 static inline uint64_t ODY_DSSX_PERF_CNT_TARGET_TMR_VALX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 13476 static inline uint64_t ODY_DSSX_PERF_CNT_TARGET_TMR_VALX(uint64_t a, uint64_t b) 13477 { 13478 if ((a <= 19) && (b <= 7)) 13479 return 0x87e1b0020060ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 13480 __ody_csr_fatal("DSSX_PERF_CNT_TARGET_TMR_VALX", 2, a, b, 0, 0, 0, 0); 13481 } 13482 13483 #define typedef_ODY_DSSX_PERF_CNT_TARGET_TMR_VALX(a, b) ody_dssx_perf_cnt_target_tmr_valx_t 13484 #define bustype_ODY_DSSX_PERF_CNT_TARGET_TMR_VALX(a, b) CSR_TYPE_RSL 13485 #define basename_ODY_DSSX_PERF_CNT_TARGET_TMR_VALX(a, b) "DSSX_PERF_CNT_TARGET_TMR_VALX" 13486 #define device_bar_ODY_DSSX_PERF_CNT_TARGET_TMR_VALX(a, b) 0x0 /* PF_BAR0 */ 13487 #define busnum_ODY_DSSX_PERF_CNT_TARGET_TMR_VALX(a, b) (a) 13488 #define arguments_ODY_DSSX_PERF_CNT_TARGET_TMR_VALX(a, b) (a), (b), -1, -1 13489 13490 /** 13491 * Register (RSL) dss#_perf_cnt_value# 13492 * 13493 * Performance Counters Value Register 13494 * Count of enabled events that occurred when the counter is enabled. 13495 */ 13496 union ody_dssx_perf_cnt_valuex { 13497 uint64_t u; 13498 struct ody_dssx_perf_cnt_valuex_s { 13499 uint64_t counter_value : 64; 13500 } s; 13501 /* struct ody_dssx_perf_cnt_valuex_s cn; */ 13502 }; 13503 typedef union ody_dssx_perf_cnt_valuex ody_dssx_perf_cnt_valuex_t; 13504 13505 static inline uint64_t ODY_DSSX_PERF_CNT_VALUEX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 13506 static inline uint64_t ODY_DSSX_PERF_CNT_VALUEX(uint64_t a, uint64_t b) 13507 { 13508 if ((a <= 19) && (b <= 7)) 13509 return 0x87e1b00201c0ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 13510 __ody_csr_fatal("DSSX_PERF_CNT_VALUEX", 2, a, b, 0, 0, 0, 0); 13511 } 13512 13513 #define typedef_ODY_DSSX_PERF_CNT_VALUEX(a, b) ody_dssx_perf_cnt_valuex_t 13514 #define bustype_ODY_DSSX_PERF_CNT_VALUEX(a, b) CSR_TYPE_RSL 13515 #define basename_ODY_DSSX_PERF_CNT_VALUEX(a, b) "DSSX_PERF_CNT_VALUEX" 13516 #define device_bar_ODY_DSSX_PERF_CNT_VALUEX(a, b) 0x0 /* PF_BAR0 */ 13517 #define busnum_ODY_DSSX_PERF_CNT_VALUEX(a, b) (a) 13518 #define arguments_ODY_DSSX_PERF_CNT_VALUEX(a, b) (a), (b), -1, -1 13519 13520 /** 13521 * Register (RSL) dss#_perf_cnt_value_rd_op 13522 * 13523 * Performance Counters Value of DRAM Read Operations Register 13524 * Free running count of DRAM read operations. 13525 */ 13526 union ody_dssx_perf_cnt_value_rd_op { 13527 uint64_t u; 13528 struct ody_dssx_perf_cnt_value_rd_op_s { 13529 uint64_t rd_op_counter_value : 64; 13530 } s; 13531 /* struct ody_dssx_perf_cnt_value_rd_op_s cn; */ 13532 }; 13533 typedef union ody_dssx_perf_cnt_value_rd_op ody_dssx_perf_cnt_value_rd_op_t; 13534 13535 static inline uint64_t ODY_DSSX_PERF_CNT_VALUE_RD_OP(uint64_t a) __attribute__ ((pure, always_inline)); 13536 static inline uint64_t ODY_DSSX_PERF_CNT_VALUE_RD_OP(uint64_t a) 13537 { 13538 if (a <= 19) 13539 return 0x87e1b0020258ll + 0x1000000ll * ((a) & 0x1f); 13540 __ody_csr_fatal("DSSX_PERF_CNT_VALUE_RD_OP", 1, a, 0, 0, 0, 0, 0); 13541 } 13542 13543 #define typedef_ODY_DSSX_PERF_CNT_VALUE_RD_OP(a) ody_dssx_perf_cnt_value_rd_op_t 13544 #define bustype_ODY_DSSX_PERF_CNT_VALUE_RD_OP(a) CSR_TYPE_RSL 13545 #define basename_ODY_DSSX_PERF_CNT_VALUE_RD_OP(a) "DSSX_PERF_CNT_VALUE_RD_OP" 13546 #define device_bar_ODY_DSSX_PERF_CNT_VALUE_RD_OP(a) 0x0 /* PF_BAR0 */ 13547 #define busnum_ODY_DSSX_PERF_CNT_VALUE_RD_OP(a) (a) 13548 #define arguments_ODY_DSSX_PERF_CNT_VALUE_RD_OP(a) (a), -1, -1, -1 13549 13550 /** 13551 * Register (RSL) dss#_perf_cnt_value_wr_op 13552 * 13553 * Performance Counters Value of DRAM Write Operations Register 13554 * Free running count of DRAM write operations. 13555 */ 13556 union ody_dssx_perf_cnt_value_wr_op { 13557 uint64_t u; 13558 struct ody_dssx_perf_cnt_value_wr_op_s { 13559 uint64_t wr_op_counter_value : 64; 13560 } s; 13561 /* struct ody_dssx_perf_cnt_value_wr_op_s cn; */ 13562 }; 13563 typedef union ody_dssx_perf_cnt_value_wr_op ody_dssx_perf_cnt_value_wr_op_t; 13564 13565 static inline uint64_t ODY_DSSX_PERF_CNT_VALUE_WR_OP(uint64_t a) __attribute__ ((pure, always_inline)); 13566 static inline uint64_t ODY_DSSX_PERF_CNT_VALUE_WR_OP(uint64_t a) 13567 { 13568 if (a <= 19) 13569 return 0x87e1b0020250ll + 0x1000000ll * ((a) & 0x1f); 13570 __ody_csr_fatal("DSSX_PERF_CNT_VALUE_WR_OP", 1, a, 0, 0, 0, 0, 0); 13571 } 13572 13573 #define typedef_ODY_DSSX_PERF_CNT_VALUE_WR_OP(a) ody_dssx_perf_cnt_value_wr_op_t 13574 #define bustype_ODY_DSSX_PERF_CNT_VALUE_WR_OP(a) CSR_TYPE_RSL 13575 #define basename_ODY_DSSX_PERF_CNT_VALUE_WR_OP(a) "DSSX_PERF_CNT_VALUE_WR_OP" 13576 #define device_bar_ODY_DSSX_PERF_CNT_VALUE_WR_OP(a) 0x0 /* PF_BAR0 */ 13577 #define busnum_ODY_DSSX_PERF_CNT_VALUE_WR_OP(a) (a) 13578 #define arguments_ODY_DSSX_PERF_CNT_VALUE_WR_OP(a) (a), -1, -1, -1 13579 13580 /** 13581 * Register (RSL) dss#_perf_cnt_wr_cmd_cfg# 13582 * 13583 * DSS Performance Counters CHI Write Command event Configuration Register 13584 * Configuration register of CHI write command event. This register is used to 13585 * configure the filtering criteria according to CHI request properties. 13586 * Note: This register is a continuation to DSS_PERF_CNT_CFG. 13587 */ 13588 union ody_dssx_perf_cnt_wr_cmd_cfgx { 13589 uint64_t u; 13590 struct ody_dssx_perf_cnt_wr_cmd_cfgx_s { 13591 uint64_t wr_cmd_event_en : 1; 13592 uint64_t wr_cmd_match_size : 1; 13593 uint64_t wr_cmd_desired_size : 3; 13594 uint64_t wr_cmd_match_pri : 1; 13595 uint64_t wr_cmd_desired_pri : 2; 13596 uint64_t wr_cmd_match_mpamns : 1; 13597 uint64_t wr_cmd_desired_mpamns : 1; 13598 uint64_t wr_cmd_match_pmg : 1; 13599 uint64_t wr_cmd_desired_pmg : 1; 13600 uint64_t wr_cmd_match_partid : 9; 13601 uint64_t wr_cmd_desired_partid : 9; 13602 uint64_t wr_cmd_match_req_src : 1; 13603 uint64_t wr_cmd_desired_req_src : 2; 13604 uint64_t wr_cmd_match_req_type : 1; 13605 uint64_t wr_cmd_desired_req_type : 2; 13606 uint64_t wr_cmd_cnt_behavior : 1; 13607 uint64_t reserved_37_63 : 27; 13608 } s; 13609 /* struct ody_dssx_perf_cnt_wr_cmd_cfgx_s cn; */ 13610 }; 13611 typedef union ody_dssx_perf_cnt_wr_cmd_cfgx ody_dssx_perf_cnt_wr_cmd_cfgx_t; 13612 13613 static inline uint64_t ODY_DSSX_PERF_CNT_WR_CMD_CFGX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 13614 static inline uint64_t ODY_DSSX_PERF_CNT_WR_CMD_CFGX(uint64_t a, uint64_t b) 13615 { 13616 if ((a <= 19) && (b <= 7)) 13617 return 0x87e1b00083d0ll + 0x1000000ll * ((a) & 0x1f) + 8ll * ((b) & 0x7); 13618 __ody_csr_fatal("DSSX_PERF_CNT_WR_CMD_CFGX", 2, a, b, 0, 0, 0, 0); 13619 } 13620 13621 #define typedef_ODY_DSSX_PERF_CNT_WR_CMD_CFGX(a, b) ody_dssx_perf_cnt_wr_cmd_cfgx_t 13622 #define bustype_ODY_DSSX_PERF_CNT_WR_CMD_CFGX(a, b) CSR_TYPE_RSL 13623 #define basename_ODY_DSSX_PERF_CNT_WR_CMD_CFGX(a, b) "DSSX_PERF_CNT_WR_CMD_CFGX" 13624 #define device_bar_ODY_DSSX_PERF_CNT_WR_CMD_CFGX(a, b) 0x0 /* PF_BAR0 */ 13625 #define busnum_ODY_DSSX_PERF_CNT_WR_CMD_CFGX(a, b) (a) 13626 #define arguments_ODY_DSSX_PERF_CNT_WR_CMD_CFGX(a, b) (a), (b), -1, -1 13627 13628 /** 13629 * Register (RSL) dss#_phy_apb_reset_n 13630 * 13631 * DSS PHY APB Clock Domain Reset Register 13632 * PHY APB clock domain software reset - active low. 13633 */ 13634 union ody_dssx_phy_apb_reset_n { 13635 uint64_t u; 13636 struct ody_dssx_phy_apb_reset_n_s { 13637 uint64_t s_phy_apb_reset_n : 1; 13638 uint64_t reserved_1_63 : 63; 13639 } s; 13640 /* struct ody_dssx_phy_apb_reset_n_s cn; */ 13641 }; 13642 typedef union ody_dssx_phy_apb_reset_n ody_dssx_phy_apb_reset_n_t; 13643 13644 static inline uint64_t ODY_DSSX_PHY_APB_RESET_N(uint64_t a) __attribute__ ((pure, always_inline)); 13645 static inline uint64_t ODY_DSSX_PHY_APB_RESET_N(uint64_t a) 13646 { 13647 if (a <= 19) 13648 return 0x87e1b0000018ll + 0x1000000ll * ((a) & 0x1f); 13649 __ody_csr_fatal("DSSX_PHY_APB_RESET_N", 1, a, 0, 0, 0, 0, 0); 13650 } 13651 13652 #define typedef_ODY_DSSX_PHY_APB_RESET_N(a) ody_dssx_phy_apb_reset_n_t 13653 #define bustype_ODY_DSSX_PHY_APB_RESET_N(a) CSR_TYPE_RSL 13654 #define basename_ODY_DSSX_PHY_APB_RESET_N(a) "DSSX_PHY_APB_RESET_N" 13655 #define device_bar_ODY_DSSX_PHY_APB_RESET_N(a) 0x0 /* PF_BAR0 */ 13656 #define busnum_ODY_DSSX_PHY_APB_RESET_N(a) (a) 13657 #define arguments_ODY_DSSX_PHY_APB_RESET_N(a) (a), -1, -1, -1 13658 13659 /** 13660 * Register (RSL) dss#_phy_ctrl 13661 * 13662 * DSS PHY Control Register 13663 * PHY control register. 13664 */ 13665 union ody_dssx_phy_ctrl { 13666 uint64_t u; 13667 struct ody_dssx_phy_ctrl_s { 13668 uint64_t s_phy_pprot : 3; 13669 uint64_t s_phy_pwrok : 1; 13670 uint64_t s_phy_mdc_dis : 1; 13671 uint64_t s_dual_channel_en : 1; 13672 uint64_t reserved_6_63 : 58; 13673 } s; 13674 /* struct ody_dssx_phy_ctrl_s cn; */ 13675 }; 13676 typedef union ody_dssx_phy_ctrl ody_dssx_phy_ctrl_t; 13677 13678 static inline uint64_t ODY_DSSX_PHY_CTRL(uint64_t a) __attribute__ ((pure, always_inline)); 13679 static inline uint64_t ODY_DSSX_PHY_CTRL(uint64_t a) 13680 { 13681 if (a <= 19) 13682 return 0x87e1b0000040ll + 0x1000000ll * ((a) & 0x1f); 13683 __ody_csr_fatal("DSSX_PHY_CTRL", 1, a, 0, 0, 0, 0, 0); 13684 } 13685 13686 #define typedef_ODY_DSSX_PHY_CTRL(a) ody_dssx_phy_ctrl_t 13687 #define bustype_ODY_DSSX_PHY_CTRL(a) CSR_TYPE_RSL 13688 #define basename_ODY_DSSX_PHY_CTRL(a) "DSSX_PHY_CTRL" 13689 #define device_bar_ODY_DSSX_PHY_CTRL(a) 0x0 /* PF_BAR0 */ 13690 #define busnum_ODY_DSSX_PHY_CTRL(a) (a) 13691 #define arguments_ODY_DSSX_PHY_CTRL(a) (a), -1, -1, -1 13692 13693 /** 13694 * Register (RSL) dss#_phy_ref_reset_n 13695 * 13696 * DSS PHY Domain Reset Register 13697 * PHY clock software reset - active low. 13698 */ 13699 union ody_dssx_phy_ref_reset_n { 13700 uint64_t u; 13701 struct ody_dssx_phy_ref_reset_n_s { 13702 uint64_t s_phy_ref_reset_n : 1; 13703 uint64_t reserved_1_63 : 63; 13704 } s; 13705 /* struct ody_dssx_phy_ref_reset_n_s cn; */ 13706 }; 13707 typedef union ody_dssx_phy_ref_reset_n ody_dssx_phy_ref_reset_n_t; 13708 13709 static inline uint64_t ODY_DSSX_PHY_REF_RESET_N(uint64_t a) __attribute__ ((pure, always_inline)); 13710 static inline uint64_t ODY_DSSX_PHY_REF_RESET_N(uint64_t a) 13711 { 13712 if (a <= 19) 13713 return 0x87e1b0000008ll + 0x1000000ll * ((a) & 0x1f); 13714 __ody_csr_fatal("DSSX_PHY_REF_RESET_N", 1, a, 0, 0, 0, 0, 0); 13715 } 13716 13717 #define typedef_ODY_DSSX_PHY_REF_RESET_N(a) ody_dssx_phy_ref_reset_n_t 13718 #define bustype_ODY_DSSX_PHY_REF_RESET_N(a) CSR_TYPE_RSL 13719 #define basename_ODY_DSSX_PHY_REF_RESET_N(a) "DSSX_PHY_REF_RESET_N" 13720 #define device_bar_ODY_DSSX_PHY_REF_RESET_N(a) 0x0 /* PF_BAR0 */ 13721 #define busnum_ODY_DSSX_PHY_REF_RESET_N(a) (a) 13722 #define arguments_ODY_DSSX_PHY_REF_RESET_N(a) (a), -1, -1, -1 13723 13724 /** 13725 * Register (RSL) dss#_rsl_ddrctl_permit 13726 * 13727 * DSS RSL Bus Permit to DDRCTL Register 13728 * This register sets the permissions for access to the DDRCTL addresses. 13729 * DDRCTL MPAM addresses are exluded from this register. 13730 */ 13731 union ody_dssx_rsl_ddrctl_permit { 13732 uint64_t u; 13733 struct ody_dssx_rsl_ddrctl_permit_s { 13734 uint64_t sec_dis : 1; 13735 uint64_t nsec_dis : 1; 13736 uint64_t xcp0_dis : 1; 13737 uint64_t xcp1_dis : 1; 13738 uint64_t xcp2_dis : 1; 13739 uint64_t reserved_5_7 : 3; 13740 uint64_t lock : 1; 13741 uint64_t reserved_9_63 : 55; 13742 } s; 13743 /* struct ody_dssx_rsl_ddrctl_permit_s cn; */ 13744 }; 13745 typedef union ody_dssx_rsl_ddrctl_permit ody_dssx_rsl_ddrctl_permit_t; 13746 13747 static inline uint64_t ODY_DSSX_RSL_DDRCTL_PERMIT(uint64_t a) __attribute__ ((pure, always_inline)); 13748 static inline uint64_t ODY_DSSX_RSL_DDRCTL_PERMIT(uint64_t a) 13749 { 13750 if (a <= 19) 13751 return 0x87e1b0000208ll + 0x1000000ll * ((a) & 0x1f); 13752 __ody_csr_fatal("DSSX_RSL_DDRCTL_PERMIT", 1, a, 0, 0, 0, 0, 0); 13753 } 13754 13755 #define typedef_ODY_DSSX_RSL_DDRCTL_PERMIT(a) ody_dssx_rsl_ddrctl_permit_t 13756 #define bustype_ODY_DSSX_RSL_DDRCTL_PERMIT(a) CSR_TYPE_RSL 13757 #define basename_ODY_DSSX_RSL_DDRCTL_PERMIT(a) "DSSX_RSL_DDRCTL_PERMIT" 13758 #define device_bar_ODY_DSSX_RSL_DDRCTL_PERMIT(a) 0x0 /* PF_BAR0 */ 13759 #define busnum_ODY_DSSX_RSL_DDRCTL_PERMIT(a) (a) 13760 #define arguments_ODY_DSSX_RSL_DDRCTL_PERMIT(a) (a), -1, -1, -1 13761 13762 /** 13763 * Register (RSL) dss#_rsl_mct_permit 13764 * 13765 * DSS RSL Bus Permit to MCT Register 13766 * This register sets the permissions for access to the MCT addresses. 13767 */ 13768 union ody_dssx_rsl_mct_permit { 13769 uint64_t u; 13770 struct ody_dssx_rsl_mct_permit_s { 13771 uint64_t sec_dis : 1; 13772 uint64_t nsec_dis : 1; 13773 uint64_t xcp0_dis : 1; 13774 uint64_t xcp1_dis : 1; 13775 uint64_t xcp2_dis : 1; 13776 uint64_t reserved_5_7 : 3; 13777 uint64_t lock : 1; 13778 uint64_t reserved_9_63 : 55; 13779 } s; 13780 /* struct ody_dssx_rsl_mct_permit_s cn; */ 13781 }; 13782 typedef union ody_dssx_rsl_mct_permit ody_dssx_rsl_mct_permit_t; 13783 13784 static inline uint64_t ODY_DSSX_RSL_MCT_PERMIT(uint64_t a) __attribute__ ((pure, always_inline)); 13785 static inline uint64_t ODY_DSSX_RSL_MCT_PERMIT(uint64_t a) 13786 { 13787 if (a <= 19) 13788 return 0x87e1b0000200ll + 0x1000000ll * ((a) & 0x1f); 13789 __ody_csr_fatal("DSSX_RSL_MCT_PERMIT", 1, a, 0, 0, 0, 0, 0); 13790 } 13791 13792 #define typedef_ODY_DSSX_RSL_MCT_PERMIT(a) ody_dssx_rsl_mct_permit_t 13793 #define bustype_ODY_DSSX_RSL_MCT_PERMIT(a) CSR_TYPE_RSL 13794 #define basename_ODY_DSSX_RSL_MCT_PERMIT(a) "DSSX_RSL_MCT_PERMIT" 13795 #define device_bar_ODY_DSSX_RSL_MCT_PERMIT(a) 0x0 /* PF_BAR0 */ 13796 #define busnum_ODY_DSSX_RSL_MCT_PERMIT(a) (a) 13797 #define arguments_ODY_DSSX_RSL_MCT_PERMIT(a) (a), -1, -1, -1 13798 13799 /** 13800 * Register (RSL) dss#_top_global_clock_enable 13801 * 13802 * DSS TOP Global Clock Enable Register 13803 * Force DSS_TOP sub-block coarse clock to be always on. 13804 */ 13805 union ody_dssx_top_global_clock_enable { 13806 uint64_t u; 13807 struct ody_dssx_top_global_clock_enable_s { 13808 uint64_t coarse_clk_force : 1; 13809 uint64_t reserved_1_63 : 63; 13810 } s; 13811 /* struct ody_dssx_top_global_clock_enable_s cn; */ 13812 }; 13813 typedef union ody_dssx_top_global_clock_enable ody_dssx_top_global_clock_enable_t; 13814 13815 static inline uint64_t ODY_DSSX_TOP_GLOBAL_CLOCK_ENABLE(uint64_t a) __attribute__ ((pure, always_inline)); 13816 static inline uint64_t ODY_DSSX_TOP_GLOBAL_CLOCK_ENABLE(uint64_t a) 13817 { 13818 if (a <= 19) 13819 return 0x87e1b0000108ll + 0x1000000ll * ((a) & 0x1f); 13820 __ody_csr_fatal("DSSX_TOP_GLOBAL_CLOCK_ENABLE", 1, a, 0, 0, 0, 0, 0); 13821 } 13822 13823 #define typedef_ODY_DSSX_TOP_GLOBAL_CLOCK_ENABLE(a) ody_dssx_top_global_clock_enable_t 13824 #define bustype_ODY_DSSX_TOP_GLOBAL_CLOCK_ENABLE(a) CSR_TYPE_RSL 13825 #define basename_ODY_DSSX_TOP_GLOBAL_CLOCK_ENABLE(a) "DSSX_TOP_GLOBAL_CLOCK_ENABLE" 13826 #define device_bar_ODY_DSSX_TOP_GLOBAL_CLOCK_ENABLE(a) 0x0 /* PF_BAR0 */ 13827 #define busnum_ODY_DSSX_TOP_GLOBAL_CLOCK_ENABLE(a) (a) 13828 #define arguments_ODY_DSSX_TOP_GLOBAL_CLOCK_ENABLE(a) (a), -1, -1, -1 13829 13830 /** 13831 * Register (RSL) dss#_txrsp_fill_lvl_cnt_cfg 13832 * 13833 * DSS Performance Counters Accumulative Occupancy Level Configuration Of TxRSP Flitq Register 13834 * Configuration register of internal memory controller CHB link layer TxRsp flitq 13835 * queue's current fill level counter. 13836 */ 13837 union ody_dssx_txrsp_fill_lvl_cnt_cfg { 13838 uint64_t u; 13839 struct ody_dssx_txrsp_fill_lvl_cnt_cfg_s { 13840 uint64_t cnt_en : 1; 13841 uint64_t wrap_value : 1; 13842 uint64_t interrupt_en : 1; 13843 uint64_t reserved_3_63 : 61; 13844 } s; 13845 /* struct ody_dssx_txrsp_fill_lvl_cnt_cfg_s cn; */ 13846 }; 13847 typedef union ody_dssx_txrsp_fill_lvl_cnt_cfg ody_dssx_txrsp_fill_lvl_cnt_cfg_t; 13848 13849 static inline uint64_t ODY_DSSX_TXRSP_FILL_LVL_CNT_CFG(uint64_t a) __attribute__ ((pure, always_inline)); 13850 static inline uint64_t ODY_DSSX_TXRSP_FILL_LVL_CNT_CFG(uint64_t a) 13851 { 13852 if (a <= 19) 13853 return 0x87e1b00084d8ll + 0x1000000ll * ((a) & 0x1f); 13854 __ody_csr_fatal("DSSX_TXRSP_FILL_LVL_CNT_CFG", 1, a, 0, 0, 0, 0, 0); 13855 } 13856 13857 #define typedef_ODY_DSSX_TXRSP_FILL_LVL_CNT_CFG(a) ody_dssx_txrsp_fill_lvl_cnt_cfg_t 13858 #define bustype_ODY_DSSX_TXRSP_FILL_LVL_CNT_CFG(a) CSR_TYPE_RSL 13859 #define basename_ODY_DSSX_TXRSP_FILL_LVL_CNT_CFG(a) "DSSX_TXRSP_FILL_LVL_CNT_CFG" 13860 #define device_bar_ODY_DSSX_TXRSP_FILL_LVL_CNT_CFG(a) 0x0 /* PF_BAR0 */ 13861 #define busnum_ODY_DSSX_TXRSP_FILL_LVL_CNT_CFG(a) (a) 13862 #define arguments_ODY_DSSX_TXRSP_FILL_LVL_CNT_CFG(a) (a), -1, -1, -1 13863 13864 /** 13865 * Register (RSL) dss#_txrsp_fill_lvl_cnt_val 13866 * 13867 * Performance Counters Fill Level Value Register 13868 * Count of Accumulative occupancy level in memory controller internal TxRSP Flitq queue. 13869 */ 13870 union ody_dssx_txrsp_fill_lvl_cnt_val { 13871 uint64_t u; 13872 struct ody_dssx_txrsp_fill_lvl_cnt_val_s { 13873 uint64_t counter_value : 64; 13874 } s; 13875 /* struct ody_dssx_txrsp_fill_lvl_cnt_val_s cn; */ 13876 }; 13877 typedef union ody_dssx_txrsp_fill_lvl_cnt_val ody_dssx_txrsp_fill_lvl_cnt_val_t; 13878 13879 static inline uint64_t ODY_DSSX_TXRSP_FILL_LVL_CNT_VAL(uint64_t a) __attribute__ ((pure, always_inline)); 13880 static inline uint64_t ODY_DSSX_TXRSP_FILL_LVL_CNT_VAL(uint64_t a) 13881 { 13882 if (a <= 19) 13883 return 0x87e1b00085c0ll + 0x1000000ll * ((a) & 0x1f); 13884 __ody_csr_fatal("DSSX_TXRSP_FILL_LVL_CNT_VAL", 1, a, 0, 0, 0, 0, 0); 13885 } 13886 13887 #define typedef_ODY_DSSX_TXRSP_FILL_LVL_CNT_VAL(a) ody_dssx_txrsp_fill_lvl_cnt_val_t 13888 #define bustype_ODY_DSSX_TXRSP_FILL_LVL_CNT_VAL(a) CSR_TYPE_RSL 13889 #define basename_ODY_DSSX_TXRSP_FILL_LVL_CNT_VAL(a) "DSSX_TXRSP_FILL_LVL_CNT_VAL" 13890 #define device_bar_ODY_DSSX_TXRSP_FILL_LVL_CNT_VAL(a) 0x0 /* PF_BAR0 */ 13891 #define busnum_ODY_DSSX_TXRSP_FILL_LVL_CNT_VAL(a) (a) 13892 #define arguments_ODY_DSSX_TXRSP_FILL_LVL_CNT_VAL(a) (a), -1, -1, -1 13893 13894 /** 13895 * Register (RSL) dss#_txrsp_filllvl_cnt_ovrflw 13896 * 13897 * Performance Counters TxRSP Fill Level overflow indication Register 13898 * This register indicates if TxRSP Flitq fill level counter overflowed. 13899 */ 13900 union ody_dssx_txrsp_filllvl_cnt_ovrflw { 13901 uint64_t u; 13902 struct ody_dssx_txrsp_filllvl_cnt_ovrflw_s { 13903 uint64_t counter_overflow : 1; 13904 uint64_t reserved_1_63 : 63; 13905 } s; 13906 /* struct ody_dssx_txrsp_filllvl_cnt_ovrflw_s cn; */ 13907 }; 13908 typedef union ody_dssx_txrsp_filllvl_cnt_ovrflw ody_dssx_txrsp_filllvl_cnt_ovrflw_t; 13909 13910 static inline uint64_t ODY_DSSX_TXRSP_FILLLVL_CNT_OVRFLW(uint64_t a) __attribute__ ((pure, always_inline)); 13911 static inline uint64_t ODY_DSSX_TXRSP_FILLLVL_CNT_OVRFLW(uint64_t a) 13912 { 13913 if (a <= 19) 13914 return 0x87e1b00086c0ll + 0x1000000ll * ((a) & 0x1f); 13915 __ody_csr_fatal("DSSX_TXRSP_FILLLVL_CNT_OVRFLW", 1, a, 0, 0, 0, 0, 0); 13916 } 13917 13918 #define typedef_ODY_DSSX_TXRSP_FILLLVL_CNT_OVRFLW(a) ody_dssx_txrsp_filllvl_cnt_ovrflw_t 13919 #define bustype_ODY_DSSX_TXRSP_FILLLVL_CNT_OVRFLW(a) CSR_TYPE_RSL 13920 #define basename_ODY_DSSX_TXRSP_FILLLVL_CNT_OVRFLW(a) "DSSX_TXRSP_FILLLVL_CNT_OVRFLW" 13921 #define device_bar_ODY_DSSX_TXRSP_FILLLVL_CNT_OVRFLW(a) 0x0 /* PF_BAR0 */ 13922 #define busnum_ODY_DSSX_TXRSP_FILLLVL_CNT_OVRFLW(a) (a) 13923 #define arguments_ODY_DSSX_TXRSP_FILLLVL_CNT_OVRFLW(a) (a), -1, -1, -1 13924 13925 #endif /* __ODY_CSRS_DSS_H__ */ 13926