chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
e

chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
expectation so that future platform implementers don't get misled.

Change-Id: Ic33f0b6da74592ad6778fd802c2f0b85223af614
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(stm32mp2): correct early/crash console init

The previous code used 64-bit registers as the target and source for
load and store operations on 32-bit hardware registers. In certain
cases (e.g., w

fix(stm32mp2): correct early/crash console init

The previous code used 64-bit registers as the target and source for
load and store operations on 32-bit hardware registers. In certain
cases (e.g., when using USART1 as the debug console), this could result
in deadlocks where the A35 gets stuck in a permanent loop due to test
conditions that are never fulfilled.

To resolve this issue, 32-bit registers are now used for these
operations.

Change-Id: Id2c03a1df26738fe815079da042cc2dd989f4f8e
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>

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Merge "feat(stm32mp2): add FWU support" into integration

feat(stm32mp2): add a runtime service for STGEN configuration

Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Th

feat(stm32mp2): add a runtime service for STGEN configuration

Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Therefore, implement a SiP SMC handler for this purpose and
a runtime service to catch SIP SMCs.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I7854e1ae6328f149798b43d52bb1ecdf71a5aa69

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feat(stm32mp2): add common SMC runtime services

Implement the common SMC runtime services for stm32mp2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Max

feat(stm32mp2): add common SMC runtime services

Implement the common SMC runtime services for stm32mp2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I214e4b2bfba439572c079bbc9ffb62bc87793ce9

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feat(stm32mp2): add FWU support

Add stm32_get_bkpr_fwu_info_addr() function.
Call stm32_fwu_set_boot_idx() in bl2_plat_handle_post_image_load().

Signed-off-by: Yann Gautier <yann.gautier@foss.st.co

feat(stm32mp2): add FWU support

Add stm32_get_bkpr_fwu_info_addr() function.
Call stm32_fwu_set_boot_idx() in bl2_plat_handle_post_image_load().

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ieb57dffa4ce784d1ed61b401dc17376fe745c111

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build: disable suffix rules globally

This change centralises the logic that disables the default suffix rules
that Make provides. These rules are a hold-over from legacy standards of
Make, and occas

build: disable suffix rules globally

This change centralises the logic that disables the default suffix rules
that Make provides. These rules are a hold-over from legacy standards of
Make, and occasionally conflict with our rules.

Change-Id: I9e023edbc01b5ae48a96fa1078d0b81faabb0cb9
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(stm32mp2): use TOOL_ADD_IMG_PAYLOAD for BL31 DT" into integration

fix(stm32mp2): use TOOL_ADD_IMG_PAYLOAD for BL31 DT

Use TOOL_ADD_IMG_PAYLOAD instead of TOOL_ADD_IMG to generate the BL31
device tree blob to be included in FIP. This allows building all TF-A
binari

fix(stm32mp2): use TOOL_ADD_IMG_PAYLOAD for BL31 DT

Use TOOL_ADD_IMG_PAYLOAD instead of TOOL_ADD_IMG to generate the BL31
device tree blob to be included in FIP. This allows building all TF-A
binaries and FIP in a single command. Else, as TOOL_ADD_IMG evaluate
the existence of the file before building it, we have a build error.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I72d2f70733c49792d0321ad07f5a3bbd283a36d4

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fix(stm32mp2): enable timer earlier in BL31

The timer is required when setting console. In BL2 the timer init is
done in clock driver init. This is not the case in BL31. So initialize
the generic_de

fix(stm32mp2): enable timer earlier in BL31

The timer is required when setting console. In BL2 the timer init is
done in clock driver init. This is not the case in BL31. So initialize
the generic_delay_timer_init() just after stm32mp2_clk_init() call.
This is required after the recent changes in timer framework [1].

[1]: a6485b2b3b refactor(delay-timer): add timer callback functions

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4e84a45fc526ed132e97b238596aa69ddfc2b058

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fix(stm32mp2): set PLAT_MAX_PWR_LVL to one

Set maximum power level to 1 as power management isn't implemented yet.

Change-Id: I26cefbb5e199944d371bf06a76b2c41f73d38585
Signed-off-by: Maxime Méré <m

fix(stm32mp2): set PLAT_MAX_PWR_LVL to one

Set maximum power level to 1 as power management isn't implemented yet.

Change-Id: I26cefbb5e199944d371bf06a76b2c41f73d38585
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp2): boot BL33 at EL1 or EL2

STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_U

feat(stm32mp2): boot BL33 at EL1 or EL2

STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_UNUSED_NS_EL2 defined to Iiitialize the unused EL2
registers.

Change BL33 spsr parameter in bl2_mem_params_descs[] to use MODE_EL2
or MODE_EL1 depending on this flag. Default to MODE_EL1 as kernel
isn't able to boot at EL2 yet.

Change-Id: I6a8b35280d454d8140d7b28f0a5fc9b9a5093d6d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>

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feat(stm32mp2): disable unsupported features

SPE and SVE for non-secure world are not supported on Arm v8.0.
Disable the corresponding flags. This also saves a bit of memory.

Change-Id: I323fb74103

feat(stm32mp2): disable unsupported features

SPE and SVE for non-secure world are not supported on Arm v8.0.
Disable the corresponding flags. This also saves a bit of memory.

Change-Id: I323fb7410393ea9711759be4c47848316fb68860
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(stm32mp2): initialize gic and delay timer in bl31_plat_arch_setup

For minimal BL31 setup, GIC and tick must be initialized.

Change-Id: I8d62253e93b77cd8ce8091ccc9ea88208bdd6053
Signed-off-by:

feat(stm32mp2): initialize gic and delay timer in bl31_plat_arch_setup

For minimal BL31 setup, GIC and tick must be initialized.

Change-Id: I8d62253e93b77cd8ce8091ccc9ea88208bdd6053
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp2): add BL31 device tree support

BL31 will need to access a device tree for several configurations (UART,
GIC, OTP mapping...).
Create a BL31 device tree (SOC_FW_CONFIG). It is loaded in

feat(stm32mp2): add BL31 device tree support

BL31 will need to access a device tree for several configurations (UART,
GIC, OTP mapping...).
Create a BL31 device tree (SOC_FW_CONFIG). It is loaded in DDR, in a
spare area.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I320a05859e1aa3dd8db9a274e7201075a8c250c2

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feat(stm32mp2): load FW binaries to DDR

Now that DDR is initialized, we can load the different firmware
parts: BL32 (OP-TEE header), BL32 extra1 (OP-TEE), HW_CONFIG (U-Boot
device tree) and BL33 (U

feat(stm32mp2): load FW binaries to DDR

Now that DDR is initialized, we can load the different firmware
parts: BL32 (OP-TEE header), BL32 extra1 (OP-TEE), HW_CONFIG (U-Boot
device tree) and BL33 (U-Boot).

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic79429c3bd4516c339f91a10e0b3f2828bf6c392

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feat(stm32mp2): enable DDR driver

Call stm32mp2_ddr_probe() function in platform setup.
Move DDR systematic test file in common.mk.

Change-Id: I982abd33635a3222a52c967eac64676bc26b0d6b
Signed-off-b

feat(stm32mp2): enable DDR driver

Call stm32mp2_ddr_probe() function in platform setup.
Move DDR systematic test file in common.mk.

Change-Id: I982abd33635a3222a52c967eac64676bc26b0d6b
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(st-ddr): add STM32MP2 driver

Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY
and its firmware, as well as the DDR controller.

Signed-off-by: Nicolas Le Bayon <nicolas.le.

feat(st-ddr): add STM32MP2 driver

Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY
and its firmware, as well as the DDR controller.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5

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feat(st): add stm32mp_is_wakeup_from_standby()

This function is used to know if this is a return from Standby mode,
and the DDR was in self-refresh, allowing a correct return to OS.
They just return

feat(st): add stm32mp_is_wakeup_from_standby()

This function is used to know if this is a return from Standby mode,
and the DDR was in self-refresh, allowing a correct return to OS.
They just return false for the moment.

Change-Id: Ie7de9a9f6477f8158e144f6626070a77fdc53ceb
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp2): add RETRAM map/unmap capability

Add RETRAM base address and size definition at platform level.
RETRAM is used by the DDR driver to store retention registers (DDR
training results) in

feat(stm32mp2): add RETRAM map/unmap capability

Add RETRAM base address and size definition at platform level.
RETRAM is used by the DDR driver to store retention registers (DDR
training results) in order to restore them in standby exit sequence.
Add map/unmap services at platform level and configure dedicated RISAB5.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I460b36fccce62e83c1fbff298f96b23530aaa4f3

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feat(stm32mp2): add helper to get DDRDBG base address

Add a function to get DDRDBG peripheral IO memory base address.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I20d14fca4

feat(stm32mp2): add helper to get DDRDBG base address

Add a function to get DDRDBG peripheral IO memory base address.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I20d14fca49528c296c1f7d49a66129d932f44e49

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feat(stm32mp2): handle DDR power supplies

Modify platform driver to handle the DDR power supplies when
a PMIC is present.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I98df132a63c2ad

feat(stm32mp2): handle DDR power supplies

Modify platform driver to handle the DDR power supplies when
a PMIC is present.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I98df132a63c2ad351d4dae949f5dbb831cc40637

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Merge changes I14df5d21,I7f952205,I6f52ec2c,Ibe0cacf8 into integration

* changes:
feat(stm32mp2-fdts): describe stpmic2 power supplies
feat(stm32mp2-fdts): add I2C7 pin muxing
feat(stm32mp2-fd

Merge changes I14df5d21,I7f952205,I6f52ec2c,Ibe0cacf8 into integration

* changes:
feat(stm32mp2-fdts): describe stpmic2 power supplies
feat(stm32mp2-fdts): add I2C7 pin muxing
feat(stm32mp2-fdts): add UART and I2C nodes for STM32MP2
feat(st-pmic): add STPMIC2 driver

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feat(stm32mp2): improve BL31 size management

Change the size of BL31 limit allocation to be half the sysram size.
Defining BL31_PROGBITS_LIMIT to detect overflows.

Signed-off-by: Maxime Méré <maxim

feat(stm32mp2): improve BL31 size management

Change the size of BL31 limit allocation to be half the sysram size.
Defining BL31_PROGBITS_LIMIT to detect overflows.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iccc1cc0826b8113a3c2fd6ffa77ca419795854d3

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feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boo

feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boot of a board.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ibe0cacf8aec2871eb9a86ec16cbbd18d3745fe9e

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