xref: /rk3399_ARM-atf/plat/st/stm32mp2/bl2_plat_setup.c (revision 213a08eb422a69bc7c95579fadf076f5af152f49) 
1 /*
2  * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <cdefs.h>
9 #include <errno.h>
10 #include <stdint.h>
11 
12 #include <common/debug.h>
13 #include <common/desc_image_load.h>
14 #include <drivers/clk.h>
15 #include <drivers/mmc.h>
16 #include <drivers/st/regulator_fixed.h>
17 #include <drivers/st/stm32mp2_ddr_helpers.h>
18 #include <drivers/st/stm32mp2_ram.h>
19 #include <drivers/st/stm32mp_pmic2.h>
20 #include <drivers/st/stm32mp_risab_regs.h>
21 #include <lib/fconf/fconf.h>
22 #include <lib/fconf/fconf_dyn_cfg_getter.h>
23 #include <lib/mmio.h>
24 #include <lib/xlat_tables/xlat_tables_v2.h>
25 #include <plat/common/platform.h>
26 
27 #include <platform_def.h>
28 #include <stm32mp_common.h>
29 #include <stm32mp_dt.h>
30 
31 #define BOOT_CTX_ADDR	0x0e000020UL
32 
33 static void print_reset_reason(void)
34 {
35 	uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
36 
37 	if (rstsr == 0U) {
38 		WARN("Reset reason unknown\n");
39 		return;
40 	}
41 
42 	INFO("Reset reason (0x%x):\n", rstsr);
43 
44 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
45 		if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
46 			INFO("System exits from Standby for CA35\n");
47 			return;
48 		}
49 
50 		if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
51 			INFO("D1 domain exits from DStandby\n");
52 			return;
53 		}
54 	}
55 
56 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
57 		INFO("  Power-on Reset (rst_por)\n");
58 		return;
59 	}
60 
61 	if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
62 		INFO("  Brownout Reset (rst_bor)\n");
63 		return;
64 	}
65 
66 	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
67 		INFO("  System reset (SYSRST) by M33\n");
68 		return;
69 	}
70 
71 	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
72 		INFO("  System reset (SYSRST) by A35\n");
73 		return;
74 	}
75 
76 	if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
77 		INFO("  Clock failure on HSE\n");
78 		return;
79 	}
80 
81 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
82 		INFO("  IWDG1 system reset (rst_iwdg1)\n");
83 		return;
84 	}
85 
86 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
87 		INFO("  IWDG2 system reset (rst_iwdg2)\n");
88 		return;
89 	}
90 
91 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
92 		INFO("  IWDG3 system reset (rst_iwdg3)\n");
93 		return;
94 	}
95 
96 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
97 		INFO("  IWDG4 system reset (rst_iwdg4)\n");
98 		return;
99 	}
100 
101 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
102 		INFO("  IWDG5 system reset (rst_iwdg5)\n");
103 		return;
104 	}
105 
106 	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
107 		INFO("  A35 processor core 1 reset\n");
108 		return;
109 	}
110 
111 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
112 		INFO("  Pad Reset from NRST\n");
113 		return;
114 	}
115 
116 	if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
117 		INFO("  Reset due to a failure of VDD_CORE\n");
118 		return;
119 	}
120 
121 	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
122 		INFO("  A35 processor reset\n");
123 		return;
124 	}
125 
126 	ERROR("  Unidentified reset reason\n");
127 }
128 
129 void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
130 				  u_register_t arg1 __unused,
131 				  u_register_t arg2 __unused,
132 				  u_register_t arg3 __unused)
133 {
134 	stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR);
135 }
136 
137 void bl2_platform_setup(void)
138 {
139 	int ret;
140 
141 	ret = stm32mp2_ddr_probe();
142 	if (ret != 0) {
143 		ERROR("DDR probe: error %d\n", ret);
144 		panic();
145 	}
146 }
147 
148 static void reset_backup_domain(void)
149 {
150 	uintptr_t pwr_base = stm32mp_pwr_base();
151 	uintptr_t rcc_base = stm32mp_rcc_base();
152 
153 	/*
154 	 * Disable the backup domain write protection.
155 	 * The protection is enable at each reset by hardware
156 	 * and must be disabled by software.
157 	 */
158 	mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
159 
160 	while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
161 		;
162 	}
163 
164 	/* Reset backup domain on cold boot cases */
165 	if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {
166 		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
167 
168 		while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) {
169 			;
170 		}
171 
172 		mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
173 	}
174 }
175 
176 void bl2_el3_plat_arch_setup(void)
177 {
178 	const char *board_model;
179 	boot_api_context_t *boot_context =
180 		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
181 
182 	if (stm32_otp_probe() != 0U) {
183 		EARLY_ERROR("OTP probe failed\n");
184 		panic();
185 	}
186 
187 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
188 			BL_CODE_END - BL_CODE_BASE,
189 			MT_CODE | MT_SECURE);
190 
191 	configure_mmu();
192 
193 	if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
194 		panic();
195 	}
196 
197 	reset_backup_domain();
198 
199 	/*
200 	 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2),
201 	 * and so before stm32mp2_clk_init().
202 	 */
203 	ddr_sub_system_clk_init();
204 
205 	if (stm32mp2_clk_init() < 0) {
206 		panic();
207 	}
208 
209 #if STM32MP_DDR_FIP_IO_STORAGE
210 	/*
211 	 * RISAB3 setup (dedicated for SRAM1)
212 	 *
213 	 * Allow secure read/writes data accesses to non-secure
214 	 * blocks or pages, all RISAB registers are writable.
215 	 * DDR firmwares are saved there before being loaded in DDRPHY memory.
216 	 */
217 	mmio_write_32(RISAB3_BASE + RISAB_CR, RISAB_CR_SRWIAD);
218 #endif
219 
220 	stm32_save_boot_info(boot_context);
221 
222 	if (stm32mp_uart_console_setup() != 0) {
223 		goto skip_console_init;
224 	}
225 
226 	stm32mp_print_cpuinfo();
227 
228 	board_model = dt_get_board_model();
229 	if (board_model != NULL) {
230 		NOTICE("Model: %s\n", board_model);
231 	}
232 
233 	stm32mp_print_boardinfo();
234 
235 	print_reset_reason();
236 
237 skip_console_init:
238 	if (fixed_regulator_register() != 0) {
239 		panic();
240 	}
241 
242 	if (dt_pmic_status() > 0) {
243 		initialize_pmic();
244 	}
245 
246 	fconf_populate("TB_FW", STM32MP_DTB_BASE);
247 
248 	/*
249 	 * RISAB5 setup (dedicated for RETRAM)
250 	 *
251 	 * Allow secure read/writes data accesses to non-secure
252 	 * blocks or pages, all RISAB registers are writable.
253 	 * DDR retention registers are saved there and restored
254 	 * when exiting standby low power state.
255 	 */
256 	mmio_write_32(RISAB5_BASE + RISAB_CR, RISAB_CR_SRWIAD);
257 
258 	stm32mp_io_setup();
259 }
260 
261 /*******************************************************************************
262  * This function can be used by the platforms to update/use image
263  * information for given `image_id`.
264  ******************************************************************************/
265 int bl2_plat_handle_post_image_load(unsigned int image_id)
266 {
267 	int err = 0;
268 	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
269 	const struct dyn_cfg_dtb_info_t *config_info;
270 	unsigned int i;
271 	const unsigned int image_ids[] = {
272 		BL31_IMAGE_ID,
273 	};
274 
275 	assert(bl_mem_params != NULL);
276 
277 #if STM32MP_SDMMC || STM32MP_EMMC
278 	/*
279 	 * Invalidate remaining data read from MMC but not flushed by load_image_flush().
280 	 * We take the worst case which is 2 MMC blocks.
281 	 */
282 	if ((image_id != FW_CONFIG_ID) &&
283 	    ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
284 		inv_dcache_range(bl_mem_params->image_info.image_base +
285 				 bl_mem_params->image_info.image_size,
286 				 2U * MMC_BLOCK_SIZE);
287 	}
288 #endif /* STM32MP_SDMMC || STM32MP_EMMC */
289 
290 	switch (image_id) {
291 	case FW_CONFIG_ID:
292 		/* Set global DTB info for fixed fw_config information */
293 		set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
294 				FW_CONFIG_ID);
295 		fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
296 
297 		/* Iterate through all the fw config IDs */
298 		for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
299 			bl_mem_params = get_bl_mem_params_node(image_ids[i]);
300 			assert(bl_mem_params != NULL);
301 
302 			config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
303 			if (config_info == NULL) {
304 				continue;
305 			}
306 
307 			bl_mem_params->image_info.image_base = config_info->config_addr;
308 			bl_mem_params->image_info.image_max_size = config_info->config_max_size;
309 
310 			bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
311 
312 			switch (image_ids[i]) {
313 			case BL31_IMAGE_ID:
314 				bl_mem_params->ep_info.pc = config_info->config_addr;
315 				break;
316 			default:
317 				return -EINVAL;
318 			}
319 		}
320 
321 		/*
322 		 * After this step, the BL2 device tree area will be overwritten
323 		 * with BL31 binary, no other data should be read from BL2 DT.
324 		 */
325 
326 		break;
327 
328 	default:
329 		/* Do nothing in default case */
330 		break;
331 	}
332 
333 	return err;
334 }
335