fix(stm32mp2): remove unused macro PLAT_NB_GPIO_REGUS

The macro PLAT_NB_GPIO_REGUS is not used, remove it.

Change-Id: I4303545ee92be95cd7040a20dfe79d417dc07be4
Signed-off-by: Yann Gautier <yann.gau

fix(stm32mp2): remove unused macro PLAT_NB_GPIO_REGUS

The macro PLAT_NB_GPIO_REGUS is not used, remove it.

Change-Id: I4303545ee92be95cd7040a20dfe79d417dc07be4
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(stm32mp2): correct ORR instruction in plat_crash_console_init

For some cases, the value (DEBUG_UART_TX_GPIO_ALTERNATE <<
((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) cannot fit the
p

fix(stm32mp2): correct ORR instruction in plat_crash_console_init

For some cases, the value (DEBUG_UART_TX_GPIO_ALTERNATE <<
((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) cannot fit the
pattern for immediate value for ORR instruction.
Use a temporary register, filled with mov_imm macro.
While at it change the other ORR or BIC instructions that could have the
same issue.

Change-Id: If4434b910463af7d55b9e4ea6562a67e606b02bb
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp2): add a new stm32mp21 power compatible

Introduce new compatible st,stm32mp21-pwr. It is based st,stm32mp25-pwr but
without vddio4.

Signed-off-by: Valentin Caron <valentin.caron@foss.s

feat(stm32mp2): add a new stm32mp21 power compatible

Introduce new compatible st,stm32mp21-pwr. It is based st,stm32mp25-pwr but
without vddio4.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Change-Id: Ibf22bec75aa310eb0f3d1e1f3fc603498f9e49b8

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feat(stm32mp2): add RIFSC USB configuration for variants

Add RIFSC related service call for STM32MP21 and STM32MP23 variants
with dedicated parameters. Add definitions for STM32MP21 because USB OTG

feat(stm32mp2): add RIFSC USB configuration for variants

Add RIFSC related service call for STM32MP21 and STM32MP23 variants
with dedicated parameters. Add definitions for STM32MP21 because USB OTG
Add USB OTG_HS definitions for STM32MP21.

Change-Id: I5276192ed257c3461bf7d84f0900c30fc4ad60ae
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp2): include dedicated RIFSC ID headers

RIFSC IDs differs from each STM32MP2 variants.
Include the correct files depending on the SoC that is compiled.

Signed-off-by: Nicolas Le Bayon <n

feat(stm32mp2): include dedicated RIFSC ID headers

RIFSC IDs differs from each STM32MP2 variants.
Include the correct files depending on the SoC that is compiled.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I26d6119e0b5be0c113111b4781ab39567d19c1fb

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feat(stm32mp21): enable USBOTG DFU

USBOTG DFU is present on STM32MP21. Enable related driver and adapt
platform init sequence.

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Nicolas L

feat(stm32mp21): enable USBOTG DFU

USBOTG DFU is present on STM32MP21. Enable related driver and adapt
platform init sequence.

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ia7d885c86400b7f90bd605bd797612007989b909

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feat(stm32mp2): manage RISAF MCE key for STM32MP21

On STM32MP21, RISAF encryption key is automatically generated from the
HWKEY (derivation) using RNG2 IP and enabled by a dummy write sequence
on RI

feat(stm32mp2): manage RISAF MCE key for STM32MP21

On STM32MP21, RISAF encryption key is automatically generated from the
HWKEY (derivation) using RNG2 IP and enabled by a dummy write sequence
on RISAF encryption key registers.
The context seed saving can then be replaced by new MCE one.
Set maximum size at platform level.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3f1571eaff1749758c7ed3d7522d629f8a7eb865

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feat(stm32mp2): define UART8 and UART9 under STM32MP25 flag

On STM32MP21 and STM32MP23, there are no UART8 and UART9.
The STM32MP_NB_OF_UART is then 7.
The stm32mp2_uart_addresses[] struct is also u

feat(stm32mp2): define UART8 and UART9 under STM32MP25 flag

On STM32MP21 and STM32MP23, there are no UART8 and UART9.
The STM32MP_NB_OF_UART is then 7.
The stm32mp2_uart_addresses[] struct is also updated.

Change-Id: I2019210207d9c3f24e2f29af67ad53ea54f8acff
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp21): display package type

The package type is read from OTP fuse. Display it with other SoC
information at boot.

Change-Id: Ib75461f4eebd56be5e29c93d488c0a8f84d5575a
Signed-off-by: Yann

feat(stm32mp21): display package type

The package type is read from OTP fuse. Display it with other SoC
information at boot.

Change-Id: Ib75461f4eebd56be5e29c93d488c0a8f84d5575a
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp21): add SoC part numbers

Add STM32MP21xx SoCs part numbers and the code to display it at boot.
STM32MP21x is always single core, directly return true in function
stm32mp_is_single_core(

feat(stm32mp21): add SoC part numbers

Add STM32MP21xx SoCs part numbers and the code to display it at boot.
STM32MP21x is always single core, directly return true in function
stm32mp_is_single_core().
As for STM32MP25, STM32MP21xC and STM32MP21xF can support
authenticated boot.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I586b584a3dab61ea9507a2c798a02ebdc9de0052

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feat(stm32mp21): update boot API header version

Update BOOT_API_HEADER_VERSION to header version 2.3 for STM32MP21.

STM32MP21 can use sha384 or sha256 as hash algorithm.

Set sha256 as hash algorit

feat(stm32mp21): update boot API header version

Update BOOT_API_HEADER_VERSION to header version 2.3 for STM32MP21.

STM32MP21 can use sha384 or sha256 as hash algorithm.

Set sha256 as hash algorithm by default. Sha384 support must be
developed.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: If76f1f15752ab12b0897003ffef6bfcab275c00d

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feat(stm32mp21): update STM32 header size for STM32MP21

On STM32MP21, the STM32 header v2.3 is used, and the length is 576
bytes, versus 512 bytes for all other STM32MP2 variants.

Signed-off-by: Ni

feat(stm32mp21): update STM32 header size for STM32MP21

On STM32MP21, the STM32 header v2.3 is used, and the length is 576
bytes, versus 512 bytes for all other STM32MP2 variants.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I8a5778ac8f6331ec083f122150231ede245be514

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feat(stm32mp21): remove GPIOJ and GPIOK

On STM32MP21, there are no GPIOJ and GPIOK instance.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I53d40691e4d084166c5d13c6475a6e821c

feat(stm32mp21): remove GPIOJ and GPIOK

On STM32MP21, there are no GPIOJ and GPIOK instance.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I53d40691e4d084166c5d13c6475a6e821c8d9256

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feat(stm32mp21): update SRAM1 and RETRAM base address

On STM32MP21, SRAM1 is located in range 0x0E060000-0x0E06FFFF.
RETRAM range is 0x0E040000-0x0E05FFFF.

Signed-off-by: Yann Gautier <yann.gautier

feat(stm32mp21): update SRAM1 and RETRAM base address

On STM32MP21, SRAM1 is located in range 0x0E060000-0x0E06FFFF.
RETRAM range is 0x0E040000-0x0E05FFFF.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I0ac34a1efefa601207eb8e66d66f7b41c37a5441

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feat(stm32mp21): manage STM32MP21 DT overlays

Add BL2 and BL31 DT overlays for STM32MP21 and their management in
platform.mk file.

Change-Id: I6ea0861280befa6b4f20c7cd7feef97cbdb7a0ab
Signed-off-by

feat(stm32mp21): manage STM32MP21 DT overlays

Add BL2 and BL31 DT overlays for STM32MP21 and their management in
platform.mk file.

Change-Id: I6ea0861280befa6b4f20c7cd7feef97cbdb7a0ab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp23): manage STM32MP23 DT overlays

Add BL2 and BL31 DT overlays for STM32MP23 and their management in
platform.mk file.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-I

feat(stm32mp23): manage STM32MP23 DT overlays

Add BL2 and BL31 DT overlays for STM32MP23 and their management in
platform.mk file.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I1808f88f7959b9ee109769dba4b3d3148ec3b38b

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feat(stm32mp23): display package type

The package type is read from OTP fuse. Display it with other SoC
information at boot.

Change-Id: I855bd1ac8d96ca88a7e4ee5ac8b6f65697214cc9
Signed-off-by: Yann

feat(stm32mp23): display package type

The package type is read from OTP fuse. Display it with other SoC
information at boot.

Change-Id: I855bd1ac8d96ca88a7e4ee5ac8b6f65697214cc9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp23): add SoC part numbers

Add STM32MP23xx SoCs part numbers and the code to display it at boot.
As for STM32MP25, STM32MP23xC and STM32MP23xF can support
authenticated boot.

Signed-off-

feat(stm32mp23): add SoC part numbers

Add STM32MP23xx SoCs part numbers and the code to display it at boot.
As for STM32MP25, STM32MP23xC and STM32MP23xF can support
authenticated boot.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I9fd5cefa7df47ebb0263959a3180f5bfceb1c0dd

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fix(stm32mp2): reorder DDR3 and DDR4 power supply sequences

DDR power supply sequence has to respect the order described in the
specification.
Expected DDR3 order must be VREF / VTT / VDD.
Expected

fix(stm32mp2): reorder DDR3 and DDR4 power supply sequences

DDR power supply sequence has to respect the order described in the
specification.
Expected DDR3 order must be VREF / VTT / VDD.
Expected DDR4 order must be VPP / VREF / VTT / VDD.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I4dad32aad9f96f68d8c5e38a90c31c21badec1c2

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Merge changes I8d332dbe,I9d30b6f9,I2fd7eece,Ibcd65f39,I86cc5e97 into integration

* changes:
feat(bl2): support RESET_TO_BL2 and ENABLE_RME
fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set
f

Merge changes I8d332dbe,I9d30b6f9,I2fd7eece,Ibcd65f39,I86cc5e97 into integration

* changes:
feat(bl2): support RESET_TO_BL2 and ENABLE_RME
fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set
fix(fvp): increase resident text size of BL2
fix(arm): support FCONF when TRANSFER_LIST and RESET_BL2 is set
fix(arm): update next image's ep info with the FW config address

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feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main

feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main there are two different code paths for RESET_BL2,
one handles BL2 running in EL1 and other for BL2 running in EL3.

When RME is enabled, BL2 always runs at EL3 but the current flow calls
bl2_early_platform_setup2, bl2_plat_arch_setup instead of
bl2_el3_early_platform_setup, bl2_el3_plat_arch_setup. Adding RME,
TRANSFER_LIST, ROMLIB support in bl2_el3_* helpers makes
arm_bl2_el3_setup.c almost identical to arm_bl2_setup.c.

This patch removes bl2_el3_plat helpers and related files. Now different
combinations of RESET_TO_BL2, ENABLE_RME are handled in common bl2_setup
routines in arm_bl2_setup.c. This helps to have common place to support
new features and build flags for BL2 irrespective of which EL the BL2
runs.

BREAKING-CHANGE: This patch also changes all existing platform files and
functions that use format bl2_el3_* to bl2_plat helpers. If any platform
or out-of-tree platforms that need to support running BL2 in EL1 or EL3
must now handle it in bl2_early_platform_setup2 and bl2_plat_arch_setup.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I8d332dbe2de1db3b69319496c8d04626cdcf4140

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feat(stm32mp2): manage core 1 enabling

After boot, the BootROM will issue a reset of the Cortex-A35 cores.
Core 0 will boot till kernel. Core 1 is placed in WFI in TF-A BL2.
Through PSCI, Linux will

feat(stm32mp2): manage core 1 enabling

After boot, the BootROM will issue a reset of the Cortex-A35 cores.
Core 0 will boot till kernel. Core 1 is placed in WFI in TF-A BL2.
Through PSCI, Linux will ask to have Core 1 available. The PSCI platform
code is done in stm32_pwr_domain_on(). Core0 will change Core1 reset
address thanks to CA35SS_SYSCFG_VBAR_CR register to BL31 entry point.
And will reset Core1 by setting RCC_C1P1RSTCSETR_C1P1PORRST bit.
It is possible to turn core 1 on and off. But it is not possible to do
so on core 0.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I01e59e3a2398c48cc050ec4703d6610da9e9c4bd

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feat(stm32mp2): add a ca35ss driver

Move the access on the ca35ss registers in a separate file.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I6b1a4aca9832dfc2549f26dc85

feat(stm32mp2): add a ca35ss driver

Move the access on the ca35ss registers in a separate file.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I6b1a4aca9832dfc2549f26dc8579b0728db3feb5

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feat(stm32mp2): stub PM code in serial boot

When booting from USB or UART, with programmer, the low-power sequences
won't be used, some code can then be stubbed under UART and USB flags.

Change-Id:

feat(stm32mp2): stub PM code in serial boot

When booting from USB or UART, with programmer, the low-power sequences
won't be used, some code can then be stubbed under UART and USB flags.

Change-Id: I10bda7930bd809640f2b40fe46a6fa568946c09d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(st): use KEEP for .dtb_image and .bl2_image sections

Use KEEP keyword in linker scripts that are used to build .stm32 files.
This avoids them being removed if --gc-sections option is used.

Chan

fix(st): use KEEP for .dtb_image and .bl2_image sections

Use KEEP keyword in linker scripts that are used to build .stm32 files.
This avoids them being removed if --gc-sections option is used.

Change-Id: If8e98a293199184ef3cabc45da8de6cd505d9886
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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