feat(stm32mp2): add RIFSC/RISAB protection for USB3DR

Add RIFSC/RISAB protection for USB3-IP:
- USB3DR Peripheral only accessible form Secure/Priv
- USB3DR Master is Secure/Priv to access SYSRAM in

feat(stm32mp2): add RIFSC/RISAB protection for USB3DR

Add RIFSC/RISAB protection for USB3-IP:
- USB3DR Peripheral only accessible form Secure/Priv
- USB3DR Master is Secure/Priv to access SYSRAM in bl2 plat setup.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Change-Id: Ic735cd1cadc5a3a52065b0c7db328268d405a77c

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feat(st-drivers): add RIFSC driver

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave periph

feat(st-drivers): add RIFSC driver

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave peripherals) with RISUP(Resource Isolation
Slave Unit for Peripherals) OR RISAL(Resource Isolation Slave Unit
for Address space - Lite) logics.
-RIMC registers(Non RIF-Aware masters counterpart) with RIMU
(Resource Isolation Master Unit) logic. It is possible for a master to
inherit from its slave port(RISUP) configuration.

This doesn't support semaphore acquisition.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iba4cdbf53243292fa0b42cad8392c43734dd9bc2

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feat(stm32mp2): add STM32MP_USB_PROGRAMMER support

Add STM32MP_USB_PROGRAMMER support for STM32MP2 platform by
compiling usb-dwc3 driver and adding the requested memory and
USB-DFU configurations.

feat(stm32mp2): add STM32MP_USB_PROGRAMMER support

Add STM32MP_USB_PROGRAMMER support for STM32MP2 platform by
compiling usb-dwc3 driver and adding the requested memory and
USB-DFU configurations.

The DFU stack is used in BL2 when STM32MP_USB_PROGRAMMER is activated
by the STMicroelectronics tools STM32Cubeprogrammer for serial boot mode
on USB.

Change-Id: I0dd74152ee6e0a3a3d1332d4fb2edbae7743fcc1
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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feat(stm32mp2): generate FIP for DDR initialization

Generate a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

It is loaded in internal memory

feat(stm32mp2): generate FIP for DDR initialization

Generate a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

It is loaded in internal memory before to be used with support of
the FIP memmap.

To ease Trusted Boot porting for serial boot, we can use TOOL_ADD_IMG
with a DDR_ prefix. To avoid the overriding rule issue with the check
rule in TOOL_ADD_IMG, a copy of the STM32MP_DDR_FW variable is created.

Change-Id: I3a051ca2b258771e48c6e9fed9d77ab512c2416f
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp2): add support for minimal FIP with only DDR FW

Load a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

This DDR FIP is loaded at t

feat(stm32mp2): add support for minimal FIP with only DDR FW

Load a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

This DDR FIP is loaded at the beginning of SYSRAM and used with
support of memmap features.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie413233de0e4d785b2d669087da34110df557ad3

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feat(stm32mp2): prepare DDR secure area encryption

The RISAF4 defines the DDR secure areas with specific security setup
(encryption). Its master key needs to be written before any activation.
This i

feat(stm32mp2): prepare DDR secure area encryption

The RISAF4 defines the DDR secure areas with specific security setup
(encryption). Its master key needs to be written before any activation.
This is done only if SoC supports encryption.

Change-Id: I38e6af65cadf9678a75be1b861ee0c5beea5bcb9
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp2): add some platform helpers

Update STM32MP2 the platform files.
Implement the helpers for STM32MP2, as we have them for STM32MP1:
stm32mp_is_single_core, stm32mp_check_closed_device an

feat(stm32mp2): add some platform helpers

Update STM32MP2 the platform files.
Implement the helpers for STM32MP2, as we have them for STM32MP1:
stm32mp_is_single_core, stm32mp_check_closed_device and
stm32mp_is_auth_supported

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1554efdb05338f07b292e77175db5a564cc25c78

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feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(t

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.

The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2

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feat(st): add RNG minor version

Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608

feat(st): add RNG minor version

Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608bd5cad77616bf0c031c66a8312b65d3e68c5

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feat(stm32mp2): add HASH and RNG compilation

Add the drivers compilation in STM32MP2 platform.mk.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892

feat(stm32mp2): add HASH and RNG compilation

Add the drivers compilation in STM32MP2 platform.mk.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892eff66c99

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Merge changes I54d18f01,I4e06c8a7,Ib5fc7dcd,Id5db5558,Ib941a04a into integration

* changes:
feat(st): adapt .stm32 file creation for clang
feat(st): adapt stm32 linker scripts for clang
feat(s

Merge changes I54d18f01,I4e06c8a7,Ib5fc7dcd,Id5db5558,Ib941a04a into integration

* changes:
feat(st): adapt .stm32 file creation for clang
feat(st): adapt stm32 linker scripts for clang
feat(st): update stm32 linker scripts
fix(st): mark INCBIN-generated sections as SHF_ALLOC
feat(st): remove unsupported option for clang

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Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family

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feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32

feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32MP21,
STM32MP23 and STM32MP25 flags.
STM32MP23 will use the same RCC clock compatible of STM32MP25 SoC.

Change-Id: I6422cd0553067dc92f80da1ad8ec78cadf2432bb
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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refactor(stm32mp2): update display of reset reason

Update the check of reset reason management, update displayed string
aligned with reference manual (por_rstn/bor_rstn/Pin reset), add some
missing

refactor(stm32mp2): update display of reset reason

Update the check of reset reason management, update displayed string
aligned with reference manual (por_rstn/bor_rstn/Pin reset), add some
missing reset reason (C1RST) and reuse string to reduce the size of BL2.

Change-Id: I343a46d69bf0447cafed684eab1b2e812e08ab3a
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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feat(stm32mp21): add PWR registers file

Use the new file stm32mp21_pwr.h for STM32MP21 PWR peripheral registers
definition. Update platform code for backup domain write protection
disabling.

Change

feat(stm32mp21): add PWR registers file

Use the new file stm32mp21_pwr.h for STM32MP21 PWR peripheral registers
definition. Update platform code for backup domain write protection
disabling.

Change-Id: Iedfa764529bcd5119be8e94da7f7b84699e86086
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1

feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1 SoCs.

This will avoid to forget to modify all these files when a new SoC is
introduced.

Change-Id: Ib984b22a19e08af5bc1b62fe2032f10240ec9122
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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docs(stm32mp2): introduce new STM32MP23 family

STM32MP23 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD

docs(stm32mp2): introduce new STM32MP23 family

STM32MP23 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
H264 - 3D GPU - AI / NN - LVDS / DSI
- STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
- STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet

Change-Id: Iaf3dd7e0c1eda055063361af3c98855b1272d4c6
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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docs(stm32mp2): introduce new STM32MP21 family

STM32MP21 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD

docs(stm32mp2): introduce new STM32MP21 family

STM32MP21 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
CSI - LTDC
- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet

Change-Id: Ie3db430bedd86c3b444bec647792be24b20a0cba
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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fix(stm32mp2): correct typo in definition header

Fix a typo about the platform in a comment (STM32MP2 instead
of STM32MP1).

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Change-I

fix(stm32mp2): correct typo in definition header

Fix a typo about the platform in a comment (STM32MP2 instead
of STM32MP1).

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Change-Id: I6a58b659d97d7143e277dea57d4eede7729092bc

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feat(st): adapt stm32 linker scripts for clang

With Clang, the address inside a section does not seem relative to its
start address. Use ABSOLUTE keyword for those addresses.
For stm32 binary contai

feat(st): adapt stm32 linker scripts for clang

With Clang, the address inside a section does not seem relative to its
start address. Use ABSOLUTE keyword for those addresses.
For stm32 binary containing BL2 and its DT, we can use that as PIE is
not used (either disabled or used with BL2_IN_XIP_MEM).
This is still working with GCC.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4e06c8a72c41370695db27fb6c52414487dfae47

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feat(st): update stm32 linker scripts

Remove an extra dot for the .data section.
Use FILL(0) instead of *(.data*). There is nothing there matching this
expression and was just use to have a filler.

feat(st): update stm32 linker scripts

Remove an extra dot for the .data section.
Use FILL(0) instead of *(.data*). There is nothing there matching this
expression and was just use to have a filler. Use explicit FILL(0)
instead.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ib5fc7dcdfe2b34b6892602512b8ae4115d45f307

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fix(st): mark INCBIN-generated sections as SHF_ALLOC

This is the same as rk3399 patch[1], add "a" option for sections
added to create stm32 file (containing BL2 and its DTB) in order to
properly lin

fix(st): mark INCBIN-generated sections as SHF_ALLOC

This is the same as rk3399 patch[1], add "a" option for sections
added to create stm32 file (containing BL2 and its DTB) in order to
properly link with clang.
This is still working with GCC.

[1]: 279cad8ed3 fix(rk3399): mark INCBIN-generated sections as SHF_ALLOC

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Id5db55580c9c156aa6bf616c7c09a9307bca85f9

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feat(stm32mp2): use USART1 for debug console on ultra-fly boards

This commit configures the debug console to use USART1 for
ultra-fly boards, ensuring the early console works as expected
on these bo

feat(stm32mp2): use USART1 for debug console on ultra-fly boards

This commit configures the debug console to use USART1 for
ultra-fly boards, ensuring the early console works as expected
on these boards.

These changes are specific to the ultra-fly boards and do not
affect any other boards.

Change-Id: I17f2c50779426dc31a8e85d6903141c331882c86
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>

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feat(stm32mp2): disable PIE by default on STM32MP2 platform

Allow to disable ENABLE_PIE on STM32MP2. BL31 is loaded at the beginning
of SYSRAM whatever the options set. Set ENABLE_PIE to 0 by defaul

feat(stm32mp2): disable PIE by default on STM32MP2 platform

Allow to disable ENABLE_PIE on STM32MP2. BL31 is loaded at the beginning
of SYSRAM whatever the options set. Set ENABLE_PIE to 0 by default.
This should allow us to reduce BL31 and BL2 size.

Change-Id: Ie8c83c9205e81301eb1fdcf24b94216172586630
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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refactor(stm32mp2): remove useless STM32MP_SEC_SYSRAM_SIZE

The macro STM32MP_SEC_SYSRAM_SIZE only redefine STM32MP_SYSRAM_SIZE.
Directly use the latter one and remove the STM32MP_SEC_SYSRAM_SIZE.

S

refactor(stm32mp2): remove useless STM32MP_SEC_SYSRAM_SIZE

The macro STM32MP_SEC_SYSRAM_SIZE only redefine STM32MP_SYSRAM_SIZE.
Directly use the latter one and remove the STM32MP_SEC_SYSRAM_SIZE.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I9cca19fda7294be3f31ec74293ce122037541d12

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