1 /* 2 * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #endif 14 #include <drivers/st/stm32mp25_rcc.h> 15 #ifndef __ASSEMBLER__ 16 #include <drivers/st/stm32mp2_clk.h> 17 #endif 18 #if STM32MP21 19 #include <drivers/st/stm32mp21_pwr.h> 20 #else 21 #include <drivers/st/stm32mp2_pwr.h> 22 #endif /* STM32MP21 */ 23 #include <dt-bindings/clock/stm32mp25-clks.h> 24 #include <dt-bindings/clock/stm32mp25-clksrc.h> 25 #include <dt-bindings/gpio/stm32-gpio.h> 26 #include <dt-bindings/reset/stm32mp25-resets.h> 27 28 #ifndef __ASSEMBLER__ 29 #include <boot_api.h> 30 #include <stm32mp2_private.h> 31 #include <stm32mp_common.h> 32 #include <stm32mp_dt.h> 33 #include <stm32mp_shared_resources.h> 34 #endif 35 36 /******************************************************************************* 37 * CHIP ID 38 ******************************************************************************/ 39 #define STM32MP2_CHIP_ID U(0x505) 40 41 #define STM32MP251A_PART_NB U(0x400B3E6D) 42 #define STM32MP251C_PART_NB U(0x000B306D) 43 #define STM32MP251D_PART_NB U(0xC00B3E6D) 44 #define STM32MP251F_PART_NB U(0x800B306D) 45 #define STM32MP253A_PART_NB U(0x400B3E0C) 46 #define STM32MP253C_PART_NB U(0x000B300C) 47 #define STM32MP253D_PART_NB U(0xC00B3E0C) 48 #define STM32MP253F_PART_NB U(0x800B300C) 49 #define STM32MP255A_PART_NB U(0x40082E00) 50 #define STM32MP255C_PART_NB U(0x00082000) 51 #define STM32MP255D_PART_NB U(0xC0082E00) 52 #define STM32MP255F_PART_NB U(0x80082000) 53 #define STM32MP257A_PART_NB U(0x40002E00) 54 #define STM32MP257C_PART_NB U(0x00002000) 55 #define STM32MP257D_PART_NB U(0xC0002E00) 56 #define STM32MP257F_PART_NB U(0x80002000) 57 58 #define STM32MP2_REV_A U(0x08) 59 #define STM32MP2_REV_B U(0x10) 60 #define STM32MP2_REV_X U(0x12) 61 #define STM32MP2_REV_Y U(0x11) 62 #define STM32MP2_REV_Z U(0x09) 63 64 /******************************************************************************* 65 * PACKAGE ID 66 ******************************************************************************/ 67 #define STM32MP25_PKG_CUSTOM U(0) 68 #define STM32MP25_PKG_AL_VFBGA361 U(1) 69 #define STM32MP25_PKG_AK_VFBGA424 U(3) 70 #define STM32MP25_PKG_AI_TFBGA436 U(5) 71 #define STM32MP25_PKG_UNKNOWN U(7) 72 73 /******************************************************************************* 74 * STM32MP2 memory map related constants 75 ******************************************************************************/ 76 #define STM32MP_SYSRAM_BASE U(0x0E000000) 77 #define STM32MP_SYSRAM_SIZE U(0x00040000) 78 #define SRAM1_BASE U(0x0E040000) 79 #define SRAM1_SIZE_FOR_TFA U(0x00010000) 80 #define RETRAM_BASE U(0x0E080000) 81 #define RETRAM_SIZE U(0x00020000) 82 83 /* DDR configuration */ 84 #define STM32MP_DDR_BASE U(0x80000000) 85 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 86 87 /* DDR power initializations */ 88 #ifndef __ASSEMBLER__ 89 enum ddr_type { 90 STM32MP_DDR3, 91 STM32MP_DDR4, 92 STM32MP_LPDDR4 93 }; 94 #endif 95 96 /* Section used inside TF binaries */ 97 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 98 /* 512 Bytes reserved for header */ 99 #define STM32MP_HEADER_SIZE U(0x00000200) 100 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \ 101 STM32MP_PARAM_LOAD_SIZE) 102 103 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 104 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 105 106 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 107 STM32MP_PARAM_LOAD_SIZE + \ 108 STM32MP_HEADER_SIZE) 109 110 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 111 (STM32MP_PARAM_LOAD_SIZE + \ 112 STM32MP_HEADER_SIZE)) 113 114 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */ 115 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */ 116 117 /* Allocate remaining sysram to BL31 Binary only */ 118 #define STM32MP_BL31_SIZE (STM32MP_SYSRAM_SIZE - \ 119 STM32MP_BL2_SIZE) 120 121 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \ 122 STM32MP_SYSRAM_SIZE - \ 123 STM32MP_BL2_SIZE) 124 125 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 126 127 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 128 STM32MP_BL2_RO_SIZE) 129 130 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 131 STM32MP_SYSRAM_SIZE - \ 132 STM32MP_BL2_RW_BASE) 133 134 /* BL2 and BL32/sp_min require 4 tables */ 135 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 136 137 /* 138 * MAX_MMAP_REGIONS is usually: 139 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 140 */ 141 #if defined(IMAGE_BL31) 142 #define MAX_MMAP_REGIONS 7 143 #else 144 #define MAX_MMAP_REGIONS 6 145 #endif 146 147 /* DTB initialization value */ 148 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 149 150 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 151 STM32MP_BL2_DTB_SIZE) 152 153 #if defined(IMAGE_BL2) 154 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 155 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 156 #endif 157 158 #if STM32MP_DDR_FIP_IO_STORAGE 159 #define STM32MP_DDR_FW_BASE SRAM1_BASE 160 #define STM32MP_DDR_FW_DMEM_OFFSET U(0x400) 161 #define STM32MP_DDR_FW_IMEM_OFFSET U(0x800) 162 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800) 163 #endif 164 165 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE 166 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE 167 168 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 169 #define STM32MP_BL33_MAX_SIZE U(0x400000) 170 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 171 STM32MP_BL33_MAX_SIZE) 172 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) 173 #define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */ 174 175 /******************************************************************************* 176 * STM32MP2 device/io map related constants (used for MMU) 177 ******************************************************************************/ 178 #define STM32MP_DEVICE_BASE U(0x40000000) 179 #define STM32MP_DEVICE_SIZE U(0x40000000) 180 181 /******************************************************************************* 182 * STM32MP2 RCC 183 ******************************************************************************/ 184 #define RCC_BASE U(0x44200000) 185 186 /******************************************************************************* 187 * STM32MP2 PWR 188 ******************************************************************************/ 189 #define PWR_BASE U(0x44210000) 190 191 /******************************************************************************* 192 * STM32MP2 GPIO 193 ******************************************************************************/ 194 #define GPIOA_BASE U(0x44240000) 195 #define GPIOB_BASE U(0x44250000) 196 #define GPIOC_BASE U(0x44260000) 197 #define GPIOD_BASE U(0x44270000) 198 #define GPIOE_BASE U(0x44280000) 199 #define GPIOF_BASE U(0x44290000) 200 #define GPIOG_BASE U(0x442A0000) 201 #define GPIOH_BASE U(0x442B0000) 202 #define GPIOI_BASE U(0x442C0000) 203 #define GPIOJ_BASE U(0x442D0000) 204 #define GPIOK_BASE U(0x442E0000) 205 #define GPIOZ_BASE U(0x46200000) 206 #define GPIO_BANK_OFFSET U(0x10000) 207 208 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 209 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 210 211 /******************************************************************************* 212 * STM32MP2 UART 213 ******************************************************************************/ 214 #define USART1_BASE U(0x40330000) 215 #define USART2_BASE U(0x400E0000) 216 #define USART3_BASE U(0x400F0000) 217 #define UART4_BASE U(0x40100000) 218 #define UART5_BASE U(0x40110000) 219 #define USART6_BASE U(0x40220000) 220 #define UART7_BASE U(0x40370000) 221 #define UART8_BASE U(0x40380000) 222 #define UART9_BASE U(0x402C0000) 223 #define STM32MP_NB_OF_UART U(9) 224 225 /* For UART crash console */ 226 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 227 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 228 #ifdef ULTRA_FLY 229 #define STM32MP_DEBUG_USART_BASE USART1_BASE 230 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 231 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 232 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 233 #define DEBUG_UART_TX_GPIO_PORT 3 234 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 235 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 236 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 237 #define DEBUG_UART_TX_EN_REG RCC_USART1CFGR 238 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 239 #define DEBUG_UART_RST_REG RCC_USART1CFGR 240 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 241 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV19CFGR 242 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV19CFGR 243 #else 244 #define STM32MP_DEBUG_USART_BASE USART2_BASE 245 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 246 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 247 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 248 #define DEBUG_UART_TX_GPIO_PORT 4 249 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 250 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 251 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 252 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 253 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 254 #define DEBUG_UART_RST_REG RCC_USART2CFGR 255 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 256 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 257 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 258 #endif 259 260 /******************************************************************************* 261 * STM32MP2 SDMMC 262 ******************************************************************************/ 263 #define STM32MP_SDMMC1_BASE U(0x48220000) 264 #define STM32MP_SDMMC2_BASE U(0x48230000) 265 #define STM32MP_SDMMC3_BASE U(0x48240000) 266 267 /******************************************************************************* 268 * STM32MP2 BSEC / OTP 269 ******************************************************************************/ 270 /* 271 * 367 available OTPs, the other are masked 272 * - ECIES key: 368 to 375 (only readable by bootrom) 273 * - HWKEY: 376 to 383 (never reloadable or readable) 274 */ 275 #define STM32MP2_OTP_MAX_ID U(0x16F) 276 #define STM32MP2_MID_OTP_START U(0x80) 277 #define STM32MP2_UPPER_OTP_START U(0x100) 278 279 /* OTP labels */ 280 #define PART_NUMBER_OTP "part-number-otp" 281 #define REVISION_OTP "rev_otp" 282 #define PACKAGE_OTP "package-otp" 283 #define HCONF1_OTP "otp124" 284 #define NAND_OTP "otp16" 285 #define NAND2_OTP "otp20" 286 #define BOARD_ID_OTP "board-id" 287 #define UID_OTP "uid-otp" 288 #define LIFECYCLE2_OTP "otp18" 289 #define PKH_OTP "otp144" 290 #define ENCKEY_OTP "otp260" 291 292 /* OTP mask */ 293 /* PACKAGE */ 294 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 295 #define PACKAGE_OTP_PKG_SHIFT U(0) 296 297 /* IWDG OTP */ 298 #define HCONF1_OTP_IWDG_HW_POS U(0) 299 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 300 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 301 302 /* NAND OTP */ 303 /* NAND parameter storage flag */ 304 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 305 306 /* NAND page size in bytes */ 307 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 308 #define NAND_PAGE_SIZE_SHIFT U(29) 309 #define NAND_PAGE_SIZE_2K U(0) 310 #define NAND_PAGE_SIZE_4K U(1) 311 #define NAND_PAGE_SIZE_8K U(2) 312 313 /* NAND block size in pages */ 314 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 315 #define NAND_BLOCK_SIZE_SHIFT U(27) 316 #define NAND_BLOCK_SIZE_64_PAGES U(0) 317 #define NAND_BLOCK_SIZE_128_PAGES U(1) 318 #define NAND_BLOCK_SIZE_256_PAGES U(2) 319 320 /* NAND number of block (in unit of 256 blocks) */ 321 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 322 #define NAND_BLOCK_NB_SHIFT U(19) 323 #define NAND_BLOCK_NB_UNIT U(256) 324 325 /* NAND bus width in bits */ 326 #define NAND_WIDTH_MASK BIT_32(18) 327 #define NAND_WIDTH_SHIFT U(18) 328 329 /* NAND number of ECC bits per 512 bytes */ 330 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 331 #define NAND_ECC_BIT_NB_SHIFT U(15) 332 #define NAND_ECC_BIT_NB_UNSET U(0) 333 #define NAND_ECC_BIT_NB_1_BITS U(1) 334 #define NAND_ECC_BIT_NB_4_BITS U(2) 335 #define NAND_ECC_BIT_NB_8_BITS U(3) 336 #define NAND_ECC_ON_DIE U(4) 337 338 /* NAND number of planes */ 339 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 340 341 /* NAND2 OTP */ 342 #define NAND2_PAGE_SIZE_SHIFT U(16) 343 344 /* NAND2 config distribution */ 345 #define NAND2_CONFIG_DISTRIB BIT_32(0) 346 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 347 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 348 349 /* MONOTONIC OTP */ 350 #define MAX_MONOTONIC_VALUE U(32) 351 352 /* UID OTP */ 353 #define UID_WORD_NB U(3) 354 355 /* Lifecycle OTP */ 356 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 357 358 /******************************************************************************* 359 * STM32MP2 TAMP 360 ******************************************************************************/ 361 #define PLAT_MAX_TAMP_INT U(5) 362 #define PLAT_MAX_TAMP_EXT U(3) 363 #define TAMP_BASE U(0x46010000) 364 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 365 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 366 #define TAMP_BKP_REG_CLK CK_BUS_RTC 367 #define TAMP_BKP_SEC_NUMBER U(10) 368 #define TAMP_COUNTR U(0x40) 369 370 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 371 static inline uintptr_t tamp_bkpr(uint32_t idx) 372 { 373 return TAMP_BKP_REGISTER_BASE + (idx << 2); 374 } 375 #endif 376 377 /******************************************************************************* 378 * STM32MP2 DDRCTRL 379 ******************************************************************************/ 380 #define DDRCTRL_BASE U(0x48040000) 381 382 /******************************************************************************* 383 * STM32MP2 DDRDBG 384 ******************************************************************************/ 385 #define DDRDBG_BASE U(0x48050000) 386 387 /******************************************************************************* 388 * STM32MP2 DDRPHYC 389 ******************************************************************************/ 390 #define DDRPHYC_BASE U(0x48C00000) 391 392 /******************************************************************************* 393 * Miscellaneous STM32MP1 peripherals base address 394 ******************************************************************************/ 395 #define BSEC_BASE U(0x44000000) 396 #define DBGMCU_BASE U(0x4A010000) 397 #define HASH_BASE U(0x42010000) 398 #define RTC_BASE U(0x46000000) 399 #define STGEN_BASE U(0x48080000) 400 #define SYSCFG_BASE U(0x44230000) 401 402 /******************************************************************************* 403 * STM32MP RIF 404 ******************************************************************************/ 405 #define RISAB3_BASE U(0x42110000) 406 #define RISAB5_BASE U(0x42130000) 407 408 /******************************************************************************* 409 * STM32MP CA35SSC 410 ******************************************************************************/ 411 #define A35SSC_BASE U(0x48800000) 412 413 /******************************************************************************* 414 * REGULATORS 415 ******************************************************************************/ 416 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 417 #define PLAT_NB_RDEVS U(19) 418 /* 2 FIXED */ 419 #define PLAT_NB_FIXED_REGUS U(2) 420 /* No GPIO regu */ 421 #define PLAT_NB_GPIO_REGUS U(0) 422 423 /******************************************************************************* 424 * Device Tree defines 425 ******************************************************************************/ 426 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 427 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 428 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 429 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 430 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2" 431 #define DT_UART_COMPAT "st,stm32h7-uart" 432 433 #endif /* STM32MP2_DEF_H */ 434