1 /* 2 * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #include <drivers/st/stm32mp2_clk.h> 14 #include <drivers/st/stm32mp2_risaf.h> 15 #endif 16 #if STM32MP21 17 #include <drivers/st/stm32mp21_pwr.h> 18 #include <drivers/st/stm32mp21_rcc.h> 19 #else /* STM32MP21 */ 20 #include <drivers/st/stm32mp2_pwr.h> 21 #include <drivers/st/stm32mp25_rcc.h> 22 #endif /* STM32MP21 */ 23 #if STM32MP21 24 #include <dt-bindings/clock/st,stm32mp21-rcc.h> 25 #include <dt-bindings/clock/stm32mp21-clksrc.h> 26 #include <dt-bindings/reset/st,stm32mp21-rcc.h> 27 #endif /* STM32MP21 */ 28 #if STM32MP23 29 #include <dt-bindings/clock/stm32mp25-clks.h> 30 #include <dt-bindings/clock/stm32mp25-clksrc.h> 31 #include <dt-bindings/reset/stm32mp25-resets.h> 32 #endif /* STM32MP23 */ 33 #if STM32MP25 34 #include <dt-bindings/clock/stm32mp25-clks.h> 35 #include <dt-bindings/clock/stm32mp25-clksrc.h> 36 #include <dt-bindings/reset/stm32mp25-resets.h> 37 #endif /* STM32MP25 */ 38 #include <dt-bindings/gpio/stm32-gpio.h> 39 #include <dt-bindings/soc/rif.h> 40 41 #ifndef __ASSEMBLER__ 42 #include <boot_api.h> 43 #include <stm32mp2_private.h> 44 #include <stm32mp_common.h> 45 #include <stm32mp_dt.h> 46 #include <stm32mp_shared_resources.h> 47 #endif 48 49 /******************************************************************************* 50 * CHIP ID 51 ******************************************************************************/ 52 #define STM32MP2_CHIP_ID U(0x505) 53 54 #define STM32MP251A_PART_NB U(0x400B3E6D) 55 #define STM32MP251C_PART_NB U(0x000B306D) 56 #define STM32MP251D_PART_NB U(0xC00B3E6D) 57 #define STM32MP251F_PART_NB U(0x800B306D) 58 #define STM32MP253A_PART_NB U(0x400B3E0C) 59 #define STM32MP253C_PART_NB U(0x000B300C) 60 #define STM32MP253D_PART_NB U(0xC00B3E0C) 61 #define STM32MP253F_PART_NB U(0x800B300C) 62 #define STM32MP255A_PART_NB U(0x40082E00) 63 #define STM32MP255C_PART_NB U(0x00082000) 64 #define STM32MP255D_PART_NB U(0xC0082E00) 65 #define STM32MP255F_PART_NB U(0x80082000) 66 #define STM32MP257A_PART_NB U(0x40002E00) 67 #define STM32MP257C_PART_NB U(0x00002000) 68 #define STM32MP257D_PART_NB U(0xC0002E00) 69 #define STM32MP257F_PART_NB U(0x80002000) 70 71 #define STM32MP2_REV_A U(0x08) 72 #define STM32MP2_REV_B U(0x10) 73 #define STM32MP2_REV_X U(0x12) 74 #define STM32MP2_REV_Y U(0x11) 75 #define STM32MP2_REV_Z U(0x09) 76 77 /******************************************************************************* 78 * PACKAGE ID 79 ******************************************************************************/ 80 #define STM32MP25_PKG_CUSTOM U(0) 81 #define STM32MP25_PKG_AL_VFBGA361 U(1) 82 #define STM32MP25_PKG_AK_VFBGA424 U(3) 83 #define STM32MP25_PKG_AI_TFBGA436 U(5) 84 #define STM32MP25_PKG_UNKNOWN U(7) 85 86 /******************************************************************************* 87 * STM32MP2 memory map related constants 88 ******************************************************************************/ 89 #define STM32MP_SYSRAM_BASE U(0x0E000000) 90 #define STM32MP_SYSRAM_SIZE U(0x00040000) 91 #define SRAM1_BASE U(0x0E040000) 92 #define SRAM1_SIZE_FOR_TFA U(0x00010000) 93 #define RETRAM_BASE U(0x0E080000) 94 #define RETRAM_SIZE U(0x00020000) 95 96 #if defined(IMAGE_BL2) && STM32MP_USB_PROGRAMMER 97 #define STM32MP_USB_DWC3_SIZE PAGE_SIZE 98 #define STM32MP_USB_DWC3_BASE (STM32MP_SYSRAM_BASE + \ 99 STM32MP_SYSRAM_SIZE - \ 100 STM32MP_SYSRAM_DEVICE_SIZE) 101 102 #define STM32MP_SYSRAM_DEVICE_SIZE STM32MP_USB_DWC3_SIZE 103 #define STM32MP_SYSRAM_DEVICE_BASE STM32MP_USB_DWC3_BASE 104 105 #define STM32MP_SYSRAM_MEM_SIZE (STM32MP_SYSRAM_SIZE - \ 106 STM32MP_SYSRAM_DEVICE_SIZE) 107 #define STM32MP_SYSRAM_MEM_BASE STM32MP_SYSRAM_BASE 108 #endif /* IMAGE_BL2 && STM32MP_USB_PROGRAMMER */ 109 110 /* DDR configuration */ 111 #define STM32MP_DDR_BASE U(0x80000000) 112 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 113 114 /* DDR power initializations */ 115 #ifndef __ASSEMBLER__ 116 enum ddr_type { 117 STM32MP_DDR3, 118 STM32MP_DDR4, 119 STM32MP_LPDDR4 120 }; 121 #endif 122 123 /* Section used inside TF binaries */ 124 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 125 /* 512 Bytes reserved for header */ 126 #define STM32MP_HEADER_SIZE U(0x00000200) 127 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \ 128 STM32MP_PARAM_LOAD_SIZE) 129 130 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 131 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 132 133 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 134 STM32MP_PARAM_LOAD_SIZE + \ 135 STM32MP_HEADER_SIZE) 136 137 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 138 (STM32MP_PARAM_LOAD_SIZE + \ 139 STM32MP_HEADER_SIZE)) 140 141 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */ 142 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */ 143 144 /* Allocate remaining sysram to BL31 Binary only */ 145 #define STM32MP_BL31_SIZE (STM32MP_SYSRAM_SIZE - \ 146 STM32MP_BL2_SIZE) 147 148 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \ 149 STM32MP_SYSRAM_SIZE - \ 150 STM32MP_BL2_SIZE) 151 152 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 153 154 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 155 STM32MP_BL2_RO_SIZE) 156 157 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 158 STM32MP_SYSRAM_SIZE - \ 159 STM32MP_BL2_RW_BASE) 160 161 /* BL2 and BL32/sp_min require 4 tables */ 162 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 163 164 /* 165 * MAX_MMAP_REGIONS is usually: 166 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 167 */ 168 #if STM32MP_USB_PROGRAMMER || defined(IMAGE_BL31) 169 #define MAX_MMAP_REGIONS 7 170 #else 171 #define MAX_MMAP_REGIONS 6 172 #endif 173 174 /* DTB initialization value */ 175 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 176 177 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 178 STM32MP_BL2_DTB_SIZE) 179 180 #if defined(IMAGE_BL2) 181 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 182 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 183 #endif 184 185 #if STM32MP_DDR_FIP_IO_STORAGE 186 #define STM32MP_DDR_FW_BASE SRAM1_BASE 187 #define STM32MP_DDR_FW_DMEM_OFFSET U(0x400) 188 #define STM32MP_DDR_FW_IMEM_OFFSET U(0x800) 189 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800) 190 #endif 191 192 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE 193 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE 194 195 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 196 #define STM32MP_BL33_MAX_SIZE U(0x400000) 197 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 198 STM32MP_BL33_MAX_SIZE) 199 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) 200 #define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */ 201 202 /******************************************************************************* 203 * STM32MP2 device/io map related constants (used for MMU) 204 ******************************************************************************/ 205 #define STM32MP_DEVICE_BASE U(0x40000000) 206 #define STM32MP_DEVICE_SIZE U(0x40000000) 207 208 /******************************************************************************* 209 * STM32MP2 RCC 210 ******************************************************************************/ 211 #define RCC_BASE U(0x44200000) 212 213 /******************************************************************************* 214 * STM32MP2 PWR 215 ******************************************************************************/ 216 #define PWR_BASE U(0x44210000) 217 218 /******************************************************************************* 219 * STM32MP2 GPIO 220 ******************************************************************************/ 221 #define GPIOA_BASE U(0x44240000) 222 #define GPIOB_BASE U(0x44250000) 223 #define GPIOC_BASE U(0x44260000) 224 #define GPIOD_BASE U(0x44270000) 225 #define GPIOE_BASE U(0x44280000) 226 #define GPIOF_BASE U(0x44290000) 227 #define GPIOG_BASE U(0x442A0000) 228 #define GPIOH_BASE U(0x442B0000) 229 #define GPIOI_BASE U(0x442C0000) 230 #define GPIOJ_BASE U(0x442D0000) 231 #define GPIOK_BASE U(0x442E0000) 232 #define GPIOZ_BASE U(0x46200000) 233 #define GPIO_BANK_OFFSET U(0x10000) 234 235 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 236 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 237 238 /******************************************************************************* 239 * STM32MP2 UART 240 ******************************************************************************/ 241 #define USART1_BASE U(0x40330000) 242 #define USART2_BASE U(0x400E0000) 243 #define USART3_BASE U(0x400F0000) 244 #define UART4_BASE U(0x40100000) 245 #define UART5_BASE U(0x40110000) 246 #define USART6_BASE U(0x40220000) 247 #define UART7_BASE U(0x40370000) 248 #define UART8_BASE U(0x40380000) 249 #define UART9_BASE U(0x402C0000) 250 #define STM32MP_NB_OF_UART U(9) 251 252 /* For UART crash console */ 253 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 254 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 255 #ifdef ULTRA_FLY 256 #define STM32MP_DEBUG_USART_BASE USART1_BASE 257 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 258 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 259 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 260 #define DEBUG_UART_TX_GPIO_PORT 3 261 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 262 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 263 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 264 #define DEBUG_UART_TX_EN_REG RCC_USART1CFGR 265 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 266 #define DEBUG_UART_RST_REG RCC_USART1CFGR 267 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 268 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV19CFGR 269 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV19CFGR 270 #else 271 #define STM32MP_DEBUG_USART_BASE USART2_BASE 272 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 273 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 274 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 275 #define DEBUG_UART_TX_GPIO_PORT 4 276 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 277 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 278 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 279 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 280 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 281 #define DEBUG_UART_RST_REG RCC_USART2CFGR 282 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 283 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 284 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 285 #endif 286 287 /******************************************************************************* 288 * STM32MP2 SDMMC 289 ******************************************************************************/ 290 #define STM32MP_SDMMC1_BASE U(0x48220000) 291 #define STM32MP_SDMMC2_BASE U(0x48230000) 292 #define STM32MP_SDMMC3_BASE U(0x48240000) 293 294 /******************************************************************************* 295 * STM32MP2 OSPI 296 ******************************************************************************/ 297 /* OSPI 1 & 2 memory map area */ 298 #define STM32MP_OSPI_MM_BASE U(0x60000000) 299 #define STM32MP_OSPI_MM_SIZE U(0x10000000) 300 301 /******************************************************************************* 302 * STM32MP2 BSEC / OTP 303 ******************************************************************************/ 304 /* 305 * 367 available OTPs, the other are masked 306 * - ECIES key: 368 to 375 (only readable by bootrom) 307 * - HWKEY: 376 to 383 (never reloadable or readable) 308 */ 309 #define STM32MP2_OTP_MAX_ID U(0x16F) 310 #define STM32MP2_MID_OTP_START U(0x80) 311 #define STM32MP2_UPPER_OTP_START U(0x100) 312 313 /* OTP labels */ 314 #define PART_NUMBER_OTP "part-number-otp" 315 #define REVISION_OTP "rev_otp" 316 #define PACKAGE_OTP "package-otp" 317 #define HCONF1_OTP "otp124" 318 #define NAND_OTP "otp16" 319 #define NAND2_OTP "otp20" 320 #define BOARD_ID_OTP "board-id" 321 #define UID_OTP "uid-otp" 322 #define LIFECYCLE2_OTP "otp18" 323 #define PKH_OTP "otp144" 324 #define ENCKEY_OTP "otp260" 325 326 /* OTP mask */ 327 /* PACKAGE */ 328 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 329 #define PACKAGE_OTP_PKG_SHIFT U(0) 330 331 /* IWDG OTP */ 332 #define HCONF1_OTP_IWDG_HW_POS U(0) 333 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 334 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 335 336 /* NAND OTP */ 337 /* NAND parameter storage flag */ 338 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 339 340 /* NAND page size in bytes */ 341 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 342 #define NAND_PAGE_SIZE_SHIFT U(29) 343 #define NAND_PAGE_SIZE_2K U(0) 344 #define NAND_PAGE_SIZE_4K U(1) 345 #define NAND_PAGE_SIZE_8K U(2) 346 347 /* NAND block size in pages */ 348 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 349 #define NAND_BLOCK_SIZE_SHIFT U(27) 350 #define NAND_BLOCK_SIZE_64_PAGES U(0) 351 #define NAND_BLOCK_SIZE_128_PAGES U(1) 352 #define NAND_BLOCK_SIZE_256_PAGES U(2) 353 354 /* NAND number of block (in unit of 256 blocks) */ 355 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 356 #define NAND_BLOCK_NB_SHIFT U(19) 357 #define NAND_BLOCK_NB_UNIT U(256) 358 359 /* NAND bus width in bits */ 360 #define NAND_WIDTH_MASK BIT_32(18) 361 #define NAND_WIDTH_SHIFT U(18) 362 363 /* NAND number of ECC bits per 512 bytes */ 364 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 365 #define NAND_ECC_BIT_NB_SHIFT U(15) 366 #define NAND_ECC_BIT_NB_UNSET U(0) 367 #define NAND_ECC_BIT_NB_1_BITS U(1) 368 #define NAND_ECC_BIT_NB_4_BITS U(2) 369 #define NAND_ECC_BIT_NB_8_BITS U(3) 370 #define NAND_ECC_ON_DIE U(4) 371 372 /* NAND number of planes */ 373 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 374 375 /* NAND2 OTP */ 376 #define NAND2_PAGE_SIZE_SHIFT U(16) 377 378 /* NAND2 config distribution */ 379 #define NAND2_CONFIG_DISTRIB BIT_32(0) 380 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 381 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 382 383 /* MONOTONIC OTP */ 384 #define MAX_MONOTONIC_VALUE U(32) 385 386 /* UID OTP */ 387 #define UID_WORD_NB U(3) 388 389 /* Lifecycle OTP */ 390 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 391 392 /******************************************************************************* 393 * STM32MP2 TAMP 394 ******************************************************************************/ 395 #define PLAT_MAX_TAMP_INT U(5) 396 #define PLAT_MAX_TAMP_EXT U(3) 397 #define TAMP_BASE U(0x46010000) 398 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 399 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 400 #define TAMP_BKP_REG_CLK CK_BUS_RTC 401 #define TAMP_BKP_SEC_NUMBER U(10) 402 #define TAMP_COUNTR U(0x40) 403 404 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 405 static inline uintptr_t tamp_bkpr(uint32_t idx) 406 { 407 return TAMP_BKP_REGISTER_BASE + (idx << 2); 408 } 409 #endif 410 411 /******************************************************************************* 412 * STM32MP2 USB 413 ******************************************************************************/ 414 #define USB_DWC3_BASE U(0x48300000) 415 416 /******************************************************************************* 417 * STM32MP2 DDRCTRL 418 ******************************************************************************/ 419 #define DDRCTRL_BASE U(0x48040000) 420 421 /******************************************************************************* 422 * STM32MP2 DDRDBG 423 ******************************************************************************/ 424 #define DDRDBG_BASE U(0x48050000) 425 426 /******************************************************************************* 427 * STM32MP2 DDRPHYC 428 ******************************************************************************/ 429 #define DDRPHYC_BASE U(0x48C00000) 430 431 /******************************************************************************* 432 * Miscellaneous STM32MP2 peripherals base address 433 ******************************************************************************/ 434 #define BSEC_BASE U(0x44000000) 435 #define DBGMCU_BASE U(0x4A010000) 436 #define HASH_BASE U(0x42010000) 437 #define RTC_BASE U(0x46000000) 438 #define STGEN_BASE U(0x48080000) 439 #define SYSCFG_BASE U(0x44230000) 440 441 /******************************************************************************* 442 * STM32MP RIF 443 ******************************************************************************/ 444 #define RISAB1_BASE U(0x420F0000) 445 #define RISAB2_BASE U(0x42100000) 446 #define RISAB3_BASE U(0x42110000) 447 #define RISAB5_BASE U(0x42130000) 448 449 #define RISAF1_INST 0 450 #define RISAF2_INST 1 451 #define RISAF4_INST 3 452 #define RISAF5_INST 4 453 #define RISAF_MAX_INSTANCE 5 454 455 #define RISAF1_BASE U(0x420A0000) 456 #define RISAF2_BASE U(0x420B0000) 457 #define RISAF4_BASE U(0x420D0000) 458 #define RISAF5_BASE U(0x420E0000) 459 460 #define USE_RISAF2 461 #define USE_RISAF4 462 463 #ifdef USE_RISAF1 464 #define RISAF1_MAX_REGION 4 465 #else 466 #define RISAF1_MAX_REGION 0 467 #endif 468 #ifdef USE_RISAF2 469 #define RISAF2_MAX_REGION 4 470 #else 471 #define RISAF2_MAX_REGION 0 472 #endif 473 #ifdef USE_RISAF4 474 /* Consider only encrypted region maximum number, to save memory consumption */ 475 #define RISAF4_MAX_REGION 4 476 #else 477 #define RISAF4_MAX_REGION 0 478 #endif 479 #ifdef USE_RISAF5 480 #define RISAF5_MAX_REGION 2 481 #else 482 #define RISAF5_MAX_REGION 0 483 #endif 484 #define RISAF_MAX_REGION (RISAF1_MAX_REGION + RISAF2_MAX_REGION + \ 485 RISAF4_MAX_REGION + RISAF5_MAX_REGION) 486 487 #define RISAF_KEY_SIZE_IN_BYTES RISAF_ENCRYPTION_KEY_SIZE_IN_BYTES 488 #define RISAF_SEED_SIZE_IN_BYTES U(4) 489 490 /******************************************************************************* 491 * STM32MP CA35SSC 492 ******************************************************************************/ 493 #define A35SSC_BASE U(0x48800000) 494 495 /******************************************************************************* 496 * REGULATORS 497 ******************************************************************************/ 498 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 499 #define PLAT_NB_RDEVS U(19) 500 /* 2 FIXED */ 501 #define PLAT_NB_FIXED_REGUS U(2) 502 /* No GPIO regu */ 503 #define PLAT_NB_GPIO_REGUS U(0) 504 505 /******************************************************************************* 506 * Device Tree defines 507 ******************************************************************************/ 508 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 509 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 510 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 511 #if STM32MP21 512 #define DT_RCC_CLK_COMPAT "st,stm32mp21-rcc" 513 #else 514 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 515 #endif 516 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2" 517 #define DT_UART_COMPAT "st,stm32h7-uart" 518 519 #endif /* STM32MP2_DEF_H */ 520