1# 2# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Extra partitions used to find FIP, contains: 8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2). 9STM32_EXTRA_PARTS := 6 10 11include plat/st/common/common.mk 12 13CRASH_REPORTING := 1 14# Disable PIE by default. To re-enable it, uncomment next line. 15#ENABLE_PIE := 1 16PROGRAMMABLE_RESET_ADDRESS := 1 17ifeq ($(ENABLE_PIE),1) 18BL2_IN_XIP_MEM := 1 19endif 20 21STM32MP_BL33_EL1 ?= 1 22ifeq ($(STM32MP_BL33_EL1),1) 23INIT_UNUSED_NS_EL2 := 1 24endif 25 26# Disable features unsupported in ARMv8.0 27ENABLE_SPE_FOR_NS := 0 28ENABLE_SVE_FOR_NS := 0 29 30# Default Device tree 31DTB_FILE_NAME ?= stm32mp257f-ev1.dtb 32 33TF_CFLAGS += -DSTM32MP2X 34 35STM32MP21 ?= 0 36STM32MP23 ?= 0 37STM32MP25 ?= 0 38 39ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),) 40STM32MP21 := 1 41endif 42ifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),) 43STM32MP23 := 1 44endif 45ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),) 46STM32MP25 := 1 47endif 48ifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1) 49$(warning STM32MP21=$(STM32MP21)) 50$(warning STM32MP23=$(STM32MP23)) 51$(warning STM32MP25=$(STM32MP25)) 52$(warning DTB_FILE_NAME=$(DTB_FILE_NAME)) 53$(error Cannot enable more than one STM32MP2x flag) 54endif 55 56# STM32 image header version v2.2 or v2.3 for STM32MP21 57STM32_HEADER_VERSION_MAJOR := 2 58ifeq ($(STM32MP21),1) 59STM32_HEADER_VERSION_MINOR := 3 60else 61STM32_HEADER_VERSION_MINOR := 2 62endif 63 64STM32_HASH_VER := 4 65STM32_RNG_VER := 4 66 67# Set load address for serial boot devices 68DWL_BUFFER_BASE ?= 0x87000000 69 70# DDR types 71STM32MP_DDR3_TYPE ?= 0 72STM32MP_DDR4_TYPE ?= 0 73STM32MP_LPDDR4_TYPE ?= 0 74ifeq (${STM32MP_DDR3_TYPE},1) 75DDR_TYPE := ddr3 76endif 77ifeq (${STM32MP_DDR4_TYPE},1) 78DDR_TYPE := ddr4 79endif 80ifeq (${STM32MP_LPDDR4_TYPE},1) 81DDR_TYPE := lpddr4 82endif 83 84# DDR features 85STM32MP_DDR_DUAL_AXI_PORT := 1 86STM32MP_DDR_FIP_IO_STORAGE := 1 87 88# Device tree 89BL2_DTSI := stm32mp25-bl2.dtsi 90FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 91BL31_DTSI := stm32mp25-bl31.dtsi 92FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME))) 93 94# Macros and rules to build TF binary 95STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 96STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S 97STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S 98 99STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 100STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 101STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME))) 102ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 103STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2 104STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin 105STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME} 106endif 107FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 108 109# Add the FW_CONFIG to FIP and specify the same to certtool 110$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 111 112# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 113$(eval $(call TOOL_ADD_IMG_PAYLOAD,STM32MP_SOC_FW_CONFIG,$(STM32MP_SOC_FW_CONFIG),--soc-fw-config,$(patsubst %.dtb,%.dts,$(STM32MP_SOC_FW_CONFIG)))) 114 115ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 116# Add the FW_DDR to FIP and specify the same to certtool 117$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw)) 118endif 119 120# Ultratronik Specific Boards 121ifeq ($(findstring ultra-fly,$(DTB_FILE_NAME)),ultra-fly) 122ULTRA_FLY := 1 123$(eval $(call assert_booleans,\ 124 $(sort \ 125 ULTRA_FLY \ 126 ))) 127$(eval $(call add_defines,\ 128 $(sort \ 129 ULTRA_FLY \ 130 ))) 131endif 132 133# Enable flags for C files 134$(eval $(call assert_booleans,\ 135 $(sort \ 136 STM32MP_DDR_DUAL_AXI_PORT \ 137 STM32MP_DDR_FIP_IO_STORAGE \ 138 STM32MP_DDR3_TYPE \ 139 STM32MP_DDR4_TYPE \ 140 STM32MP_LPDDR4_TYPE \ 141 STM32MP21 \ 142 STM32MP23 \ 143 STM32MP25 \ 144 STM32MP_BL33_EL1 \ 145))) 146 147$(eval $(call assert_numerics,\ 148 $(sort \ 149 PLAT_PARTITION_MAX_ENTRIES \ 150 STM32_HASH_VER \ 151 STM32_HEADER_VERSION_MAJOR \ 152 STM32_RNG_VER \ 153 STM32_TF_A_COPIES \ 154))) 155 156$(eval $(call add_defines,\ 157 $(sort \ 158 DWL_BUFFER_BASE \ 159 PLAT_DEF_FIP_UUID \ 160 PLAT_PARTITION_MAX_ENTRIES \ 161 PLAT_TBBR_IMG_DEF \ 162 STM32_HASH_VER \ 163 STM32_RNG_VER \ 164 STM32_TF_A_COPIES \ 165 STM32MP_DDR_DUAL_AXI_PORT \ 166 STM32MP_DDR_FIP_IO_STORAGE \ 167 STM32MP_DDR3_TYPE \ 168 STM32MP_DDR4_TYPE \ 169 STM32MP_LPDDR4_TYPE \ 170 STM32MP21 \ 171 STM32MP23 \ 172 STM32MP25 \ 173 STM32MP_BL33_EL1 \ 174))) 175 176# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI 177# Disable mbranch-protection to avoid adding useless code 178TF_CFLAGS += -mbranch-protection=none 179 180# Include paths and source files 181PLAT_INCLUDES += -Iplat/st/stm32mp2/include/ 182PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/ 183PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/ 184 185PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S 186PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S 187PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S 188 189PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \ 190 drivers/st/pmic/stpmic2.c \ 191 192PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c 193 194PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c 195 196PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \ 197 drivers/st/reset/stm32mp2_reset.c \ 198 plat/st/stm32mp2/stm32mp2_syscfg.c 199 200PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 201 drivers/st/clk/clk-stm32mp2.c \ 202 drivers/st/crypto/stm32_rng.c 203 204BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c 205 206BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \ 207 plat/st/stm32mp2/plat_ddr.c 208 209BL2_SOURCES += drivers/st/crypto/stm32_hash.c 210 211ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 212BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 213endif 214 215ifeq (${STM32MP_USB_PROGRAMMER},1) 216BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c 217endif 218 219BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \ 220 drivers/st/ddr/stm32mp2_ddr_helpers.c \ 221 drivers/st/ddr/stm32mp2_ram.c 222 223BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \ 224 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \ 225 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \ 226 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \ 227 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \ 228 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \ 229 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \ 230 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \ 231 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \ 232 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \ 233 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \ 234 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \ 235 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \ 236 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c 237 238BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \ 239 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \ 240 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \ 241 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \ 242 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c 243 244# BL31 sources 245BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 246 247BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \ 248 plat/st/stm32mp2/stm32mp2_pm.c \ 249 plat/st/stm32mp2/stm32mp2_topology.c 250# Generic GIC v2 251include drivers/arm/gic/v2/gicv2.mk 252 253BL31_SOURCES += ${GICV2_SOURCES} \ 254 plat/common/plat_gicv2.c \ 255 plat/st/common/stm32mp_gic.c 256 257# Generic PSCI 258BL31_SOURCES += plat/common/plat_psci_common.c 259 260BL31_SOURCES += plat/st/common/stm32mp_svc_setup.c \ 261 plat/st/stm32mp2/services/stgen_svc.c \ 262 plat/st/stm32mp2/services/stm32mp2_svc_setup.c 263 264# Arm Archtecture services 265BL31_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c 266 267# Compilation rules 268.PHONY: check_ddr_type 269bl2: check_ddr_type 270 271check_ddr_type: 272 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \ 273 $(STM32MP_DDR4_TYPE) + \ 274 $(STM32MP_LPDDR4_TYPE))))) 275 @if [ ${DDR_TYPE} != 1 ]; then \ 276 echo "One and only one DDR type must be defined"; \ 277 false; \ 278 fi 279 280# Create DTB file for BL31 281${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/ 282 @echo '#include "$(patsubst fdts/%,%,$<)"' > $@ 283 @echo '#include "${BL31_DTSI}"' >> $@ 284 285include plat/st/common/common_rules.mk 286