1 /* 2 * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cdefs.h> 9 #include <errno.h> 10 #include <stdint.h> 11 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/clk.h> 15 #include <drivers/mmc.h> 16 #include <drivers/st/regulator_fixed.h> 17 #include <drivers/st/stm32mp2_ddr_helpers.h> 18 #include <drivers/st/stm32mp2_ram.h> 19 #include <drivers/st/stm32mp_pmic2.h> 20 #include <drivers/st/stm32mp_risab_regs.h> 21 #include <lib/fconf/fconf.h> 22 #include <lib/fconf/fconf_dyn_cfg_getter.h> 23 #include <lib/mmio.h> 24 #include <lib/optee_utils.h> 25 #include <lib/xlat_tables/xlat_tables_v2.h> 26 #include <plat/common/platform.h> 27 28 #include <platform_def.h> 29 #include <stm32mp_common.h> 30 #include <stm32mp_dt.h> 31 32 #define BOOT_CTX_ADDR 0x0e000020UL 33 34 static void print_reset_reason(void) 35 { 36 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR); 37 const char *reason_str = "Unidentified"; 38 39 #if !STM32MP21 40 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) { 41 INFO("CA35 processor core 1 reset\n"); 42 } 43 #endif /* !STM32MP21 */ 44 45 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) { 46 if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) { 47 reason_str = "System exits from Standby for CA35"; 48 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) { 49 reason_str = "D1 domain exits from DStandby"; 50 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_VCPURSTF) != 0U) { 51 reason_str = "System reset from VCPU monitor"; 52 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) { 53 reason_str = "CA35 reset by CM33 (C1RST)"; 54 } else { 55 reason_str = "Unidentified"; 56 } 57 } else { 58 if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) { 59 reason_str = "Power-on reset (por_rstn)"; 60 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) { 61 reason_str = "Brownout reset (bor_rstn)"; 62 } else if ((rstsr & (RCC_C1BOOTRSTSSETR_SYSC2RSTF | 63 RCC_C1BOOTRSTSSETR_SYSC1RSTF)) != 0U) { 64 reason_str = "System reset (SYSRST)"; 65 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) { 66 reason_str = "Clock failure on HSE"; 67 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF) != 0U) { 68 reason_str = "IWDG system reset (iwdgX_out_rst)"; 69 } else if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) { 70 reason_str = "Pin reset from NRST"; 71 } else { 72 reason_str = "Unidentified"; 73 } 74 } 75 76 INFO("Reset reason: %s (0x%x)\n", reason_str, rstsr); 77 } 78 79 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 80 u_register_t arg1 __unused, 81 u_register_t arg2 __unused, 82 u_register_t arg3 __unused) 83 { 84 stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR); 85 } 86 87 void bl2_platform_setup(void) 88 { 89 int ret; 90 91 ret = stm32mp2_ddr_probe(); 92 if (ret != 0) { 93 ERROR("DDR probe: error %d\n", ret); 94 panic(); 95 } 96 97 if (stm32mp2_risaf_init() < 0) { 98 panic(); 99 } 100 101 /* Map DDR for binary load, now with cacheable attribute */ 102 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 103 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 104 if (ret < 0) { 105 ERROR("DDR mapping: error %d\n", ret); 106 panic(); 107 } 108 } 109 110 static void reset_backup_domain(void) 111 { 112 uintptr_t pwr_base = stm32mp_pwr_base(); 113 uintptr_t rcc_base = stm32mp_rcc_base(); 114 115 /* 116 * Disable the backup domain write protection. 117 * The protection is enable at each reset by hardware 118 * and must be disabled by software. 119 */ 120 #if STM32MP21 121 mmio_setbits_32(pwr_base + PWR_BDCR, PWR_BDCR_DBP); 122 123 while ((mmio_read_32(pwr_base + PWR_BDCR) & PWR_BDCR_DBP) == 0U) { 124 ; 125 } 126 #else /* STM32MP21 */ 127 mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P); 128 129 while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) { 130 ; 131 } 132 #endif /* STM32MP21 */ 133 134 /* Reset backup domain on cold boot cases */ 135 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) { 136 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 137 138 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { 139 ; 140 } 141 142 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 143 } 144 } 145 146 void bl2_el3_plat_arch_setup(void) 147 { 148 const char *board_model; 149 boot_api_context_t *boot_context = 150 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 151 152 if (stm32_otp_probe() != 0U) { 153 EARLY_ERROR("OTP probe failed\n"); 154 panic(); 155 } 156 157 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 158 BL_CODE_END - BL_CODE_BASE, 159 MT_CODE | MT_SECURE); 160 161 configure_mmu(); 162 163 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 164 panic(); 165 } 166 167 reset_backup_domain(); 168 169 /* 170 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2), 171 * and so before stm32mp2_clk_init(). 172 */ 173 ddr_sub_system_clk_init(); 174 175 if (stm32mp2_clk_init() < 0) { 176 panic(); 177 } 178 179 #if STM32MP_DDR_FIP_IO_STORAGE 180 /* 181 * RISAB3 setup (dedicated for SRAM1) 182 * 183 * Allow secure read/writes data accesses to non-secure 184 * blocks or pages, all RISAB registers are writable. 185 * DDR firmwares are saved there before being loaded in DDRPHY memory. 186 */ 187 mmio_write_32(RISAB3_BASE + RISAB_CR, RISAB_CR_SRWIAD); 188 #endif 189 190 stm32_save_boot_info(boot_context); 191 192 if (stm32mp_uart_console_setup() != 0) { 193 goto skip_console_init; 194 } 195 196 stm32mp_print_cpuinfo(); 197 198 board_model = dt_get_board_model(); 199 if (board_model != NULL) { 200 NOTICE("Model: %s\n", board_model); 201 } 202 203 stm32mp_print_boardinfo(); 204 205 print_reset_reason(); 206 207 skip_console_init: 208 if (fixed_regulator_register() != 0) { 209 panic(); 210 } 211 212 if (dt_pmic_status() > 0) { 213 initialize_pmic(); 214 } 215 216 fconf_populate("TB_FW", STM32MP_DTB_BASE); 217 218 /* 219 * RISAB5 setup (dedicated for RETRAM) 220 * 221 * Allow secure read/writes data accesses to non-secure 222 * blocks or pages, all RISAB registers are writable. 223 * DDR retention registers are saved there and restored 224 * when exiting standby low power state. 225 */ 226 mmio_write_32(RISAB5_BASE + RISAB_CR, RISAB_CR_SRWIAD); 227 228 stm32mp_io_setup(); 229 } 230 231 /******************************************************************************* 232 * This function can be used by the platforms to update/use image 233 * information for given `image_id`. 234 ******************************************************************************/ 235 int bl2_plat_handle_post_image_load(unsigned int image_id) 236 { 237 int err = 0; 238 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 239 bl_mem_params_node_t *pager_mem_params; 240 const struct dyn_cfg_dtb_info_t *config_info; 241 unsigned int i; 242 const unsigned int image_ids[] = { 243 BL31_IMAGE_ID, 244 SOC_FW_CONFIG_ID, 245 BL32_IMAGE_ID, 246 BL33_IMAGE_ID, 247 HW_CONFIG_ID, 248 }; 249 250 assert(bl_mem_params != NULL); 251 252 #if STM32MP_SDMMC || STM32MP_EMMC 253 /* 254 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 255 * We take the worst case which is 2 MMC blocks. 256 */ 257 if ((image_id != FW_CONFIG_ID) && 258 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 259 inv_dcache_range(bl_mem_params->image_info.image_base + 260 bl_mem_params->image_info.image_size, 261 2U * MMC_BLOCK_SIZE); 262 } 263 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 264 265 switch (image_id) { 266 case FW_CONFIG_ID: 267 /* Set global DTB info for fixed fw_config information */ 268 set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE, 269 FW_CONFIG_ID); 270 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 271 272 /* Iterate through all the fw config IDs */ 273 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 274 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 275 assert(bl_mem_params != NULL); 276 277 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 278 if (config_info == NULL) { 279 continue; 280 } 281 282 bl_mem_params->image_info.image_base = config_info->config_addr; 283 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 284 285 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 286 287 switch (image_ids[i]) { 288 case BL31_IMAGE_ID: 289 bl_mem_params->ep_info.pc = config_info->config_addr; 290 break; 291 292 case BL32_IMAGE_ID: 293 bl_mem_params->ep_info.pc = config_info->config_addr; 294 295 /* In case of OPTEE, initialize address space with tos_fw addr */ 296 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 297 if (pager_mem_params != NULL) { 298 pager_mem_params->image_info.image_base = 299 config_info->config_addr; 300 pager_mem_params->image_info.image_max_size = 301 config_info->config_max_size; 302 } 303 break; 304 305 case BL33_IMAGE_ID: 306 bl_mem_params->ep_info.pc = config_info->config_addr; 307 break; 308 309 case HW_CONFIG_ID: 310 case SOC_FW_CONFIG_ID: 311 break; 312 313 default: 314 return -EINVAL; 315 } 316 } 317 318 /* 319 * After this step, the BL2 device tree area will be overwritten 320 * with BL31 binary, no other data should be read from BL2 DT. 321 */ 322 323 break; 324 325 case BL32_IMAGE_ID: 326 if ((bl_mem_params->image_info.image_base != 0UL) && 327 (optee_header_is_valid(bl_mem_params->image_info.image_base))) { 328 /* BL32 is OP-TEE header */ 329 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 330 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 331 assert(pager_mem_params != NULL); 332 333 err = parse_optee_header(&bl_mem_params->ep_info, 334 &pager_mem_params->image_info, 335 NULL); 336 if (err != 0) { 337 ERROR("OPTEE header parse error.\n"); 338 panic(); 339 } 340 341 /* Set optee boot info from parsed header data */ 342 bl_mem_params->ep_info.args.arg0 = 0U; /* Unused */ 343 bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */ 344 bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */ 345 } 346 break; 347 348 case BL33_IMAGE_ID: 349 #if PSA_FWU_SUPPORT 350 stm32_fwu_set_boot_idx(); 351 #endif /* PSA_FWU_SUPPORT */ 352 break; 353 354 default: 355 /* Do nothing in default case */ 356 break; 357 } 358 359 return err; 360 } 361