Merge "fix(layerscape): unlock write access SMMU_CBn_ACTLR" into integration

feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_

feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_entries and create
`plat_fiptool.mk` in order to enable the integration
of the DDR FW binary into the FIP image using
`fiptool` command.

Change-Id: I10c000025378206411ab70dbc5b2e745ffb01e5d
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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fix(nxp): tbbr: adds snvs_init

Fix to initialize the SNVS driver as part of soc early init, that sets
the snvs base address to read or write to the memory mapped registers of
SNVS IP.

Change-Id: I6

fix(nxp): tbbr: adds snvs_init

Fix to initialize the SNVS driver as part of soc early init, that sets
the snvs base address to read or write to the memory mapped registers of
SNVS IP.

Change-Id: I6ebd1d17302647487ec786f5e20f51450ce29473
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>

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refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

$(OBJS): %.o: %.s
...

These behave similarly, but have some subtle differences. The former
defines a rule "for any target matching %.o where there is not a more
specific rule", whereas the latter defines a rule "for these targets,
which match %.o".

Where possible it is better to use a static pattern rule as it reduces
the rule space that Make needs to search.

Change-Id: Ifba4f44bcecf4e74980c31347e192cdf1e42003e
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(lx2160a): put cert_create_tbbr.mk in the standard location

The cert_create_tbbr.mk file is generally looked for in the platform
directory. The lx2160a breaks from this convention and stores the

fix(lx2160a): put cert_create_tbbr.mk in the standard location

The cert_create_tbbr.mk file is generally looked for in the platform
directory. The lx2160a breaks from this convention and stores the file
elsewhere, requiring a cludgy `cp` mid way through the make process. The
result is an untracked file when building the platform, which is
undesirable.

Fix this by putting the cert_create_tbbr.mk (and associated source
files) in the plat/ directory, just like we do for juno and stm32mp1.

Change-Id: Ifa8bb07dba4f55da4f0e230efa7beccf30bd1de7
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(lx2160): set snoop-delayed exclusive handling on A72 cores" into integration

fix(layerscape): unlock write access SMMU_CBn_ACTLR

This patch is to fix Errata #841119 and #826419 (see [1]) failed
apply in Linux because of SMMU_CBn_ACTLR register can't be modified
in non-secure

fix(layerscape): unlock write access SMMU_CBn_ACTLR

This patch is to fix Errata #841119 and #826419 (see [1]) failed
apply in Linux because of SMMU_CBn_ACTLR register can't be modified
in non-secure states. This mimics the changes from commit 0ca1d8fba
("fix(layerscape): unlock write access SMMU_CBn_ACTLR")

[1] https://developer.arm.com/documentation/epm133458/latest

Change-Id: I3f1e35150f66c604be2e10b3f91b39b2a7dc62bd
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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Merge "fix(nxp-crypto): restricts generating nxp_mkvb via ns-world" into integration

Merge changes Iea4c11de,Icae1fb08 into integration

* changes:
fix(lx2160): add DDRC missing DIMMs
fix(nxp): driver crypto caam

feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image

feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image, while fip.bin will be deployed as a raw MBR partition on
the SD card. This approach allows the FIP location to be auto-discovered
based on information found in the MBR. The partition ID where the image
is stored is set to partition zero but can be changed using the FIP_PART
makefile parameter. The GPT header cannot be used instead of MBR due to
the boot header on the S32G274A, which may overlap with the GPT reserved
area.

Change-Id: I26746023dba7788613a74ae69c86124b450e6bdb
Co-developed-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Co-developed-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661

feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661d2f6b5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id:

feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id: I223904c24a14a89ef676626b54a5937f39a17eda
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): set the system counter rate

Generic timer initialization at the BL2 stage is incomplete without
configuring the system counter frequency. This configuration is
performed by the PS

feat(s32g274ardb): set the system counter rate

Generic timer initialization at the BL2 stage is incomplete without
configuring the system counter frequency. This configuration is
performed by the PSCI layer in BL31.

Change-Id: I134cffe47819061f1608386cf98a39014cd12396
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): init the generic timer for BL2

The generic timer must be initialized during BL2 because the uSDHC
driver, which will be enabled in subsequent commits, requires it for
delays.

Cha

feat(s32g274ardb): init the generic timer for BL2

The generic timer must be initialized during BL2 because the uSDHC
driver, which will be enabled in subsequent commits, requires it for
delays.

Change-Id: Ia09b3d3565a09ace7389d2e063af1185cc80fa27
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from

fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from
Normal world. Leading to the leak og MKVB to non-secure world.

Fix to prevent MKVB generation for requests originating from non-secure
world.
- For non-secure world, this SMC is return failure.

Additional fix for bound-check before continuing to generate the MKVB.

Change-Id: I9940b4dfe33289c2d57595a2a08acff29a12c974
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>

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fix(lx2160): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or

fix(lx2160): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.

Similar to commit 5668db72b ("feat(ti): set snoop-delayed exclusive
handling on A72 cores") enable the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.

Change-Id: I984f3d08b7a608f59f38e01461aeb448f2ef5af1
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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fix(lx2160): add DDRC missing DIMMs

LX2160a has 2 DDRC. Let's assume 2 DIMMs.

Without such modification, only half of the memory if available on the
board.

Inspired from plat/nxp/soc-lx2160a/lx216

fix(lx2160): add DDRC missing DIMMs

LX2160a has 2 DDRC. Let's assume 2 DIMMs.

Without such modification, only half of the memory if available on the
board.

Inspired from plat/nxp/soc-lx2160a/lx2160ardb/platform.mk

Change-Id: Iea4c11de104a2999fdff0da7f8e7a3baada0fd3d
Signed-off-by: Vincent Jardin <vjardin@free.fr>

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feat(auth): introducing auth.mk

Introducing authentication specific makefile auth.mk to include common
auth source files.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I

feat(auth): introducing auth.mk

Introducing authentication specific makefile auth.mk to include common
auth source files.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ifb07c48861fe415d82cb7390c3a5f6e60ba699d9

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refactor(s32g274a): replace mov/movk with mov_imm

Replace pairs of mov and movk instructions with the mov_imm macro to
align with the rest of the infrastructure and avoid code duplication.

Change-I

refactor(s32g274a): replace mov/movk with mov_imm

Replace pairs of mov and movk instructions with the mov_imm macro to
align with the rest of the infrastructure and avoid code duplication.

Change-Id: I3c091eb8ff111c7bc030b32ad5948cbfaea3b35c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
e

chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
expectation so that future platform implementers don't get misled.

Change-Id: Ic33f0b6da74592ad6778fd802c2f0b85223af614
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "build: remove Windows compatibility layer" into integration

build: remove Windows compatibility layer

For a couple of releases now we have officially withdrawn support for
building TF-A on Windows using the native environment, relying instead
on POSIX emulat

build: remove Windows compatibility layer

For a couple of releases now we have officially withdrawn support for
building TF-A on Windows using the native environment, relying instead
on POSIX emulation layers like MSYS2, Mingw64, Cygwin or WSL.

This change removes the remainder of the OS compatibility layer
entirely, and migrates the build system over to explicitly relying on a
POSIX environment.

Change-Id: I8fb60d998162422e958009afd17eab826e3bc39b
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks ca

feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.

Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable MMU for BL31 stage

Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularit

feat(s32g274a): enable MMU for BL31 stage

Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularity during the porting process.

Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): dynamically map GIC regions

Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.

Change-Id: Ia810e

feat(s32g274a): dynamically map GIC regions

Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.

Change-Id: Ia810ec2329993057173e8fc25620a3df59b1e55d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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