1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <endian.h> 8 9 #include <arch.h> 10 #include <caam.h> 11 #include <cassert.h> 12 #include <cci.h> 13 #include <common/debug.h> 14 #include <dcfg.h> 15 #include <i2c.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <ls_interconnect.h> 18 #include <mmio.h> 19 #ifdef POLICY_FUSE_PROVISION 20 #include <nxp_gpio.h> 21 #endif 22 #include <nxp_smmu.h> 23 #include <nxp_timer.h> 24 #include <plat_console.h> 25 #include <plat_gic.h> 26 #include <plat_tzc400.h> 27 #include <pmu.h> 28 #include <scfg.h> 29 #if defined(NXP_SFP_ENABLED) 30 #include <sfp.h> 31 #endif 32 33 #include <errata.h> 34 #ifdef CONFIG_OCRAM_ECC_EN 35 #include <ocram.h> 36 #endif 37 #include "plat_common.h" 38 #include "platform_def.h" 39 #include "soc.h" 40 41 static dcfg_init_info_t dcfg_init_data = { 42 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 43 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 44 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 45 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 46 }; 47 48 static struct soc_type soc_list[] = { 49 SOC_ENTRY(LS1017AN, LS1017AN, 1, 1), 50 SOC_ENTRY(LS1017AE, LS1017AE, 1, 1), 51 SOC_ENTRY(LS1018AN, LS1018AN, 1, 1), 52 SOC_ENTRY(LS1018AE, LS1018AE, 1, 1), 53 SOC_ENTRY(LS1027AN, LS1027AN, 1, 2), 54 SOC_ENTRY(LS1027AE, LS1027AE, 1, 2), 55 SOC_ENTRY(LS1028AN, LS1028AN, 1, 2), 56 SOC_ENTRY(LS1028AE, LS1028AE, 1, 2), 57 }; 58 59 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 60 assert_invalid_ls1028a_cluster_count); 61 62 /* 63 * Function returns the base counter frequency 64 * after reading the first entry at CNTFID0 (0x20 offset). 65 * 66 * Function is used by: 67 * 1. ARM common code for PSCI management. 68 * 2. ARM Generic Timer init. 69 * 70 */ 71 unsigned int plat_get_syscnt_freq2(void) 72 { 73 unsigned int counter_base_frequency; 74 /* 75 * Below register specifies the base frequency of the system counter. 76 * As per NXP Board Manuals: 77 * The system counter always works with SYS_REF_CLK/4 frequency clock. 78 */ 79 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); 80 81 return counter_base_frequency; 82 } 83 84 #ifdef IMAGE_BL2 85 86 #ifdef POLICY_FUSE_PROVISION 87 static gpio_init_info_t gpio_init_data = { 88 .gpio1_base_addr = NXP_GPIO1_ADDR, 89 .gpio2_base_addr = NXP_GPIO2_ADDR, 90 .gpio3_base_addr = NXP_GPIO3_ADDR, 91 }; 92 #endif 93 94 void soc_preload_setup(void) 95 { 96 } 97 98 void soc_early_init(void) 99 { 100 uint8_t num_clusters, cores_per_cluster; 101 102 #ifdef CONFIG_OCRAM_ECC_EN 103 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); 104 #endif 105 dcfg_init(&dcfg_init_data); 106 enable_timer_base_to_cluster(NXP_PMU_ADDR); 107 enable_core_tb(NXP_PMU_ADDR); 108 dram_regions_info_t *dram_regions_info = get_dram_regions_info(); 109 110 #ifdef POLICY_FUSE_PROVISION 111 gpio_init(&gpio_init_data); 112 sec_init(NXP_CAAM_ADDR); 113 #endif 114 115 #if LOG_LEVEL > 0 116 /* Initialize the console to provide early debug support */ 117 plat_console_init(NXP_CONSOLE_ADDR, 118 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 119 #endif 120 enum boot_device dev = get_boot_dev(); 121 /* 122 * Mark the buffer for SD in OCRAM as non secure. 123 * The buffer is assumed to be at end of OCRAM for 124 * the logic below to calculate TZPC programming 125 */ 126 if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) { 127 /* 128 * Calculate the region in OCRAM which is secure 129 * The buffer for SD needs to be marked non-secure 130 * to allow SD to do DMA operations on it 131 */ 132 uint32_t secure_region = (NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE); 133 uint32_t mask = secure_region/TZPC_BLOCK_SIZE; 134 135 mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask); 136 137 /* Add the entry for buffer in MMU Table */ 138 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, 139 NXP_SD_BLOCK_BUF_SIZE, MT_DEVICE | MT_RW | MT_NS); 140 } 141 142 /* 143 * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts. 144 */ 145 smmu_cache_unlock(NXP_SMMU_ADDR); 146 INFO("SMMU Cache Unlocking is Configured.\n"); 147 148 #if TRUSTED_BOARD_BOOT 149 uint32_t mode; 150 151 sfp_init(NXP_SFP_ADDR); 152 153 /* 154 * For secure boot disable SMMU. 155 * Later when platform security policy comes in picture, 156 * this might get modified based on the policy 157 */ 158 if (check_boot_mode_secure(&mode) == true) { 159 bypass_smmu(NXP_SMMU_ADDR); 160 } 161 162 /* 163 * For Mbedtls currently crypto is not supported via CAAM 164 * enable it when that support is there. In tbbr.mk 165 * the CAAM_INTEG is set as 0. 166 */ 167 #ifndef MBEDTLS_X509 168 /* Initialize the crypto accelerator if enabled */ 169 if (is_sec_enabled()) { 170 sec_init(NXP_CAAM_ADDR); 171 } else { 172 INFO("SEC is disabled.\n"); 173 } 174 #endif 175 #endif 176 177 /* Set eDDRTQ for DDR performance */ 178 scfg_setbits32((void *)(NXP_SCFG_ADDR + 0x210), 0x1f1f1f1f); 179 180 soc_errata(); 181 182 /* 183 * Initialize Interconnect for this cluster during cold boot. 184 * No need for locks as no other CPU is active. 185 */ 186 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 187 188 /* 189 * Enable Interconnect coherency for the primary CPU's cluster. 190 */ 191 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 192 plat_ls_interconnect_enter_coherency(num_clusters); 193 194 delay_timer_init(NXP_TIMER_ADDR); 195 i2c_init(NXP_I2C_ADDR); 196 dram_regions_info->total_dram_size = init_ddr(); 197 } 198 199 void soc_bl2_prepare_exit(void) 200 { 201 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 202 set_sfp_wr_disable(); 203 #endif 204 } 205 206 /* 207 * This function returns the boot device based on RCW_SRC 208 */ 209 enum boot_device get_boot_dev(void) 210 { 211 enum boot_device src = BOOT_DEVICE_NONE; 212 uint32_t porsr1; 213 uint32_t rcw_src; 214 215 porsr1 = read_reg_porsr1(); 216 217 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 218 switch (rcw_src) { 219 case FLEXSPI_NOR: 220 src = BOOT_DEVICE_FLEXSPI_NOR; 221 INFO("RCW BOOT SRC is FLEXSPI NOR\n"); 222 break; 223 case FLEXSPI_NAND2K_VAL: 224 case FLEXSPI_NAND4K_VAL: 225 INFO("RCW BOOT SRC is FLEXSPI NAND\n"); 226 src = BOOT_DEVICE_FLEXSPI_NAND; 227 break; 228 case SDHC1_VAL: 229 src = BOOT_DEVICE_EMMC; 230 INFO("RCW BOOT SRC is SD\n"); 231 break; 232 case SDHC2_VAL: 233 src = BOOT_DEVICE_SDHC2_EMMC; 234 INFO("RCW BOOT SRC is EMMC\n"); 235 break; 236 default: 237 break; 238 } 239 240 return src; 241 } 242 243 /* 244 * This function sets up access permissions on memory regions 245 ****************************************************************************/ 246 void soc_mem_access(void) 247 { 248 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 249 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; 250 int dram_idx = 0; 251 /* index 0 is reserved for region-0 */ 252 int index = 1; 253 254 for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions; 255 dram_idx++) { 256 if (info_dram_regions->region[dram_idx].size == 0) { 257 ERROR("DDR init failure, or"); 258 ERROR("DRAM regions not populated correctly.\n"); 259 break; 260 } 261 262 index = populate_tzc400_reg_list(tzc400_reg_list, 263 dram_idx, index, 264 info_dram_regions->region[dram_idx].addr, 265 info_dram_regions->region[dram_idx].size, 266 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 267 } 268 269 mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list); 270 } 271 272 #else 273 274 static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2]; 275 /* 276 * This function dynamically constructs the topology according to 277 * SoC Flavor and returns it. 278 */ 279 const unsigned char *plat_get_power_domain_tree_desc(void) 280 { 281 uint8_t num_clusters, cores_per_cluster; 282 unsigned int i; 283 284 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 285 /* 286 * The highest level is the system level. The next level is constituted 287 * by clusters and then cores in clusters. 288 */ 289 _power_domain_tree_desc[0] = 1; 290 _power_domain_tree_desc[1] = num_clusters; 291 292 for (i = 0; i < _power_domain_tree_desc[1]; i++) 293 _power_domain_tree_desc[i + 2] = cores_per_cluster; 294 295 return _power_domain_tree_desc; 296 } 297 298 /* 299 * This function returns the core count within the cluster corresponding to 300 * `mpidr`. 301 */ 302 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 303 { 304 uint8_t num_clusters, cores_per_cluster; 305 306 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 307 return num_clusters; 308 } 309 310 void soc_early_platform_setup2(void) 311 { 312 dcfg_init(&dcfg_init_data); 313 /* Initialize system level generic timer for Socs */ 314 delay_timer_init(NXP_TIMER_ADDR); 315 316 #if LOG_LEVEL > 0 317 /* Initialize the console to provide early debug support */ 318 plat_console_init(NXP_CONSOLE_ADDR, 319 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 320 #endif 321 } 322 323 void soc_platform_setup(void) 324 { 325 /* Initialize the GIC driver, cpu and distributor interfaces */ 326 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; 327 static interrupt_prop_t ls_interrupt_props[] = { 328 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), 329 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) 330 }; 331 332 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, 333 PLATFORM_CORE_COUNT, 334 ls_interrupt_props, 335 ARRAY_SIZE(ls_interrupt_props), 336 target_mask_array, 337 plat_core_pos); 338 339 plat_ls_gic_init(); 340 enable_init_timer(); 341 } 342 343 /* This function initializes the soc from the BL31 module */ 344 void soc_init(void) 345 { 346 uint8_t num_clusters, cores_per_cluster; 347 348 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 349 350 /* Low-level init of the soc */ 351 soc_init_lowlevel(); 352 _init_global_data(); 353 soc_init_percpu(); 354 _initialize_psci(); 355 356 /* 357 * Initialize Interconnect for this cluster during cold boot. 358 * No need for locks as no other CPU is active. 359 */ 360 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 361 362 /* Enable Interconnect coherency for the primary CPU's cluster. */ 363 plat_ls_interconnect_enter_coherency(num_clusters); 364 365 /* Set platform security policies */ 366 _set_platform_security(); 367 368 /* Init SEC Engine which will be used by SiP */ 369 if (is_sec_enabled()) { 370 sec_init(NXP_CAAM_ADDR); 371 } else { 372 INFO("SEC is disabled.\n"); 373 } 374 } 375 376 #ifdef NXP_WDOG_RESTART 377 static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags, 378 void *handle, void *cookie) 379 { 380 uint8_t data = WDOG_RESET_FLAG; 381 382 wr_nv_app_data(WDT_RESET_FLAG_OFFSET, 383 (uint8_t *)&data, sizeof(data)); 384 385 mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT); 386 387 return 0; 388 } 389 #endif 390 391 void soc_runtime_setup(void) 392 { 393 #ifdef NXP_WDOG_RESTART 394 request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler); 395 #endif 396 } 397 398 /* This function returns the total number of cores in the SoC. */ 399 unsigned int get_tot_num_cores(void) 400 { 401 uint8_t num_clusters, cores_per_cluster; 402 403 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 404 return (num_clusters * cores_per_cluster); 405 } 406 407 /* This function returns the PMU IDLE Cluster mask. */ 408 unsigned int get_pmu_idle_cluster_mask(void) 409 { 410 uint8_t num_clusters, cores_per_cluster; 411 412 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 413 return ((1 << num_clusters) - 2); 414 } 415 416 /* This function returns the PMU Flush Cluster mask. */ 417 unsigned int get_pmu_flush_cluster_mask(void) 418 { 419 uint8_t num_clusters, cores_per_cluster; 420 421 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 422 return ((1 << num_clusters) - 2); 423 } 424 425 /* This function returns the PMU idle core mask. */ 426 unsigned int get_pmu_idle_core_mask(void) 427 { 428 return ((1 << get_tot_num_cores()) - 2); 429 } 430 431 /* Function to return the SoC SYS CLK */ 432 unsigned int get_sys_clk(void) 433 { 434 return NXP_SYSCLK_FREQ; 435 } 436 #endif 437