| d4ad3da0 | 24-Apr-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
refactor(tegra132): deprecate platform
The Tegra132 platforms have reached their end of life and are no longer used in the field. Internally and externally, all known programs have removed support f
refactor(tegra132): deprecate platform
The Tegra132 platforms have reached their end of life and are no longer used in the field. Internally and externally, all known programs have removed support for this legacy platform.
This change removes this platform from the Tegra tree as a result.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I72edb689293e23b63290cdcaef60468b90687a5a
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| deb875b5 | 26-Aug-2020 |
Sandeep Tripathy <sandeep.tripathy@broadcom.com> |
plat: tegra: Use generic ehf defines
Use common ehf file for generic frameworks like SDEI, RAS and extend plat specific defines using 'PLAT_EHF_DESC'.
Signed-off-by: Sandeep Tripathy <sandeep.tripa
plat: tegra: Use generic ehf defines
Use common ehf file for generic frameworks like SDEI, RAS and extend plat specific defines using 'PLAT_EHF_DESC'.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Change-Id: I8a8161c6030f8d226a8bdf0301e7fe6139f019a4
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| a565d16c | 04-Aug-2020 |
anzhou <anzhou@nvidia.com> |
Tegra: common: fixup the bl31 code size to be copied at reset
If the CPU doesn't run from BL31_BASE, the firmware needs to be copied from load address to BL31_BASE during cold boot. The size should
Tegra: common: fixup the bl31 code size to be copied at reset
If the CPU doesn't run from BL31_BASE, the firmware needs to be copied from load address to BL31_BASE during cold boot. The size should be the actual size of the code, which is indicated by the __RELA_END__ linker variable.
This patch updates the copy routine to use this variable as a result.
Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: Ie3a48dd54cda1dc152204903d609da3117a0ced9
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| c23f5e1c | 05-Aug-2020 |
anzhou <anzhou@nvidia.com> |
Tegra: common: disable GICC after domain off
The the GIC CPU interface should be disabled after cpu off. The Tegra power management code should mark the connected core as asleep as part of the CPU o
Tegra: common: disable GICC after domain off
The the GIC CPU interface should be disabled after cpu off. The Tegra power management code should mark the connected core as asleep as part of the CPU off sequence.
This patch disables the GICC after CPU off as a result.
Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: Ib1a3d8903f5e6d55bd2ee0c16134dbe2562235ea
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| 26c22a5e | 23-Jul-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: sanity check power state type
This patch sanity checks the power state type before use, from the platform's PSCI handler.
Verified with TFTF Standard Test Suite.
Change-Id: Icd45faac6c02
Tegra186: sanity check power state type
This patch sanity checks the power state type before use, from the platform's PSCI handler.
Verified with TFTF Standard Test Suite.
Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 923c221b | 26-Jun-2020 |
anzhou <anzhou@nvidia.com> |
Tegra: fixup CNTPS_TVAL_EL1 delay timer reads
The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical, decrementing timer as the source. The current logic incorrectly marks this as
Tegra: fixup CNTPS_TVAL_EL1 delay timer reads
The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical, decrementing timer as the source. The current logic incorrectly marks this as an incrementing timer, by negating the timer value.
This patch fixes the anomaly and updates the driver to remove this logic.
Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4
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