Merge "fix(intel): implement soc and lwsoc bridge control for burst speed" into integration

fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90

fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90d79a548163d198eea177d70dfbc0d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): update hand-off data to include agilex5 params

Update hand-off data structure to include agilex5
platform specific parameters.

Change-Id: Ic610e2d8da7488e49462293d13293e26520579e2
Sign

feat(intel): update hand-off data to include agilex5 params

Update hand-off data structure to include agilex5
platform specific parameters.

Change-Id: Ic610e2d8da7488e49462293d13293e26520579e2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): update mailbox SDM printout message" into integration

Merge "fix(intel): update the size with addition 0x8000 0000 base" into integration

Merge "fix(intel): fix bridge enable and disable function" into integration

Merge "fix(intel): update outdated code for Linux direct boot" into integration

fix(intel): update the size with addition 0x8000 0000 base

The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR
Thus, we need to add in the DDR base address which is 0x8000 0000.

Ch

fix(intel): update the size with addition 0x8000 0000 base

The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR
Thus, we need to add in the DDR base address which is 0x8000 0000.

Change-Id: I177596243e0616c6eadc2fa388e85e28692dc8f7
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4

fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4. bridge timeout workaround for F2SOC and F2SDRAM


Change-Id: Ide4210ff862531f82e083633af385b559ffbe16b
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df

fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df0e0a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc u

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): update Agilex5 DDR and IOSSM driver

DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2

feat(intel): update Agilex5 DDR and IOSSM driver

DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update mailbox SDM printout message

The printout message is misleading.
Update the message content and mask out the return code.

Change-Id: I08acb73894f8504b2773a19dbb10b42a65fcda5d
Sig

fix(intel): update mailbox SDM printout message

The printout message is misleading.
Update the message content and mask out the return code.

Change-Id: I08acb73894f8504b2773a19dbb10b42a65fcda5d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): update CCU configuration for Agilex5 platform

Update CCU configuration for DSU, FPGA2SOC, GIC_M, SMMU, PSS NOC, DCE0,
DCE1,DMI0, DMI1, L4 peripheral firewall, L4 system firewall, LWSOC2F

fix(intel): update CCU configuration for Agilex5 platform

Update CCU configuration for DSU, FPGA2SOC, GIC_M, SMMU, PSS NOC, DCE0,
DCE1,DMI0, DMI1, L4 peripheral firewall, L4 system firewall, LWSOC2FPGA,
SOCFPGA and TCU.

Change-Id: Id416d58b0115098b99a8dfdccb28a7d6f6747f75
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): add cache invalidation during BL31 initialization

During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the

fix(intel): add cache invalidation during BL31 initialization

During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the sync-up of stale
values in the cache to be synced with the main memory.
So, before the cache cleaning is done in u-boot proper,
it is invalidated in BL31 so that the cache data gets in
sync with u-boot proper memory address space and when
u-boot proper does its initialization which in turn clears
its BSS and heap section.

Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): bridge ack timing issue causing fpga config hung

Increase the timeout of waiting for bridge ack to solve the
fpga config hung.

Change-Id: I967af02b336c296206b4947be718953ff8ca30cf
Signe

fix(intel): bridge ack timing issue causing fpga config hung

Increase the timeout of waiting for bridge ack to solve the
fpga config hung.

Change-Id: I967af02b336c296206b4947be718953ff8ca30cf
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "fix(intel): update memcpy to memcpy_s" into integration

Merge "fix(intel): software workaround for bridge timeout" into integration

fix(intel): update memcpy to memcpy_s

memcpy does not check the dst_size which may
create vulnerable issue as it can overflow the buffer.
Using memcpy_s which check the dst_size will help to
reduce

fix(intel): update memcpy to memcpy_s

memcpy does not check the dst_size which may
create vulnerable issue as it can overflow the buffer.
Using memcpy_s which check the dst_size will help to
reduce the risk. Also, this memcpy is always 4 bytes
each time.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I413e6ae2ee9330501703c4cd63b7943c6f55b4c7

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fix(intel): add in missing ECC register

This patch is to add in missing ECC register (INITSTAT)

Change-Id: Iecf03dc9597ec2884901c132fb9cef7e90ab06a0
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.

fix(intel): add in missing ECC register

This patch is to add in missing ECC register (INITSTAT)

Change-Id: Iecf03dc9597ec2884901c132fb9cef7e90ab06a0
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge changes I23bdbbe1,Ic22ab741 into integration

* changes:
feat(intel): enable VAB support for Intel products
feat(intel): add in SHA384 authentication

feat(intel): enable VAB support for Intel products

This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.

Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b

feat(intel): enable VAB support for Intel products

This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.

Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b3aff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): add in SHA384 authentication

Add VAB SHA384 authentication implementation.

Change-Id: Ic22ab7416ffd0c514328d2815b136aa71ba96a84
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Sig

feat(intel): add in SHA384 authentication

Add VAB SHA384 authentication implementation.

Change-Id: Ic22ab7416ffd0c514328d2815b136aa71ba96a84
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update sip smc config addr for agilex5

Agilex5 DDR base address started from 0x8000 0000.
Thus the SIP_SMC_FPGA_CONFIG_ADDR shall be offset to
0x8040 0000.

Change-Id: I33a840cb8ebbe02bc

fix(intel): update sip smc config addr for agilex5

Agilex5 DDR base address started from 0x8000 0000.
Thus the SIP_SMC_FPGA_CONFIG_ADDR shall be offset to
0x8040 0000.

Change-Id: I33a840cb8ebbe02bc7ff9b1f5d452641af11e576
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): software workaround for bridge timeout

Hardware hdskack register does not return a correct value after
fence and drain of the bridge is done. Thus creates software
workaround.

Change-Id

fix(intel): software workaround for bridge timeout

Hardware hdskack register does not return a correct value after
fence and drain of the bridge is done. Thus creates software
workaround.

Change-Id: I78d8ee0596c3e7bd4883bfd6e92c883b8e369c10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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