1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex_system_manager.h" 13 #include <lib/utils_def.h> 14 #include <platform_def.h> 15 16 /* Platform Setting */ 17 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX 18 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 19 #define PLAT_PRIMARY_CPU 0 20 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 21 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT 22 #define PLAT_TIMER_BASE_ADDR 0xFFD01000 23 24 /* FPGA config helpers */ 25 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 26 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 27 28 /* QSPI Setting */ 29 #define CAD_QSPIDATA_OFST 0xff900000 30 #define CAD_QSPI_OFFSET 0xff8d2000 31 32 /* Register Mapping */ 33 #define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 34 #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) 35 36 #define SOCFPGA_MMC_REG_BASE 0xff808000 37 #define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100 38 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 39 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 40 #define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000 41 42 #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 43 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 44 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 45 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 46 47 /******************************************************************************* 48 * Platform memory map related constants 49 ******************************************************************************/ 50 #define DRAM_BASE (0x0) 51 #define DRAM_SIZE (0x80000000) 52 53 #define OCRAM_BASE (0xFFE00000) 54 #define OCRAM_SIZE (0x00040000) 55 56 #define MEM64_BASE (0x0100000000) 57 #define MEM64_SIZE (0x1F00000000) 58 59 #define DEVICE1_BASE (0x80000000) 60 #define DEVICE1_SIZE (0x60000000) 61 62 #define DEVICE2_BASE (0xF7000000) 63 #define DEVICE2_SIZE (0x08E00000) 64 65 #define DEVICE3_BASE (0xFFFC0000) 66 #define DEVICE3_SIZE (0x00008000) 67 68 #define DEVICE4_BASE (0x2000000000) 69 #define DEVICE4_SIZE (0x0100000000) 70 71 #define BL2_BASE (0xffe00000) 72 #define BL2_LIMIT (0xffe2b000) 73 74 #define BL31_BASE (0x1000) 75 #define BL31_LIMIT (0x81000) 76 77 /******************************************************************************* 78 * UART related constants 79 ******************************************************************************/ 80 #define PLAT_UART0_BASE (0xFFC02000) 81 #define PLAT_UART1_BASE (0xFFC02100) 82 83 /******************************************************************************* 84 * WDT related constants 85 ******************************************************************************/ 86 #define WDT_BASE (0xFFD00200) 87 88 /******************************************************************************* 89 * GIC related constants 90 ******************************************************************************/ 91 #define PLAT_GIC_BASE (0xFFFC0000) 92 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 93 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 94 #define PLAT_GICR_BASE 0 95 96 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 97 #define PLAT_HZ_CONVERT_TO_MHZ (1000000) 98 99 /******************************************************************************* 100 * SDMMC related pointer function 101 ******************************************************************************/ 102 #define SDMMC_READ_BLOCKS mmc_read_blocks 103 #define SDMMC_WRITE_BLOCKS mmc_write_blocks 104 105 /******************************************************************************* 106 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 107 * is done and HPS should trigger warm reset via RMR_EL3. 108 ******************************************************************************/ 109 #define L2_RESET_DONE_REG 0xFFD12218 110 111 /* Platform specific system counter */ 112 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 113 114 #endif /* PLAT_SOCFPGA_DEF_H */ 115