1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex5_memory_controller.h" 13 #include "agilex5_system_manager.h" 14 #include <platform_def.h> 15 16 /* Platform Setting */ 17 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 18 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 19 #define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ 20 #define XLAT_TABLES_V2 U(1) 21 #define PLAT_PRIMARY_CPU_A55 0x000 22 #define PLAT_PRIMARY_CPU_A76 0x200 23 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT 24 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 25 #define PLAT_L2_RESET_REQ 0xB007C0DE 26 #define PLAT_TIMER_BASE_ADDR 0x10D01000 27 28 /* System Counter */ 29 /* TODO: Update back to 400MHz. 30 * This shall be updated to read from L4 clock instead of hardcoded. 31 */ 32 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000) 33 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 34 35 /* FPGA config helpers */ 36 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000 37 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000 38 39 /* QSPI Setting */ 40 #define CAD_QSPIDATA_OFST 0x10900000 41 #define CAD_QSPI_OFFSET 0x108d2000 42 43 /* Register Mapping */ 44 #define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 45 #define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 46 47 #define SOCFPGA_MMC_REG_BASE 0x10808000 48 #define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 49 #define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 50 #define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 51 #define SOCFPGA_PINMUX_REG_BASE 0x10d13000 52 #define SOCFPGA_NAND_REG_BASE 0x10B80000 53 #define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000 54 55 #define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 56 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 57 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 58 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 59 60 /* Define maximum page size for NAND flash devices */ 61 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000) 62 63 /******************************************************************************* 64 * Platform memory map related constants 65 ******************************************************************************/ 66 #define DRAM_BASE (0x80000000) 67 #define DRAM_SIZE (0x80000000) 68 69 #define OCRAM_BASE (0x00000000) 70 #define OCRAM_SIZE (0x00080000) 71 72 #define MEM64_BASE (0x0080000000) 73 #define MEM64_SIZE (0x0080000000) 74 75 //128MB PSS 76 #define PSS_BASE (0x10000000) 77 #define PSS_SIZE (0x08000000) 78 79 //64MB MPFE 80 #define MPFE_BASE (0x18000000) 81 #define MPFE_SIZE (0x04000000) 82 83 //16MB CCU 84 #define CCU_BASE (0x1C000000) 85 #define CCU_SIZE (0x01000000) 86 87 //1MB GIC 88 #define GIC_BASE (0x1D000000) 89 #define GIC_SIZE (0x00100000) 90 91 #define BL2_BASE (0x00000000) 92 #define BL2_LIMIT (0x0007E000) 93 94 #define BL31_BASE (0x80000000) 95 #define BL31_LIMIT (0x82000000) 96 /******************************************************************************* 97 * UART related constants 98 ******************************************************************************/ 99 #define PLAT_UART0_BASE (0x10C02000) 100 #define PLAT_UART1_BASE (0x10C02100) 101 102 /******************************************************************************* 103 * WDT related constants 104 ******************************************************************************/ 105 #define WDT_BASE (0x10D00200) 106 107 /******************************************************************************* 108 * GIC related constants 109 ******************************************************************************/ 110 #define PLAT_GIC_BASE (0x1D000000) 111 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) 112 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) 113 #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) 114 115 #define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE 116 117 /******************************************************************************* 118 * SDMMC related pointer function 119 ******************************************************************************/ 120 #define SDMMC_READ_BLOCKS sdmmc_read_blocks 121 #define SDMMC_WRITE_BLOCKS sdmmc_write_blocks 122 123 /******************************************************************************* 124 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 125 * is done and HPS should trigger warm reset via RMR_EL3. 126 ******************************************************************************/ 127 #define L2_RESET_DONE_REG 0x10D12218 128 129 #endif /* PLAT_SOCFPGA_DEF_H */ 130