1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <scmi.h> 24 25 #include <def.h> 26 #include <plat_fdt.h> 27 #include <plat_private.h> 28 #include <plat_startup.h> 29 #include <pm_api_sys.h> 30 #include <pm_client.h> 31 32 static entry_point_info_t bl32_image_ep_info; 33 static entry_point_info_t bl33_image_ep_info; 34 35 /* 36 * Return a pointer to the 'entry_point_info' structure of the next image for 37 * the security state specified. BL33 corresponds to the non-secure image type 38 * while BL32 corresponds to the secure image type. A NULL pointer is returned 39 * if the image does not exist. 40 */ 41 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 42 { 43 assert(sec_state_is_valid(type)); 44 45 if (type == NON_SECURE) { 46 return &bl33_image_ep_info; 47 } 48 49 return &bl32_image_ep_info; 50 } 51 52 /* 53 * Set the build time defaults,if we can't find any config data. 54 */ 55 static inline void bl31_set_default_config(void) 56 { 57 bl32_image_ep_info.pc = BL32_BASE; 58 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 59 #if defined(SPD_opteed) 60 /* NS dtb addr passed to optee_os */ 61 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 62 #endif 63 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 64 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 65 DISABLE_ALL_EXCEPTIONS); 66 } 67 68 /* 69 * Perform any BL31 specific platform actions. Here is an opportunity to copy 70 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 71 * are lost (potentially). This needs to be done before the MMU is initialized 72 * so that the memory layout can be used while creating page tables. 73 */ 74 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 75 u_register_t arg2, u_register_t arg3) 76 { 77 (void)arg0; 78 (void)arg1; 79 (void)arg2; 80 (void)arg3; 81 uint32_t uart_clock; 82 int32_t rc; 83 84 board_detection(); 85 86 /* FIXME */ 87 switch (platform_id) { 88 case SPP: 89 switch (platform_version) { 90 case SPP_PSXC_MMI_V2_0: 91 cpu_clock = 770000; 92 break; 93 case SPP_PSXC_MMI_V3_0: 94 cpu_clock = 908000; 95 break; 96 default: 97 panic(); 98 } 99 break; 100 case SPP_MMD: 101 switch (platform_version) { 102 case SPP_PSXC_ISP_AIE_V2_0: 103 case SPP_PSXC_MMD_AIE_FRZ_EA: 104 case SPP_PSXC_MMD_AIE_V3_0: 105 cpu_clock = 760000; 106 break; 107 default: 108 panic(); 109 } 110 break; 111 case EMU: 112 case EMU_MMD: 113 cpu_clock = 112203; 114 break; 115 case QEMU: 116 /* Random values now */ 117 cpu_clock = 3333333; 118 break; 119 case SILICON: 120 cpu_clock = 100000000; 121 break; 122 default: 123 panic(); 124 } 125 126 uart_clock = get_uart_clk(); 127 128 if (CONSOLE_IS(pl011_0) || CONSOLE_IS(pl011_1)) { 129 static console_t _runtime_console; 130 131 /* Initialize the console to provide early debug support */ 132 rc = console_pl011_register(UART_BASE, uart_clock, 133 UART_BAUDRATE, 134 &_runtime_console); 135 if (rc == 0) { 136 panic(); 137 } 138 139 console_set_scope(&_runtime_console, CONSOLE_FLAG_BOOT | 140 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 141 } else if (CONSOLE_IS(dcc)) { 142 /* Initialize the dcc console for debug. 143 * dcc is over jtag and does not configures uart0 or uart1. 144 */ 145 rc = console_dcc_register(); 146 if (rc == 0) { 147 panic(); 148 } 149 } else { 150 /* Making MISRA C 2012 15.7 compliant */ 151 } 152 153 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 154 platform_version / 10U, platform_version % 10U); 155 156 /* Initialize the platform config for future decision making */ 157 config_setup(); 158 159 /* 160 * Do initial security configuration to allow DRAM/device access. On 161 * Base only DRAM security is programmable (via TrustZone), but 162 * other platforms might have more programmable security devices 163 * present. 164 */ 165 166 /* Populate common information for BL32 and BL33 */ 167 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 168 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 169 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 170 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 171 bl31_set_default_config(); 172 173 long rev_var = cpu_get_rev_var(); 174 175 INFO("CPU Revision = 0x%lx\n", rev_var); 176 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 177 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 178 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 179 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 180 181 } 182 183 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 184 185 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 186 { 187 static uint32_t index; 188 uint32_t i; 189 190 /* Validate 'handler' and 'id' parameters */ 191 if (handler == NULL || index >= MAX_INTR_EL3) { 192 return -EINVAL; 193 } 194 195 /* Check if a handler has already been registered */ 196 for (i = 0; i < index; i++) { 197 if (id == type_el3_interrupt_table[i].id) { 198 return -EALREADY; 199 } 200 } 201 202 type_el3_interrupt_table[index].id = id; 203 type_el3_interrupt_table[index].handler = handler; 204 205 index++; 206 207 return 0; 208 } 209 210 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 211 void *handle, void *cookie) 212 { 213 (void)id; 214 uint32_t intr_id; 215 uint32_t i; 216 interrupt_type_handler_t handler = NULL; 217 218 intr_id = plat_ic_get_pending_interrupt_id(); 219 220 for (i = 0; i < MAX_INTR_EL3; i++) { 221 if (intr_id == type_el3_interrupt_table[i].id) { 222 handler = type_el3_interrupt_table[i].handler; 223 } 224 } 225 226 if (handler != NULL) { 227 (void)handler(intr_id, flags, handle, cookie); 228 } 229 230 return 0; 231 } 232 233 void bl31_platform_setup(void) 234 { 235 prepare_dtb(); 236 237 /* Initialize the gic cpu and distributor interfaces */ 238 plat_gic_driver_init(); 239 plat_gic_init(); 240 241 if (platform_id != EMU) { 242 init_scmi_server(); 243 } 244 } 245 246 void bl31_plat_runtime_setup(void) 247 { 248 uint64_t flags = 0; 249 int32_t rc; 250 251 set_interrupt_rm_flag(flags, NON_SECURE); 252 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 253 rdo_el3_interrupt_handler, flags); 254 if (rc != 0) { 255 panic(); 256 } 257 } 258 259 /* 260 * Perform the very early platform specific architectural setup here. 261 */ 262 void bl31_plat_arch_setup(void) 263 { 264 const mmap_region_t bl_regions[] = { 265 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 266 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 267 MT_MEMORY | MT_RW | MT_NS), 268 #endif 269 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 270 MT_MEMORY | MT_RW | MT_SECURE), 271 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 272 MT_CODE | MT_SECURE), 273 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 274 MT_RO_DATA | MT_SECURE), 275 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 276 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 277 {0} 278 }; 279 280 setup_page_tables(bl_regions, plat_get_mmap()); 281 enable_mmu(0); 282 } 283