1 /* 2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/cadence/cdns_sdmmc.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/synopsys/dw_mmc.h> 18 #include <drivers/ti/uart/uart_16550.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 22 #include "agilex5_clock_manager.h" 23 #include "agilex5_memory_controller.h" 24 #include "agilex5_mmc.h" 25 #include "agilex5_pinmux.h" 26 #include "agilex5_system_manager.h" 27 #include "ccu/ncore_ccu.h" 28 #include "combophy/combophy.h" 29 #include "nand/nand.h" 30 #include "qspi/cadence_qspi.h" 31 #include "sdmmc/sdmmc.h" 32 #include "socfpga_emac.h" 33 #include "socfpga_f2sdram_manager.h" 34 #include "socfpga_handoff.h" 35 #include "socfpga_mailbox.h" 36 #include "socfpga_private.h" 37 #include "socfpga_reset_manager.h" 38 #include "socfpga_ros.h" 39 #include "socfpga_vab.h" 40 #include "wdt/watchdog.h" 41 42 43 /* Declare mmc_info */ 44 static struct mmc_device_info mmc_info; 45 46 /* Declare cadence idmac descriptor */ 47 extern struct cdns_idmac_desc cdns_desc[8] __aligned(32); 48 49 const mmap_region_t agilex_plat_mmap[] = { 50 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 51 MT_MEMORY | MT_RW | MT_NS), 52 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, 53 MT_DEVICE | MT_RW | MT_NS), 54 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, 55 MT_DEVICE | MT_RW | MT_SECURE), 56 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 57 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 58 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, 59 MT_DEVICE | MT_RW | MT_SECURE), 60 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 61 MT_DEVICE | MT_RW | MT_NS), 62 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, 63 MT_DEVICE | MT_RW | MT_SECURE), 64 {0}, 65 }; 66 67 boot_source_type boot_source = BOOT_SOURCE; 68 69 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 70 u_register_t x2, u_register_t x4) 71 { 72 static console_t console; 73 74 handoff reverse_handoff_ptr = { 0 }; 75 76 generic_delay_timer_init(); 77 config_clkmgr_handoff(&reverse_handoff_ptr); 78 mailbox_init(); 79 enable_nonsecure_access(); 80 81 deassert_peripheral_reset(); 82 if (combo_phy_init(&reverse_handoff_ptr) != 0) { 83 ERROR("Combo Phy initialization failed\n"); 84 } 85 86 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 87 PLAT_BAUDRATE, &console); 88 89 /* Store magic number */ 90 // TODO: Temp workaround to ungate testing 91 // mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ); 92 93 if (!intel_mailbox_is_fpga_not_ready()) { 94 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK | 95 FPGA2SOC_MASK | F2SDRAM0_MASK); 96 } 97 } 98 99 void bl2_el3_plat_arch_setup(void) 100 { 101 handoff reverse_handoff_ptr; 102 unsigned long offset = 0; 103 104 struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, get_mmc_clk()); 105 106 mmc_info.mmc_dev_type = MMC_DEVICE_TYPE; 107 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 108 109 /* Request ownership and direct access to QSPI */ 110 mailbox_hps_qspi_enable(); 111 112 switch (boot_source) { 113 case BOOT_SOURCE_SDMMC: 114 NOTICE("SDMMC boot\n"); 115 sdmmc_init(&reverse_handoff_ptr, ¶ms, &mmc_info); 116 socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE); 117 break; 118 119 case BOOT_SOURCE_QSPI: 120 NOTICE("QSPI boot\n"); 121 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 122 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 123 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 124 if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) { 125 offset = PLAT_QSPI_DATA_BASE; 126 } 127 socfpga_io_setup(boot_source, offset); 128 break; 129 130 case BOOT_SOURCE_NAND: 131 NOTICE("NAND boot\n"); 132 nand_init(&reverse_handoff_ptr); 133 socfpga_io_setup(boot_source, PLAT_NAND_DATA_BASE); 134 break; 135 136 default: 137 ERROR("Unsupported boot source\n"); 138 panic(); 139 break; 140 } 141 } 142 143 uint32_t get_spsr_for_bl33_entry(void) 144 { 145 unsigned long el_status; 146 unsigned int mode; 147 uint32_t spsr; 148 149 /* Figure out what mode we enter the non-secure world in */ 150 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 151 el_status &= ID_AA64PFR0_ELX_MASK; 152 153 mode = (el_status) ? MODE_EL2 : MODE_EL1; 154 155 /* 156 * TODO: Consider the possibility of specifying the SPSR in 157 * the FIP ToC and allowing the platform to have a say as 158 * well. 159 */ 160 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 161 return spsr; 162 } 163 164 int bl2_plat_handle_post_image_load(unsigned int image_id) 165 { 166 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 167 168 assert(bl_mem_params); 169 170 #if SOCFPGA_SECURE_VAB_AUTH 171 /* 172 * VAB Authentication start here. 173 * If failed to authenticate, shall not proceed to process BL31 and hang. 174 */ 175 int ret = 0; 176 177 ret = socfpga_vab_init(image_id); 178 if (ret < 0) { 179 ERROR("SOCFPGA VAB Authentication failed\n"); 180 wfi(); 181 } 182 #endif 183 184 switch (image_id) { 185 case BL33_IMAGE_ID: 186 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 187 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 188 break; 189 default: 190 break; 191 } 192 193 return 0; 194 } 195 196 /******************************************************************************* 197 * Perform any BL3-1 platform setup code 198 ******************************************************************************/ 199 void bl2_platform_setup(void) 200 { 201 } 202